archive
This commit is contained in:
Elliot Nunn
parent
0760db7b89
commit
45787c7d0a
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@ -1885,7 +1885,7 @@ finish_old_world
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sync
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setup_0x1160
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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lwz r27, 0x0630(r1)
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lwz r27, 0x009c(r27)
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bl PagingL2PWithoutBATs
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@ -1897,7 +1897,7 @@ setup_0x1160
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sync
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setup_0x1188
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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lwz r27, 0x0630(r1)
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lwz r27, 0x00a0(r27)
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lis r19, 0x00
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@ -1914,7 +1914,7 @@ setup_0x11a0
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sync
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setup_0x11bc
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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cmplw r27, r19
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addi r27, r27, -0x1000
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bgt setup_0x11a0
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@ -1929,7 +1929,7 @@ setup_0x11bc
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sync
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setup_0x11f0
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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_log 'Nanokernel replaced. Returning to boot process^n'
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@ -19,7 +19,7 @@ ecDataPageFault equ 20 ; ExceptionMemRetried
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ecDataWriteViolation equ 21 ; ExceptionMemRetried
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ecDataSupAccessViolation equ 22 ; ExceptionMemRetried
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ecDataSupWriteViolation equ 23 ; ?
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ecUnknown24 equ 24 ; ExceptionMemRetried
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ecAlignment equ 24 ; ExceptionMemRetried
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@ -1070,7 +1070,7 @@ IntAlignment ; OUTSIDE REFERER
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addi r23, r1, KDP.VecBaseMemRetry
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bne major_0x03548_0x20
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bne ThrowAlignmentException
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; DSISR for misaligned X-form instruction:
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@ -1087,7 +1087,7 @@ FDP_TableBase equ 0xa00
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; Get the FDP and F.O. if we were in MSR_LE mode
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lwz r25, KDP.PA_FDP(r1)
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bne major_0x03548_0x20
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bne ThrowAlignmentException
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rlwinm. r21, r27, 17, 30, 31 ; evaluate hi two bits of XO (or 0 for d-form?)
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@ -1139,7 +1139,8 @@ FDP_TableBase equ 0xa00
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IcbiNextBlock ; msr r14 // ; OUTSIDE REFERER
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IcbiNextBlock ; msr r14 //
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sync
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mtmsr r14
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isync
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@ -1149,14 +1150,18 @@ IcbiNextBlock ; msr r14 // ; OUTSIDE REFERER
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isync
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blr
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major_0x03548_0x20 ; OUTSIDE REFERER
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li r8, 0x00
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lis r17, -0x100
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ThrowAlignmentException
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li r8, 0
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lis r17, 0xFF00
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mtcr r8
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mr r19, r18
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rlwimi r17, r27, 7, 31, 31
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xori r17, r17, 0x01
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li r8, ecUnknown24
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rlwimi r17, r27, 7, 31, 31 ; why ~DSISR[6]... those DSISR bytes are reserved?
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xori r17, r17, 1
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li r8, ecAlignment
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b ExceptionMemRetried
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@ -1250,14 +1255,18 @@ MemRetryDSI_0x100
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beql IntPanicIsland
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mfsprg r28, 2
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mtlr r28
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bne cr7, MemRetryDSI_0x144
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bc BO_IF_NOT, 30, MemRetryDSI_0x144
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; "Ignore write to ROM", for example
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mfspr r28, srr0
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addi r28, r28, 0x04
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lwz r26, 0x0e90(r1)
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addi r28, r28, 4
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lwz r26, KDP.NanoKernelInfo + NKNanoKernelInfo.QuietWriteCount(r1)
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mtspr srr0, r28
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addi r26, r26, 0x01
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stw r26, 0x0e90(r1)
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b MemRetryDSI_0x19c
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addi r26, r26, 1
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stw r26, KDP.NanoKernelInfo + NKNanoKernelInfo.QuietWriteCount(r1)
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b MemRetryDSI_GracefulExit
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MemRetryDSI_0x144
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andi. r28, r31, 0x03
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@ -1285,7 +1294,7 @@ MemRetryDSI_0x158
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mtlr r28
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mtspr srr1, r29
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MemRetryDSI_0x19c
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MemRetryDSI_GracefulExit
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mfsprg r1, 1
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rlwinm r26, r25, 30, 24, 31
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rfi
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@ -1296,15 +1305,18 @@ MemRetryDSI_0x1c8
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andis. r28, r31, 0x8010
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bne MemRetryMachineCheck_0x14c
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_Lock PSA.HTABLock, scratch1=r28, scratch2=r31
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bl PagingFunc1
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_Lock PSA.HTABLock, scratch1=r28, scratch2=r31
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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_AssertAndRelease PSA.HTABLock, scratch=r28
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mfsprg r28, 2
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mtlr r28
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beq MemRetryDSI_0x19c
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beq MemRetryDSI_GracefulExit
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li r8, ecDataInvalidAddress
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bge ExceptionMemRetried
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li r8, ecDataPageFault
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b ExceptionMemRetried
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@ -1337,10 +1349,13 @@ MemRetryMachineCheck ; OUTSIDE REFERER
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_log '^n'
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mr r8, r28
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lwz r1, EWA.PA_KDP(r1)
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lwz r27, 0x0694(r1)
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subf r28, r19, r27
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cmpwi r28, -0x10
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blt MemRetryMachineCheck_0x14c
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cmpwi r28, 0x10
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bgt MemRetryMachineCheck_0x14c
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@ -1350,7 +1365,9 @@ MemRetryMachineCheck ; OUTSIDE REFERER
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lwz r28, 0x0e98(r1)
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addi r28, r28, 0x01
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stw r28, 0x0e98(r1)
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lwz r29, 0x0698(r1)
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li r28, 0x00
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stw r28, 0x0000(r29)
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mfspr r28, pvr
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@ -1394,7 +1411,7 @@ IntISI ; OUTSIDE REFERER
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_Lock PSA.HTABLock, scratch1=r28, scratch2=r31
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mr r27, r10
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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_AssertAndRelease PSA.HTABLock, scratch=r28
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mfsprg r8, 0
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bne major_0x039dc
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@ -1499,7 +1516,7 @@ PIHDSI ; OUTSIDE REFERER
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_Lock PSA.HTABLock, scratch1=r28, scratch2=r31
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mfspr r27, dar
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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_AssertAndRelease PSA.HTABLock, scratch=r28
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mfsprg r8, 0
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bne major_0x039dc
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@ -5,7 +5,7 @@ Local_Panic set *
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align 5
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PagingFunc1 ; OUTSIDE REFERER
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GetMeAccessToThisPage ; Page *r27 // success cr0.eq ; OUTSIDE REFERER
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mfsprg r29, 0
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mflr r28
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stw r8, -0x00dc(r29)
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@ -940,7 +940,7 @@ print_memory_logical_0x8
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print_memory_logical_0x24
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mr r27, r16
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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beq print_memory_logical_0x5c
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blt print_memory_logical_0x48
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_log '..'
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@ -974,7 +974,7 @@ print_memory_logical_0x84
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print_memory_logical_0xac
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mr r27, r16
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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li r8, 0x20
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bne print_memory_logical_0xdc
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bl PagingL2PWithoutBATs
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@ -1868,7 +1868,7 @@ VMLastExportedFunc_0xd7
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mr r14, r26
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mflr r6
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slwi r27, r4, 12
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bl PagingFunc1
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bl GetMeAccessToThisPage ; Page *r27 // success cr0.eq
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bnel Local_Panic
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mr r27, r7
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mr r29, r8
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@ -0,0 +1,137 @@
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MRLoad1241
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lbz mrScratch, -8(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 8, 0xFF000000
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MRLoad241
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lhz mrScratch, -7(mrBase)
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subi mrCtr, mrCtr, 4
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rlwimi mrHigh, mrScratch, 24, 0x00FFFF00
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b MRLoad41
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MRLoad141
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lbz mrScratch, -6(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 24, 0x0000FF00
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MRLoad41
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lwz mrScratch, -5(mrBase)
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subi mrCtr, mrCtr, 8
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rlwimi mrHigh, mrScratch, 24, 0x000000FF
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rlwimi mrLow, mrScratch, 24, 0xFFFFFF00
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b MRLoad1
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MRLoad1421
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lbz mrScratch, -8(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 8, 0xFF000000
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MRLoad421
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lwz mrScratch, -7(mrBase)
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subi mrCtr, mrCtr, 8
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rlwimi mrHigh, mrScratch, 8, 0x00FFFFFF
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rlwimi mrLow, mrScratch, 8, 0xFF000000
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b MRLoad21
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MRLoad1221
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lbz mrScratch, -6(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 24, 0x0000FF00
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MRLoad221
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lhz mrScratch, -5(mrBase)
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subi mrCtr, mrCtr, 4
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rlwimi mrHigh, mrScratch, 8, 0x000000FF
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rlwimi mrLow, mrScratch, 8, 0xFF000000
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b MRLoad21
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MRLoad121
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lbz mrScratch, -4(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrLow, mrScratch, 8, 0xFF000000
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MRLoad21
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lhz mrScratch, -3(mrBase)
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subi mrCtr, mrCtr, 4
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rlwimi mrLow, mrScratch, 24, 0x00FFFF00
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b MRLoad1
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MRLoad11
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lbz mrScratch, -2(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrLow, mrScratch, 24, 0x0000FF00
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MRLoad1
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lbz mrScratch, -1(mrBase)
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rlwimi mrLow, mrScratch, 0, 0x000000FF
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b MRExecuted
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MRLoad242
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lhz mrScratch, -8(mrBase)
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subi mrCtr, mrCtr, 4
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rlwimi mrHigh, mrScratch, 16, 0xFFFF0000
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b MRLoad42
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MRLoad142
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lbz mrScratch, -7(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 16, 0x00FF0000
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MRLoad42
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lwz mrScratch, -6(mrBase)
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subi mrCtr, mrCtr, 8
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rlwimi mrHigh, mrScratch, 16, 0x0000FFFF
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rlwimi mrLow, mrScratch, 16, 0xFFFF0000
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b MRLoad2
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MRLoad122
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lbz mrScratch, -5(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 0, 0x000000FF
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b MRLoad22
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MRLoad12
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lbz mrScratch, -3(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrLow, mrScratch, 16, 0x00FF0000
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b MRLoad2
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MRLoad44
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lwz mrHigh, -8(mrBase)
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subi mrCtr, mrCtr, 8
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lwz mrLow, -4(mrBase)
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b MRExecuted
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MRLoad124
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lbz mrScratch, -7(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 16, 0x00FF0000
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MRLoad24
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lhz mrScratch, -6(mrBase)
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subi mrCtr, mrCtr, 4
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rlwimi mrHigh, mrScratch, 0, 0x0000FFFF
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lwz mrLow, -4(mrBase)
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b MRExecuted
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MRLoad14
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lbz mrScratch, -5(mrBase)
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subi mrCtr, mrCtr, 2
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rlwimi mrHigh, mrScratch, 0, 0x000000FF
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lwz mrLow, -4(mrBase)
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b MRExecuted
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MRLoad4
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bc BO_IF, 23, @atomic
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lwz mrLow, -4(mrBase)
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b MRExecuted
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@atomic
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li mrScratch, -4
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lwarx mrScratch, mrBase
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b MRExecuted
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MRLoad8
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lwz mrLow, -8(mrBase)
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lwz mrHigh, -4(mrBase)
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b MRExecuted
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@ -151,6 +151,12 @@ MRLoadVector
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_bset r11, r11, 6
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blr
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MRStore1241
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srwi mrScratch, mrHigh, 24
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stb mrScratch, -8(mrBase)
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@ -0,0 +1,314 @@
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FDP_03ec
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lbz r23, -0x0008(r19)
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subi r17, r17, 2
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insrwi r20, r23, 8, 0
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FDP_03f8
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lhz r23, -0x0007(r19)
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subi r17, r17, 4
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insrwi r20, r23, 16, 8
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b FDP_0414
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FDP_0408
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lbz r23, -0x0006(r19)
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subi r17, r17, 2
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insrwi r20, r23, 8, 16
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FDP_0414
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lwz r23, -0x0005(r19)
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subi r17, r17, 8
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inslwi r20, r23, 8, 24
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insrwi r21, r23, 24, 0
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b FDP_0490
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FDP_0428
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lbz r23, -0x0008(r19)
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subi r17, r17, 2
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insrwi r20, r23, 8, 0
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FDP_0434
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lwz r23, -0x0007(r19)
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subi r17, r17, 8
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inslwi r20, r23, 24, 8
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insrwi r21, r23, 8, 0
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b FDP_0474
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FDP_0448
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lbz r23, -0x0006(r19)
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subi r17, r17, 2
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insrwi r20, r23, 8, 16
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FDP_0454
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lhz r23, -0x0005(r19)
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subi r17, r17, 4
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rlwimi r20, r23, 24, 24, 31
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insrwi r21, r23, 8, 0
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b FDP_0474
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FDP_0468
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lbz r23, -0x0004(r19)
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subi r17, r17, 2
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insrwi r21, r23, 8, 0
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FDP_0474
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lhz r23, -0x0003(r19)
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subi r17, r17, 4
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insrwi r21, r23, 16, 8
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b FDP_0490
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FDP_0484
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lbz r23, -0x0002(r19)
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subi r17, r17, 2
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insrwi r21, r23, 8, 16
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FDP_0490
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lbz r23, -0x0001(r19)
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insrwi r21, r23, 8, 24
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b FDP_011C
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FDP_049c
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lhz r23, -0x0008(r19)
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subi r17, r17, 4
|
||||
insrwi r20, r23, 16, 0
|
||||
b FDP_04B8
|
||||
|
||||
|
||||
FDP_04ac
|
||||
lbz r23, -0x0007(r19)
|
||||
subi r17, r17, 2
|
||||
insrwi r20, r23, 8, 8
|
||||
FDP_04b8
|
||||
lwz r23, -0x0006(r19)
|
||||
subi r17, r17, 8
|
||||
inslwi r20, r23, 16, 16
|
||||
insrwi r21, r23, 16, 0
|
||||
b FDP_0114
|
||||
|
||||
|
||||
FDP_04cc
|
||||
lbz r23, -0x0005(r19)
|
||||
subi r17, r17, 2
|
||||
insrwi r20, r23, 8, 24
|
||||
b FDP_0108
|
||||
|
||||
|
||||
FDP_04dc
|
||||
lbz r23, -0x0003(r19)
|
||||
subi r17, r17, 2
|
||||
insrwi r21, r23, 8, 8
|
||||
b FDP_0114
|
||||
|
||||
|
||||
FDP_04ec
|
||||
lwz r20, -0x0008(r19)
|
||||
subi r17, r17, 8
|
||||
lwz r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_04fc
|
||||
lbz r23, -0x0007(r19)
|
||||
subi r17, r17, 2
|
||||
insrwi r20, r23, 8, 8
|
||||
FDP_0508
|
||||
lhz r23, -0x0006(r19)
|
||||
subi r17, r17, 4
|
||||
insrwi r20, r23, 16, 16
|
||||
lwz r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_051c
|
||||
lbz r23, -0x0005(r19)
|
||||
subi r17, r17, 2
|
||||
insrwi r20, r23, 8, 24
|
||||
lwz r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0530
|
||||
bso cr5, FDP_053C
|
||||
lwz r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_053c
|
||||
li r23, -4
|
||||
lwarx r21, r23, r19
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0548
|
||||
lwz r20, -0x0008(r19)
|
||||
lwz r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0554
|
||||
clrrwi r23, r25, 10
|
||||
rlwimi r23, r17, 14, 24, 28
|
||||
addi r23, r23, 9760
|
||||
mtlr r23
|
||||
mr r23, r18
|
||||
oris r11, r11, 0x0200
|
||||
blr
|
||||
|
||||
|
||||
FDP_0570
|
||||
srwi r23, r20, 24
|
||||
stb r23, -0x0008(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_057c
|
||||
srwi r23, r20, 8
|
||||
sth r23, -0x0007(r19)
|
||||
subi r17, r17, 4
|
||||
b FDP_0598
|
||||
|
||||
|
||||
FDP_058c
|
||||
srwi r23, r20, 8
|
||||
stb r23, -0x0006(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_0598
|
||||
srwi r23, r21, 8
|
||||
insrwi r23, r20, 8, 0
|
||||
stw r23, -0x0005(r19)
|
||||
subi r17, r17, 8
|
||||
stb r21, -0x0001(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_05b0
|
||||
srwi r23, r20, 24
|
||||
stb r23, -0x0008(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_05bc
|
||||
srwi r23, r21, 24
|
||||
insrwi r23, r20, 24, 0
|
||||
stw r23, -0x0007(r19)
|
||||
subi r17, r17, 8
|
||||
b FDP_05FC
|
||||
|
||||
|
||||
FDP_05d0
|
||||
srwi r23, r20, 8
|
||||
stb r23, -0x0006(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_05dc
|
||||
srwi r23, r21, 24
|
||||
insrwi r23, r20, 8, 16
|
||||
sth r23, -0x0005(r19)
|
||||
subi r17, r17, 4
|
||||
b FDP_05FC
|
||||
|
||||
|
||||
FDP_05f0
|
||||
srwi r23, r21, 24
|
||||
stb r23, -0x0004(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_05fc
|
||||
srwi r23, r21, 8
|
||||
sth r23, -0x0003(r19)
|
||||
subi r17, r17, 4
|
||||
stb r21, -0x0001(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0610
|
||||
srwi r23, r21, 8
|
||||
stb r23, -0x0002(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_061c
|
||||
stb r21, -0x0001(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0624
|
||||
srwi r23, r20, 16
|
||||
sth r23, -0x0008(r19)
|
||||
subi r17, r17, 4
|
||||
b FDP_0640
|
||||
|
||||
|
||||
FDP_0634
|
||||
srwi r23, r20, 16
|
||||
stb r23, -0x0007(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_0640
|
||||
srwi r23, r21, 16
|
||||
insrwi r23, r20, 16, 0
|
||||
stw r23, -0x0006(r19)
|
||||
subi r17, r17, 8
|
||||
sth r21, -0x0002(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0658
|
||||
stb r20, -0x0005(r19)
|
||||
subi r17, r17, 2
|
||||
b FDP_00F4
|
||||
|
||||
|
||||
FDP_0664
|
||||
srwi r23, r21, 16
|
||||
stb r23, -0x0003(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_0670
|
||||
sth r21, -0x0002(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0678
|
||||
stw r20, -0x0008(r19)
|
||||
subi r17, r17, 8
|
||||
stw r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_0688
|
||||
srwi r23, r20, 16
|
||||
stb r23, -0x0007(r19)
|
||||
subi r17, r17, 2
|
||||
FDP_0694
|
||||
sth r20, -0x0006(r19)
|
||||
subi r17, r17, 4
|
||||
stw r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_06a4
|
||||
stb r20, -0x0005(r19)
|
||||
subi r17, r17, 2
|
||||
stw r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_06b4
|
||||
bso cr5, FDP_06C0
|
||||
stw r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_06c0
|
||||
li r23, -4
|
||||
stwcx. r21, r23, r19
|
||||
isync
|
||||
mfcr r23
|
||||
rlwimi r13, r23, 0, 0, 3
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_06d8
|
||||
stw r20, -0x0008(r19)
|
||||
stw r21, -0x0004(r19)
|
||||
b FDP_011C
|
||||
|
||||
|
||||
FDP_06e4
|
||||
clrrwi r23, r25, 10
|
||||
rlwimi r23, r17, 14, 24, 28
|
||||
addi r23, r23, 10784
|
||||
mtlr r23
|
||||
mr r23, r18
|
||||
oris r11, r11, 0x0200
|
||||
blr
|
||||
104
pdp.py
104
pdp.py
|
|
@ -85,22 +85,35 @@ def list_perms_ending_with(x):
|
|||
yield from list_perms_ending_with(nextlet + x)
|
||||
|
||||
|
||||
SPECIAL_LOADSTORE_RETURN_PATHS = ['2', '22']
|
||||
|
||||
def final_loadstore_list():
|
||||
def final_load_list():
|
||||
"""
|
||||
Big waterfall of loads/stores!
|
||||
Big waterfall of loads!
|
||||
"""
|
||||
the_list = []
|
||||
|
||||
for ender in '8421':
|
||||
for x in list_perms_ending_with(ender):
|
||||
if x not in SPECIAL_LOADSTORE_RETURN_PATHS:
|
||||
if x not in ('2','22'):
|
||||
the_list.append(x)
|
||||
|
||||
return list(reversed(the_list))
|
||||
|
||||
FINAL_LOADSTORE_LIST = final_loadstore_list()
|
||||
FINAL_LOAD_LIST = final_load_list()
|
||||
|
||||
def final_store_list():
|
||||
"""
|
||||
Big waterfall of stores!
|
||||
"""
|
||||
the_list = []
|
||||
|
||||
for ender in '8421':
|
||||
for x in list_perms_ending_with(ender):
|
||||
if x not in []:
|
||||
the_list.append(x)
|
||||
|
||||
return list(reversed(the_list))
|
||||
|
||||
FINAL_STORE_LIST = final_store_list()
|
||||
|
||||
|
||||
################################################################
|
||||
|
|
@ -160,7 +173,7 @@ def MRVectorAlignDispatchTable():
|
|||
|
||||
|
||||
def MRAlignLoads():
|
||||
waterfall = FINAL_LOADSTORE_LIST
|
||||
waterfall = FINAL_LOAD_LIST
|
||||
|
||||
for wi in range(len(waterfall)):
|
||||
sizes = waterfall[wi]
|
||||
|
|
@ -230,6 +243,81 @@ def MRAlignLoads():
|
|||
|
||||
print()
|
||||
|
||||
def MRAlignStores():
|
||||
waterfall = FINAL_STORE_LIST
|
||||
|
||||
for wi in range(len(waterfall)):
|
||||
sizes = waterfall[wi]
|
||||
|
||||
label('MRStore' + sizes)
|
||||
|
||||
sizes_as_list = [int(x) for x in sizes]
|
||||
this_size = sizes_as_list[0]
|
||||
total_size = sum(sizes_as_list)
|
||||
remain_size = sum(sizes_as_list[1:])
|
||||
|
||||
|
||||
MRAlignLoads()
|
||||
# PART 1: load a number of bytes equal to the first element in "sizes"
|
||||
|
||||
inst = {1: 'stb', 2: 'sth', 4: 'stw', 8: 'no way'}[this_size]
|
||||
|
||||
if sizes == '8': # special case
|
||||
directive('stw', 'mrLow', '-8(mrBase)')
|
||||
directive('stw', 'mrHigh', '-4(mrBase)')
|
||||
|
||||
elif remain_size == 4: # straight store!
|
||||
directive(inst, 'mrHigh', '-%d(mrBase)' % total_size)
|
||||
if len(sizes) > 1: directive('subi', 'mrCtr', 'mrCtr', 2 * this_size)
|
||||
|
||||
elif sizes == '4': # special case: emulate lwarx if asked
|
||||
directive('bc', 'BO_IF', 23, '@atomic')
|
||||
directive('stw', 'mrLow', '-4(mrBase)')
|
||||
directive('b', 'MRExecuted')
|
||||
label('@atomic')
|
||||
directive('li', 'mrScratch', -4)
|
||||
directive('stwcx.', 'mrScratch', 'mrBase')
|
||||
directive('isync')
|
||||
directive('mfcr', 'mrScratch')
|
||||
directive('rlwimi', 'r13', 'mrScratch', 0, '0xFF000000')
|
||||
|
||||
else: # arrange intermediate register then store it
|
||||
fiddler = 'rlwinm'
|
||||
|
||||
for regexponent, regname in [(0,'mrLow'), (4,'mrHigh')]:
|
||||
thisexponent = remain_size
|
||||
if regexponent >= thisexponent + this_size: continue
|
||||
if thisexponent >= regexponent + 4: continue
|
||||
|
||||
lshift = (regexponent - thisexponent) * 8
|
||||
|
||||
mask = (1 << (8 * this_size)) - 1
|
||||
|
||||
directive(fiddler, 'mrScratch', regname, normlshift(lshift), '0x%08X' % mask)
|
||||
fiddler = 'rlwimi'
|
||||
|
||||
directive(inst, 'mrScratch', '-%d(mrBase)' % total_size)
|
||||
if len(sizes) > 1: directive('subi', 'mrCtr', 'mrCtr', 2 * this_size)
|
||||
|
||||
|
||||
# PART 2: jump somewhere that will do the rest of the loads in "sizes"
|
||||
|
||||
if wi + 1 < len(waterfall) and waterfall[wi+1] == sizes[1:] and sizes[1:] != '4': # fall through
|
||||
# but beware the special case!
|
||||
pass
|
||||
|
||||
elif len(sizes[1:]) == 1: # special case: inline a single store instead of jumping
|
||||
inst = {1: 'stb', 2: 'sth', 4: 'stw', 8: 'no way'}[remain_size]
|
||||
directive(inst, 'mrLow', '-%d(mrBase)' % remain_size)
|
||||
directive('b', 'MRExecuted')
|
||||
|
||||
elif remain_size == 0: # finished executing
|
||||
directive('b', 'MRExecuted')
|
||||
|
||||
else:
|
||||
directive('b', 'MRStore' + sizes[1:])
|
||||
|
||||
print()
|
||||
|
||||
|
||||
|
||||
MRAlignStores()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,256 @@
|
|||
lvx v0, 0, r23
|
||||
lvx v1, 0, r23
|
||||
lvx v2, 0, r23
|
||||
lvx v3, 0, r23
|
||||
lvx v4, 0, r23
|
||||
lvx v5, 0, r23
|
||||
lvx v6, 0, r23
|
||||
lvx v7, 0, r23
|
||||
lvx v8, 0, r23
|
||||
lvx v9, 0, r23
|
||||
lvx v10, 0, r23
|
||||
lvx v11, 0, r23
|
||||
lvx v12, 0, r23
|
||||
lvx v13, 0, r23
|
||||
lvx v14, 0, r23
|
||||
lvx v15, 0, r23
|
||||
lvx v16, 0, r23
|
||||
lvx v17, 0, r23
|
||||
lvx v18, 0, r23
|
||||
lvx v19, 0, r23
|
||||
lvx v20, 0, r23
|
||||
lvx v21, 0, r23
|
||||
lvx v22, 0, r23
|
||||
lvx v23, 0, r23
|
||||
lvx v24, 0, r23
|
||||
lvx v25, 0, r23
|
||||
lvx v26, 0, r23
|
||||
lvx v27, 0, r23
|
||||
lvx v28, 0, r23
|
||||
lvx v29, 0, r23
|
||||
lvx v30, 0, r23
|
||||
lvx v31, 0, r23
|
||||
lvebx v0, 0, r23
|
||||
lvebx v1, 0, r23
|
||||
lvebx v2, 0, r23
|
||||
lvebx v3, 0, r23
|
||||
lvebx v4, 0, r23
|
||||
lvebx v5, 0, r23
|
||||
lvebx v6, 0, r23
|
||||
lvebx v7, 0, r23
|
||||
lvebx v8, 0, r23
|
||||
lvebx v9, 0, r23
|
||||
lvebx v10, 0, r23
|
||||
lvebx v11, 0, r23
|
||||
lvebx v12, 0, r23
|
||||
lvebx v13, 0, r23
|
||||
lvebx v14, 0, r23
|
||||
lvebx v15, 0, r23
|
||||
lvebx v16, 0, r23
|
||||
lvebx v17, 0, r23
|
||||
lvebx v18, 0, r23
|
||||
lvebx v19, 0, r23
|
||||
lvebx v20, 0, r23
|
||||
lvebx v21, 0, r23
|
||||
lvebx v22, 0, r23
|
||||
lvebx v23, 0, r23
|
||||
lvebx v24, 0, r23
|
||||
lvebx v25, 0, r23
|
||||
lvebx v26, 0, r23
|
||||
lvebx v27, 0, r23
|
||||
lvebx v28, 0, r23
|
||||
lvebx v29, 0, r23
|
||||
lvebx v30, 0, r23
|
||||
lvebx v31, 0, r23
|
||||
lvehx v0, 0, r23
|
||||
lvehx v1, 0, r23
|
||||
lvehx v2, 0, r23
|
||||
lvehx v3, 0, r23
|
||||
lvehx v4, 0, r23
|
||||
lvehx v5, 0, r23
|
||||
lvehx v6, 0, r23
|
||||
lvehx v7, 0, r23
|
||||
lvehx v8, 0, r23
|
||||
lvehx v9, 0, r23
|
||||
lvehx v10, 0, r23
|
||||
lvehx v11, 0, r23
|
||||
lvehx v12, 0, r23
|
||||
lvehx v13, 0, r23
|
||||
lvehx v14, 0, r23
|
||||
lvehx v15, 0, r23
|
||||
lvehx v16, 0, r23
|
||||
lvehx v17, 0, r23
|
||||
lvehx v18, 0, r23
|
||||
lvehx v19, 0, r23
|
||||
lvehx v20, 0, r23
|
||||
lvehx v21, 0, r23
|
||||
lvehx v22, 0, r23
|
||||
lvehx v23, 0, r23
|
||||
lvehx v24, 0, r23
|
||||
lvehx v25, 0, r23
|
||||
lvehx v26, 0, r23
|
||||
lvehx v27, 0, r23
|
||||
lvehx v28, 0, r23
|
||||
lvehx v29, 0, r23
|
||||
lvehx v30, 0, r23
|
||||
lvehx v31, 0, r23
|
||||
lvewx v0, 0, r23
|
||||
lvewx v1, 0, r23
|
||||
lvewx v2, 0, r23
|
||||
lvewx v3, 0, r23
|
||||
lvewx v4, 0, r23
|
||||
lvewx v5, 0, r23
|
||||
lvewx v6, 0, r23
|
||||
lvewx v7, 0, r23
|
||||
lvewx v8, 0, r23
|
||||
lvewx v9, 0, r23
|
||||
lvewx v10, 0, r23
|
||||
lvewx v11, 0, r23
|
||||
lvewx v12, 0, r23
|
||||
lvewx v13, 0, r23
|
||||
lvewx v14, 0, r23
|
||||
lvewx v15, 0, r23
|
||||
lvewx v16, 0, r23
|
||||
lvewx v17, 0, r23
|
||||
lvewx v18, 0, r23
|
||||
lvewx v19, 0, r23
|
||||
lvewx v20, 0, r23
|
||||
lvewx v21, 0, r23
|
||||
lvewx v22, 0, r23
|
||||
lvewx v23, 0, r23
|
||||
lvewx v24, 0, r23
|
||||
lvewx v25, 0, r23
|
||||
lvewx v26, 0, r23
|
||||
lvewx v27, 0, r23
|
||||
lvewx v28, 0, r23
|
||||
lvewx v29, 0, r23
|
||||
lvewx v30, 0, r23
|
||||
lvewx v31, 0, r23
|
||||
stvx v0, 0, r23
|
||||
stvx v1, 0, r23
|
||||
stvx v2, 0, r23
|
||||
stvx v3, 0, r23
|
||||
stvx v4, 0, r23
|
||||
stvx v5, 0, r23
|
||||
stvx v6, 0, r23
|
||||
stvx v7, 0, r23
|
||||
stvx v8, 0, r23
|
||||
stvx v9, 0, r23
|
||||
stvx v10, 0, r23
|
||||
stvx v11, 0, r23
|
||||
stvx v12, 0, r23
|
||||
stvx v13, 0, r23
|
||||
stvx v14, 0, r23
|
||||
stvx v15, 0, r23
|
||||
stvx v16, 0, r23
|
||||
stvx v17, 0, r23
|
||||
stvx v18, 0, r23
|
||||
stvx v19, 0, r23
|
||||
stvx v20, 0, r23
|
||||
stvx v21, 0, r23
|
||||
stvx v22, 0, r23
|
||||
stvx v23, 0, r23
|
||||
stvx v24, 0, r23
|
||||
stvx v25, 0, r23
|
||||
stvx v26, 0, r23
|
||||
stvx v27, 0, r23
|
||||
stvx v28, 0, r23
|
||||
stvx v29, 0, r23
|
||||
stvx v30, 0, r23
|
||||
stvx v31, 0, r23
|
||||
stvebx v0, 0, r23
|
||||
stvebx v1, 0, r23
|
||||
stvebx v2, 0, r23
|
||||
stvebx v3, 0, r23
|
||||
stvebx v4, 0, r23
|
||||
stvebx v5, 0, r23
|
||||
stvebx v6, 0, r23
|
||||
stvebx v7, 0, r23
|
||||
stvebx v8, 0, r23
|
||||
stvebx v9, 0, r23
|
||||
stvebx v10, 0, r23
|
||||
stvebx v11, 0, r23
|
||||
stvebx v12, 0, r23
|
||||
stvebx v13, 0, r23
|
||||
stvebx v14, 0, r23
|
||||
stvebx v15, 0, r23
|
||||
stvebx v16, 0, r23
|
||||
stvebx v17, 0, r23
|
||||
stvebx v18, 0, r23
|
||||
stvebx v19, 0, r23
|
||||
stvebx v20, 0, r23
|
||||
stvebx v21, 0, r23
|
||||
stvebx v22, 0, r23
|
||||
stvebx v23, 0, r23
|
||||
stvebx v24, 0, r23
|
||||
stvebx v25, 0, r23
|
||||
stvebx v26, 0, r23
|
||||
stvebx v27, 0, r23
|
||||
stvebx v28, 0, r23
|
||||
stvebx v29, 0, r23
|
||||
stvebx v30, 0, r23
|
||||
stvebx v31, 0, r23
|
||||
stvehx v0, 0, r23
|
||||
stvehx v1, 0, r23
|
||||
stvehx v2, 0, r23
|
||||
stvehx v3, 0, r23
|
||||
stvehx v4, 0, r23
|
||||
stvehx v5, 0, r23
|
||||
stvehx v6, 0, r23
|
||||
stvehx v7, 0, r23
|
||||
stvehx v8, 0, r23
|
||||
stvehx v9, 0, r23
|
||||
stvehx v10, 0, r23
|
||||
stvehx v11, 0, r23
|
||||
stvehx v12, 0, r23
|
||||
stvehx v13, 0, r23
|
||||
stvehx v14, 0, r23
|
||||
stvehx v15, 0, r23
|
||||
stvehx v16, 0, r23
|
||||
stvehx v17, 0, r23
|
||||
stvehx v18, 0, r23
|
||||
stvehx v19, 0, r23
|
||||
stvehx v20, 0, r23
|
||||
stvehx v21, 0, r23
|
||||
stvehx v22, 0, r23
|
||||
stvehx v23, 0, r23
|
||||
stvehx v24, 0, r23
|
||||
stvehx v25, 0, r23
|
||||
stvehx v26, 0, r23
|
||||
stvehx v27, 0, r23
|
||||
stvehx v28, 0, r23
|
||||
stvehx v29, 0, r23
|
||||
stvehx v30, 0, r23
|
||||
stvehx v31, 0, r23
|
||||
stvewx v0, 0, r23
|
||||
stvewx v1, 0, r23
|
||||
stvewx v2, 0, r23
|
||||
stvewx v3, 0, r23
|
||||
stvewx v4, 0, r23
|
||||
stvewx v5, 0, r23
|
||||
stvewx v6, 0, r23
|
||||
stvewx v7, 0, r23
|
||||
stvewx v8, 0, r23
|
||||
stvewx v9, 0, r23
|
||||
stvewx v10, 0, r23
|
||||
stvewx v11, 0, r23
|
||||
stvewx v12, 0, r23
|
||||
stvewx v13, 0, r23
|
||||
stvewx v14, 0, r23
|
||||
stvewx v15, 0, r23
|
||||
stvewx v16, 0, r23
|
||||
stvewx v17, 0, r23
|
||||
stvewx v18, 0, r23
|
||||
stvewx v19, 0, r23
|
||||
stvewx v20, 0, r23
|
||||
stvewx v21, 0, r23
|
||||
stvewx v22, 0, r23
|
||||
stvewx v23, 0, r23
|
||||
stvewx v24, 0, r23
|
||||
stvewx v25, 0, r23
|
||||
stvewx v26, 0, r23
|
||||
stvewx v27, 0, r23
|
||||
stvewx v28, 0, r23
|
||||
stvewx v29, 0, r23
|
||||
stvewx v30, 0, r23
|
||||
stvewx v31, 0, r23
|
||||
Loading…
Reference in New Issue