dingusppc/devices/serial/escc.h

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/*
DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
/** @file Enhanced Serial Communications Controller (ESCC) definitions. */
#ifndef ESCC_H
#define ESCC_H
#include <devices/common/hwcomponent.h>
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#include <devices/serial/chario.h>
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#include <cinttypes>
#include <memory>
#include <string>
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class DmaBidirChannel;
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/** ESCC register positions */
/* Please note that the registers below are provided
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by the Apple I/O controllers for accessing ESCC
in a more convenient way. Actual physical addresses
are controller dependent.
The registers are ordered according with the MacRISC
scheme used in the PCI Power Macintosh models.
Pre-PCI Macs uses the so-called compatibility
addressing. Please use compat_to_macrisc table
below for converting from compat to MacRISC.
*/
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enum EsccReg : uint8_t {
Port_B_Cmd = 0,
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Port_B_Data = 1, // direct access to WR8/RR8
Port_A_Cmd = 2,
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Port_A_Data = 3, // direct access to WR8/RR8
Enh_Reg_B = 4, // undocumented Apple extension
Enh_Reg_A = 5, // undocumented Apple extension
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};
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extern const uint8_t compat_to_macrisc[6];
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/** LocalTalk LTPC registers provided by a MacIO controller. */
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enum LocalTalkReg : uint8_t {
Rec_Count = 8,
Start_A = 9,
Start_B = 0xA,
Detect_AB = 0xB,
};
enum WR0Cmd : uint8_t {
Point_High = 1,
};
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/** ESCC reset commands. */
enum {
RESET_ESCC = 0xC0,
RESET_CH_A = 0x80,
RESET_CH_B = 0x40
};
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/** DPLL commands in WR14. */
enum {
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DPLL_NULL_CMD = 0,
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DPLL_ENTER_SRC_MODE = 1,
DPLL_RST_MISSING_CLK = 2,
DPLL_DISABLE = 3,
DPLL_SET_SRC_BGR = 4,
DPLL_SET_SRC_RTXC = 5,
DPLL_SET_FM_MODE = 6,
DPLL_SET_NRZI_MODE = 7
};
enum DpllMode : uint8_t {
NRZI = 0,
FM = 1
};
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/** ESCC Channel class. */
class EsccChannel {
public:
EsccChannel(std::string name) { this->name = name; };
~EsccChannel() = default;
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void attach_backend(int id);
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void reset(bool hw_reset);
uint8_t read_reg(int reg_num);
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void write_reg(int reg_num, uint8_t value);
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void send_byte(uint8_t value);
uint8_t receive_byte();
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private:
std::string name;
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uint8_t read_regs[16];
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uint8_t write_regs[16];
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uint8_t wr7_enh;
uint8_t dpll_active;
uint8_t dpll_mode;
uint8_t dpll_clock_src;
uint8_t brg_active;
uint8_t brg_clock_src;
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std::unique_ptr<CharIoBackEnd> chario;
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};
/** ESCC Controller class. */
class EsccController : public HWComponent {
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public:
EsccController();
~EsccController() = default;
static std::unique_ptr<HWComponent> create() {
return std::unique_ptr<EsccController>(new EsccController());
}
// ESCC registers access
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uint8_t read(uint8_t reg_offset);
void write(uint8_t reg_offset, uint8_t value);
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void dma_start();
void dma_stop();
void set_dma_channel(int ch_index, DmaBidirChannel *dma_ch) {
this->dma_ch[ch_index] = dma_ch;
};
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private:
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void reset();
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void write_internal(EsccChannel* ch, uint8_t value);
std::unique_ptr<EsccChannel> ch_a;
std::unique_ptr<EsccChannel> ch_b;
int reg_ptr; // register pointer for reading/writing (same for both channels)
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uint8_t master_int_cntrl;
uint8_t int_vec;
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DmaBidirChannel* dma_ch[4];
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};
#endif // ESCC_H