mesh: arbitration and selection commands.
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@ -21,6 +21,8 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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/** @file MESH (Macintosh Enhanced SCSI Hardware) controller emulation. */
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/** @file MESH (Macintosh Enhanced SCSI Hardware) controller emulation. */
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#include <core/timermanager.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/mesh.h>
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#include <devices/common/scsi/mesh.h>
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#include <devices/deviceregistry.h>
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#include <devices/deviceregistry.h>
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#include <loguru.hpp>
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#include <loguru.hpp>
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@ -34,6 +36,10 @@ int MeshController::device_postinit()
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{
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{
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this->bus_obj = dynamic_cast<ScsiBus*>(gMachineObj->get_comp_by_name("SCSI0"));
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this->bus_obj = dynamic_cast<ScsiBus*>(gMachineObj->get_comp_by_name("SCSI0"));
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this->int_ctrl = dynamic_cast<InterruptCtrl*>(
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gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
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this->irq_id = this->int_ctrl->register_dev_int(IntSrc::SCSI1);
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return 0;
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return 0;
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}
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}
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@ -51,12 +57,20 @@ void MeshController::reset(bool is_hard_reset)
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uint8_t MeshController::read(uint8_t reg_offset)
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uint8_t MeshController::read(uint8_t reg_offset)
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{
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{
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switch(reg_offset) {
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switch(reg_offset) {
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case MeshReg::Sequence:
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return this->cur_cmd;
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case MeshReg::BusStatus0:
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case MeshReg::BusStatus0:
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return this->bus_obj->test_ctrl_lines(0xFFU);
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return this->bus_obj->test_ctrl_lines(0xFFU);
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case MeshReg::BusStatus1:
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case MeshReg::BusStatus1:
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return this->bus_obj->test_ctrl_lines(0xE000U) >> 8;
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return this->bus_obj->test_ctrl_lines(0xE000U) >> 8;
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case MeshReg::Exception:
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return 0;
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case MeshReg::Error:
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return 0;
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case MeshReg::IntMask:
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case MeshReg::IntMask:
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return this->int_mask;
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return this->int_mask;
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case MeshReg::Interrupt:
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return this->int_stat;
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case MeshReg::MeshID:
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case MeshReg::MeshID:
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return this->chip_id; // tell them who we are
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return this->chip_id; // tell them who we are
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default:
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default:
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@ -93,6 +107,7 @@ void MeshController::write(uint8_t reg_offset, uint8_t value)
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break;
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break;
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case MeshReg::Interrupt:
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case MeshReg::Interrupt:
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this->int_stat &= ~(value & INT_MASK); // clear requested interrupt bits
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this->int_stat &= ~(value & INT_MASK); // clear requested interrupt bits
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update_irq();
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break;
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break;
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case MeshReg::SourceID:
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case MeshReg::SourceID:
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this->src_id = value;
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this->src_id = value;
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@ -103,6 +118,9 @@ void MeshController::write(uint8_t reg_offset, uint8_t value)
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case MeshReg::SyncParms:
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case MeshReg::SyncParms:
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this->sync_params = value;
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this->sync_params = value;
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break;
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break;
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case MeshReg::SelTimeOut:
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LOG_F(9, "MESH: selection timeout set to 0x%x", value);
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break;
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default:
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default:
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LOG_F(WARNING, "MESH: write to unimplemented register at offset 0x%x",
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LOG_F(WARNING, "MESH: write to unimplemented register at offset 0x%x",
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reg_offset);
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reg_offset);
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@ -111,20 +129,115 @@ void MeshController::write(uint8_t reg_offset, uint8_t value)
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void MeshController::perform_command(const uint8_t cmd)
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void MeshController::perform_command(const uint8_t cmd)
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{
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{
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this->cur_cmd = cmd & 0xF;
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this->cur_cmd = cmd;
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this->int_stat &= ~INT_CMD_DONE;
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this->int_stat &= ~INT_CMD_DONE;
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switch (this->cur_cmd) {
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switch (this->cur_cmd & 0xF) {
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case SeqCmd::Arbitrate:
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this->cur_state = SeqState::BUS_FREE;
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this->sequencer();
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break;
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case SeqCmd::Select:
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this->cur_state = SeqState::SEL_BEGIN;
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this->sequencer();
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break;
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case SeqCmd::DisReselect:
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LOG_F(INFO, "MESH: DisReselect command requested");
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break;
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case SeqCmd::ResetMesh:
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case SeqCmd::ResetMesh:
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this->reset(false);
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this->reset(false);
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this->int_stat |= INT_CMD_DONE;
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this->int_stat |= INT_CMD_DONE;
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break;
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break;
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case SeqCmd::FlushFIFO:
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LOG_F(INFO, "MESH: FlushFIFO command requested");
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break;
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default:
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default:
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LOG_F(ERROR, "MESH: unsupported sequencer command 0x%X", this->cur_cmd);
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LOG_F(ERROR, "MESH: unsupported sequencer command 0x%X", this->cur_cmd);
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}
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}
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}
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}
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void MeshController::seq_defer_state(uint64_t delay_ns)
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{
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seq_timer_id = TimerManager::get_instance()->add_oneshot_timer(
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delay_ns,
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[this]() {
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// re-enter the sequencer with the state specified in next_state
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this->cur_state = this->next_state;
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this->sequencer();
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});
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}
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void MeshController::sequencer()
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{
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switch (this->cur_state) {
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case SeqState::IDLE:
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break;
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case SeqState::BUS_FREE:
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if (this->bus_obj->current_phase() == ScsiPhase::BUS_FREE) {
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this->next_state = SeqState::ARB_BEGIN;
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this->seq_defer_state(BUS_FREE_DELAY + BUS_SETTLE_DELAY);
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} else { // continue waiting
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_FREE_DELAY);
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}
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break;
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case SeqState::ARB_BEGIN:
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if (!this->bus_obj->begin_arbitration(this->src_id)) {
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LOG_F(ERROR, "MESH: arbitration error, bus not free!");
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this->bus_obj->release_ctrl_lines(this->src_id);
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this->next_state = SeqState::BUS_FREE;
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this->seq_defer_state(BUS_CLEAR_DELAY);
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break;
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}
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this->next_state = SeqState::ARB_END;
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this->seq_defer_state(ARB_DELAY);
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break;
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case SeqState::ARB_END:
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if (this->bus_obj->end_arbitration(this->src_id) &&
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!this->bus_obj->test_ctrl_lines(SCSI_CTRL_SEL)) { // arbitration won
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this->bus_obj->assert_ctrl_line(this->src_id, SCSI_CTRL_SEL);
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} else { // arbitration lost
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LOG_F(INFO, "MESH: arbitration lost!");
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this->bus_obj->release_ctrl_lines(this->src_id);
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this->exception |= EXC_ARB_LOST;
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this->int_stat |= INT_EXCEPTION;
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}
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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break;
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case SeqState::SEL_BEGIN:
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this->bus_obj->begin_selection(this->src_id, this->dst_id, this->cur_cmd & 0x20);
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this->next_state = SeqState::SEL_END;
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this->seq_defer_state(SEL_TIME_OUT);
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break;
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case SeqState::SEL_END:
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if (this->bus_obj->end_selection(this->src_id, this->dst_id)) {
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this->bus_obj->release_ctrl_line(this->src_id, SCSI_CTRL_SEL);
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LOG_F(9, "MESH: selection completed");
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} else { // selection timeout
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this->bus_obj->disconnect(this->src_id);
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this->cur_state = SeqState::IDLE;
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this->exception |= EXC_SEL_TIMEOUT;
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this->int_stat |= INT_EXCEPTION;
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}
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this->int_stat |= INT_CMD_DONE;
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update_irq();
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break;
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default:
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ABORT_F("MESH: unimplemented sequencer state %d", this->cur_state);
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}
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}
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void MeshController::update_irq()
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{
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uint8_t new_irq = !!(this->int_stat & this->int_mask);
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if (new_irq != this->irq) {
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this->irq = new_irq;
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this->int_ctrl->ack_int(this->irq_id, new_irq);
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}
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}
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static const DeviceDescription Mesh_Descriptor = {
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static const DeviceDescription Mesh_Descriptor = {
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MeshController::create, {}, {}
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MeshController::create, {}, {}
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};
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};
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@ -25,6 +25,7 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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#define MESH_H
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#define MESH_H
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#include <devices/common/hwcomponent.h>
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#include <devices/common/hwcomponent.h>
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#include <devices/common/hwinterrupt.h>
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#include <devices/common/scsi/scsi.h>
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#include <devices/common/scsi/scsi.h>
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#include <cinttypes>
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#include <cinttypes>
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@ -59,7 +60,17 @@ enum MeshReg : uint8_t {
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enum SeqCmd : uint8_t {
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enum SeqCmd : uint8_t {
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NoOperation = 0,
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NoOperation = 0,
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Arbitrate = 1,
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Arbitrate = 1,
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Select = 2,
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DisReselect = 0xD,
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ResetMesh = 0xE,
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ResetMesh = 0xE,
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FlushFIFO = 0xF,
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};
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// Exception register bits.
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enum {
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EXC_SEL_TIMEOUT = 1 << 0,
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EXC_PHASE_MM = 1 << 1,
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EXC_ARB_LOST = 1 << 2,
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};
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};
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// Interrupt register bits.
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// Interrupt register bits.
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@ -70,6 +81,25 @@ enum {
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INT_MASK = INT_CMD_DONE | INT_EXCEPTION | INT_ERROR
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INT_MASK = INT_CMD_DONE | INT_EXCEPTION | INT_ERROR
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};
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};
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enum SeqState : uint32_t {
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IDLE = 0,
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BUS_FREE,
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ARB_BEGIN,
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ARB_END,
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SEL_BEGIN,
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SEL_END,
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SEND_MSG,
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SEND_CMD,
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CMD_COMPLETE,
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XFER_BEGIN,
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XFER_END,
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SEND_DATA,
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RCV_DATA,
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RCV_STATUS,
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RCV_MESSAGE,
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};
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}; // namespace MeshScsi
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}; // namespace MeshScsi
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class MeshController : public HWComponent {
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class MeshController : public HWComponent {
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@ -95,6 +125,9 @@ public:
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protected:
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protected:
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void reset(bool is_hard_reset);
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void reset(bool is_hard_reset);
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void perform_command(const uint8_t cmd);
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void perform_command(const uint8_t cmd);
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void seq_defer_state(uint64_t delay_ns);
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void sequencer();
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void update_irq();
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private:
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private:
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uint8_t chip_id;
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uint8_t chip_id;
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@ -104,9 +137,21 @@ private:
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uint8_t src_id;
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uint8_t src_id;
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uint8_t dst_id;
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uint8_t dst_id;
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uint8_t cur_cmd;
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uint8_t cur_cmd;
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uint8_t error;
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uint8_t exception;
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ScsiBus* bus_obj;
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ScsiBus* bus_obj;
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uint16_t bus_stat;
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uint16_t bus_stat;
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// Sequencer state
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uint32_t seq_timer_id;
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uint32_t cur_state;
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uint32_t next_state;
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// interrupt related stuff
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InterruptCtrl* int_ctrl = nullptr;
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uint32_t irq_id = 0;
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uint8_t irq = 0;
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};
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};
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#endif // MESH_H
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#endif // MESH_H
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