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Further work on fleshing out documentation
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@ -22,6 +22,7 @@ Code
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> one_hundred = 100;
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> one_hundred = 100;
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> one_thousand = 1000;
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> one_thousand = 1000;
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* CamelCase for class names, lowercase for variables, UPPERCASE for enumerations
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* CamelCase for class names, lowercase for variables, UPPERCASE for enumerations
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* Avoid redundancy in namespaces (i.e. use ViaCuda::read() instead of ViaCuda::cuda_read())
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Issues
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Issues
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=======
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=======
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20
zdocs/adb.md
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20
zdocs/adb.md
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@ -0,0 +1,20 @@
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# Commands
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| Command Name | Number |
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|:---------------------------:|:-------:|
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| DEVCMD_CHANGE_ID_AND_ENABLE | 0x00 |
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| DEVCMD_CHANGE_ID | 0xFD |
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| DEVCMD_CHANGE_ID_AND_ACT | 0xFE |
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| DEVCMD_SELF_TEST | 0xFF |
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# Devices
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| Device Type | Example | Default Address |
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|:-----------------:|:-------------:|:---------------:|
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| Protection | | 0x1 |
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| Encoded | Keyboard | 0x2 |
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| Relative-position | Mouse | 0x3 |
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| Absolute-position | Tablet | 0x4 |
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| Data transfer | Modem | 0x5 |
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| Other | | 0x6 |
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| Other | | 0x7 |
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@ -1,11 +1,31 @@
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# Memory Map
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AWACS can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x14000.
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AWACS can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x14000.
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# Registers
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# Register Maps
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Sound Control Register
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## NuBus Macs
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Codec Control Register
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| Register | Offset | Length
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Codec Status Register
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|:-----------------:|:------:|:------:|
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Clipping Count Register
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| Codec Control | 0x0 | 3 |
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Byte Swapping Register
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| Codec Status | 0x4 | 3 |
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| Buffer Size | 0x8 | 2 |
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| Phaser | 0xA | 4 |
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| Sound Control | 0xE | 2 |
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| DMA In | 0x12 | 1 |
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| DMA Out | 0x16 | 1 |
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## PCI Macs
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All registers are 32-bit here.
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| Register | Offset |
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|:-----------------:|:------:|
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| Sound Control | 0x0 |
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| Codec Control | 0x10 |
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| Codec Status | 0x20 |
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| Clipping Count | 0x30 |
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| Byte Swapping | 0x40 |
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Separate volume controls exist for the CD drive and the microphone.
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The DMA buffer size is set to be 0x40000 bytes, while the DMA hardware buffer size is set to be 0x2000 bytes.
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| 0xF1000000 | 0xFFBFFFFF | NuBus "standard slot" space |
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| 0xF1000000 | 0xFFBFFFFF | NuBus "standard slot" space |
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| 0xFFC00000 | 0xFFFFFFFF | ROM |
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| 0xFFC00000 | 0xFFFFFFFF | ROM |
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### IO Bus
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| Address | Area |
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|:-------------:|:------------------:|
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| 0x50F00000 | IO Base Address |
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| 0x50F04000 | SCC |
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| 0x50F14000 | Sound Chip (AWACS) |
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| 0x50F24000 | CLUT Control |
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| 0x50F28000 | Video Control |
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| 0x50F2A000 | Interrupt Control |
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## PCI Power Macs
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## PCI Power Macs
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### Main Memory
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### Main Memory
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44
zdocs/mesh.md
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44
zdocs/mesh.md
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# Registers
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| Register Name | Number |
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|:----------------:|:------:|
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| R_COUNT0 | 0x0 |
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| R_COUNT1 | 0x1 |
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| R_FIFO | 0x2 |
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| R_CMD | 0x3 |
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| R_BUS0STATUS | 0x4 |
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| R_BUS1STATUS | 0x5 |
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| FIFO_CNT | 0x6 |
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| EXCPT | 0x7 |
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| ERROR | 0x8 |
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| INTMASK | 0x9 |
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| INTERRUPT | 0xA |
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| SOURCEID | 0xB |
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| DESTID | 0xC |
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| SYNC | 0xD |
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| MESHID | 0xE |
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| SEL_TIMEOUT | 0xF |
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# Commands
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| Command Name | Number |
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|:----------------:|:------:|
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| NOP | 0x0 |
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| ARBITRATE | 0x1 |
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| SELECT | 0x2 |
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| COMMAND | 0x3 |
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| STATUS | 0x4 |
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| DATAOUT | 0x5 |
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| DATAIN | 0x6 |
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| MSGOUT | 0x7 |
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| MSGIN | 0x8 |
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| BUSFREE | 0x9 |
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| ENABLE_PARITY | 0xA |
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| DISABLE_PARITY | 0xB |
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| ENABLE_RESELECT | 0xC |
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| DISABLE_RESELECT | 0xD |
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| RESET_MESH | 0xE |
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| FLUSH_FIFO | 0xF |
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| SEQ_DMA | 0x20 |
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| SEQ_TARGET | 0x40 |
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| SEQ_ATN | 0x80 |
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@ -14,12 +14,26 @@ Swim3 is located at 0xF3015000.
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# Serial
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# Serial
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For serial, it replicates the functionality of a Zilog ESCC. There are two different ports - one located at 0xF3013000 for the printer, and the other at 0xF3013020 for the modem.
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For serial, it replicates the functionality of a Zilog ESCC. There are two different ports - one located at (MacIOBase) + 0x13000 for the printer, and the other at (MacIOBase) + 0x13020 for the modem.
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# DBDMA
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# DBDMA
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The Description-Based Direct Memory Access relies on memory-based descriptions, minimizing CPU interrupts.
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The Description-Based Direct Memory Access relies on memory-based descriptions, minimizing CPU interrupts.
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| Channel | Number |
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|:-----------------:|:------:|
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| SCSI0 | 0x0 |
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| FLOPPY | 0x1 |
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| ETHERNET TRANSMIT | 0x2 |
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| ETHERNET RECIEVE | 0x3 |
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| SCC TRANSMIT A | 0x4 |
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| SCC RECIEVE A | 0x5 |
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| SCC TRANSMIT B | 0x6 |
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| SCC RECIEVE B | 0x7 |
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| AUDIO OUT | 0x8 |
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| AUDIO IN | 0x9 |
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| SCSI1 | 0xA |
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# SWIM 3
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# SWIM 3
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The SWIM 3 (Sanders-Wozniak integrated machine 3) is the floppy drive disk controller. As can be inferred by the name, the SWIM III chip is the improvement of a combination of floppy disk driver designs by Steve Wozniak (who worked on his own floppy drive controller for early Apple computers) and Wendell B. Sander (who worked on an MFM-compatible IBM floppy drive controller).
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The SWIM 3 (Sanders-Wozniak integrated machine 3) is the floppy drive disk controller. As can be inferred by the name, the SWIM III chip is the improvement of a combination of floppy disk driver designs by Steve Wozniak (who worked on his own floppy drive controller for early Apple computers) and Wendell B. Sander (who worked on an MFM-compatible IBM floppy drive controller).
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@ -32,6 +46,20 @@ The floppy drives themselves were provided by Sony.
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Mac OS relies on 8 KB of NVRAM at minimum to run properly. It's usually found at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x60000.
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Mac OS relies on 8 KB of NVRAM at minimum to run properly. It's usually found at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x60000.
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# PMU
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| Command Name | Number | Functionality |
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|:----------------:|:------:|:----------------------------:|
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| PMUpMgrADB | 0x20 | Send ADB command |
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| PMUpMgrADBoff | 0x21 |
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| PMUxPramWrite | 0x32 |
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| PMUtimeRead | 0x38 |
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| PMUxPramRead | 0x3A |
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| PMUmaskInts | 0x70 |
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| PMUreadINT | 0x78 |
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| PMUPmgrPWRoff | 0x7E |
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| PMUResetCPU | 0xD0 |
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# Miscellaneous
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# Miscellaneous
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The Power Mac G3 Beige has an additional register at 0xFF000004, which is dubbed varyingly as the "cpu-id" (by OpenFirmware), the ""systemReg" (display driver) or "MachineID" (platform driver).
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The Power Mac G3 Beige has an additional register at 0xFF000004, which is dubbed varyingly as the "cpu-id" (by OpenFirmware), the ""systemReg" (display driver) or "MachineID" (platform driver).
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@ -2,6 +2,16 @@ Using a combination of a 6522 along with some integrated circuits, the VIA Cuda
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The usual offset for a VIA Cuda is IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x16000. The registers are spaced out by 0x200 bytes on the Heathrow.
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The usual offset for a VIA Cuda is IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x16000. The registers are spaced out by 0x200 bytes on the Heathrow.
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# Usage
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The VIA Cuda is emulated in all Power Macs through an interrupt controller. Early Power Macs also used the Parameter RAM.
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Additionally, nodes are included for ADB peripherals, Parameter RAM, Real-Time Clocks, and Power Management.
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It can be run either synchronously or asynchronously.
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However, the CUDA is also slower than the CPU, thus causing a delay that the OS expects.
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# Registers
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# Registers
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Within the emulated CUDA, these registers are spaced apart by 0x200 bytes. Apple themselves recommended avoiding the usage of Handshake Data A.
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Within the emulated CUDA, these registers are spaced apart by 0x200 bytes. Apple themselves recommended avoiding the usage of Handshake Data A.
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@ -25,15 +35,35 @@ Within the emulated CUDA, these registers are spaced apart by 0x200 bytes. Apple
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| Interrupt Enable | IER | 0xE |
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| Interrupt Enable | IER | 0xE |
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| Data A | ORA | 0xF |
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| Data A | ORA | 0xF |
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# Usage
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## Data A
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The VIA Cuda is emulated in all Power Macs through an interrupt controller. Early Power Macs also used the Parameter RAM.
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| Register Bit | Bit Mask |
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|:----------------:|:--------:|
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| Drive Select | 0x10 |
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| Disk Head Select | 0x20 |
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Additionally, nodes are included for ADB peripherals, Parameter RAM, Real-Time Clocks, and Power Management.
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## Auxiliary Contral
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It can be run either synchronously or asynchronously.
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| Register Bit | Bit Mask |
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|:---------------------------------:|:--------:|
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| Port A Latch | 0x1 |
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| Port B Latch | 0x2 |
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| Timer 2, control | 0x20 |
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| Timer 1, continuous counting | 0x40 |
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| Timer 1, drives PB7 | 0x80 |
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However, the CUDA is also slower than the CPU, thus causing a delay that the OS expects.
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## Interrupt Enable
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| Register Bit | Bit Mask |
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|:--------------:|:--------:|
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| CA2 | 0x1 |
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| CA1 | 0x2 |
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| Shift Register | 0x2 |
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| CB2 | 0x8 |
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| CB1 | 0x10 |
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| Timer 2 | 0x20 |
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| Timer 1 | 0x40 |
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| Set interrupt | 0x80 |
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# Packet Types
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# Packet Types
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