Commit Graph

64 Commits

Author SHA1 Message Date
dingusdev a95b06f703 Minor code clean-up 2024-05-08 07:07:32 -07:00
joevt e8ce805f2a poweropcodes: Remove power_setsoov.
None of the POWER opcodes uses it now, plus it is a duplicate of ppc_setsoov (though ppc_setsoov is inline so it would have to be moved to be able to use it in poweropcodes.cpp?
2024-04-10 07:30:06 -07:00
joevt 3d898ebdf3 poweropcodes: Cleanup power_rot_mask.
Use U instead of UL. U will use the smallest size that can fit all the unsigned bytes. Since 0xFFFFFFFF fits in 32 bits, the 0xFFFFFFFFU is a uint32_t.
2024-04-10 07:29:56 -07:00
joevt f45b7c47c8 poweropcodes: Fix srq.
Test bit 26 of rB instead of testing for >= 0x20 to determine which operation to perform.
2024-04-10 07:29:46 -07:00
joevt 916cb47b9d poweropcodes: Fix srlq.
Test bit 26 of rB instead of testing for >= 0x20 to determine which operation to perform.
2024-04-10 07:29:37 -07:00
joevt bce816139b poweropcodes: Fix sreq.
Including bits of rot_sh in the rA and MQ calculations is nonsensical since it is a rotation count and not a source of bits to be extracted or rotated.
The mask is not complicated, so we don't need to use power_rot_mask.
2024-04-10 07:29:28 -07:00
joevt 24bce16c4d poweropcodes: Fix srea.
Fix carry flag calculation. Anding with the rotation count (n = rB) is nonsensical.
(r & ~mask) is the rotated word ANDed with the complement of the generated mask of n zeros followed by 32 - n ones.
The manual says this 32-bit result is ORed together. This means all the bits are ORed together which is equivalent to saying 0 if all zeros and 1 if any ones. In other words: (r & ~mask) != 0.
This boolean is ANDed with bit 0 of rS to produce the carry. int32_t(rS) < 0 will test bit 0. The && operator will treat each side as a boolean so you can exclude "!= 0" tests.
2024-04-10 07:29:20 -07:00
joevt a928c67913 poweropcodes: Fix sraq.
If bit 26 of rB is set then the mask should be all ones.
If bit 26 of rB is set then rA should be all ones or all zeros (depending on the sign bit of rA).
2024-04-10 07:29:11 -07:00
joevt 2b8f510603 poweropcodes: Fix slq.
Test bit 26 of rB instead of using >= 0x20 to determine which operation to perform.
The two operations need to be switched such that rA is cleared when bit 26 is set.
Don't forget to store the result in rA.
2024-04-10 07:28:58 -07:00
joevt e8273ecc61 poweropcodes: Fix sllq.
Test bit 26 of rB instead of using >= 0x20 to determine which operation to perform.
Since the mask is not complicated, we don't need to use power_rot_mask.
2024-04-10 07:28:46 -07:00
joevt e1f31a2da3 poweropcodes: Fix rrib.
It is redundant to test bit 0 of rS and then use bit 0 of rS in the case when bit 0 of rS is set.
In the case when bit 0 of rS is not set, using bit 0 or rS is incorrect since it results in no change of rA.
2024-04-10 07:26:52 -07:00
joevt d897acfd3c poweropcodes: Fix nabs.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
2024-04-10 07:26:32 -07:00
joevt 1e57ac408a poweropcodes: Fix mul.
Operands are supposed to be twos complement numbers.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calcalation. It's supposed to depend on the low order 32 bits that are placed into MQ.
2024-04-10 07:26:24 -07:00
joevt ef8522e101 poweropcodes: Fix maskg.
The condition code register depends on rA, not rD since rA contains the result.
2024-04-10 07:26:16 -07:00
joevt c71d856a08 poweropcodes: Fix lscbx.
- Fix CR calculation. It depends on whether a match occurred and only the EQ flag is affected.
- Remove bytes_copied. We can subtract bytes_remaining from bytes_to_load to calculate that.
- Initialize ppc_result_d to zero so that bitmask is not needed to add new bytes to it. This is ok since the manual says that bytes that are not loaded are undefined.
2024-04-10 07:26:07 -07:00
joevt df7ff76404 poweropcodes: Fix doz.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations. doz does a subtract but only if the result is supposed to be positive, therefore a negative result indicates an overflow.
2024-04-10 07:22:50 -07:00
joevt 0d1ce68d19 poweropcodes: Fix divs.
dividend and divisor are supposed to be a twos compliment numbers.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:41 -07:00
joevt 88aa249ce1 poweropcodes: Fix div.
dividend is supposed to be a twos compliment number.
Fix test for dividend = -0x80000000 and divisor = -1. Previously, the test was assuming dividend was a 32-bit value from rA.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:34 -07:00
joevt ff626ae0b5 poweropcodes: Fix clcs.
For MPC601 CPUs, all values of rA return 64 though the manual says undefined values of rA produce undefined results.
For non-MPC601 CPUs, if this instruction is included (such as for risu DPPC) then return results that are obtained from a G4 running Mac OS 9.2.2.
2024-04-10 07:22:26 -07:00
joevt 529f23d836 poweropcodes: Fix abs.
Making a negative value positive requires unary negate operator rather than binary and operator since negative numbers are stored using twos compliment.
If ov is set then clear overflow when overflow doesn't happen.
2024-04-10 07:22:18 -07:00
joevt 29a832c68d ppcopcodes: Use < 0 instead of & 0x8000000. 2024-04-10 06:45:31 -07:00
joevt cb05bd05eb cpu: Add ppc_grab_regssash macro.
This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
2024-04-10 06:43:34 -07:00
Maxim Poliakovski 0ff911cc26 poweropcodes: cosmetic improvements. 2024-03-27 03:45:22 +01:00
Maxim Poliakovski 2b6f41e0d0 poweropcodes: use XER constants instead of magic numbers. 2024-03-27 03:36:17 +01:00
joevt 19ba15f2f1 ppc: Separate enums for separate fields. 2024-03-26 06:44:26 -07:00
dingusdev c281b27220 Attempted templating for interpreter 2024-03-24 12:21:19 -07:00
dingusdev 4ef3c792de Refactoring interpreter, pt. 1
Reduce the number of global variables used by interpreter
2024-03-22 08:01:29 -07:00
joevt 6a4326af39 poweropcodes: lscbx cleanup. 2024-03-01 07:46:04 -07:00
Maxim Poliakovski 0c3f399de3 poweropcodes: fix compiler warning. 2024-02-24 22:51:05 +01:00
Maxim Poliakovski 45ccabb11d poweropcodes: improve lscbx emulation. 2024-02-24 22:46:54 +01:00
dingusdev d71a213c4b Continued clean-up, part 3 2024-02-22 19:46:34 -07:00
dingusdev 1d938c93b6 Mask fixes for sr(*) 2024-02-20 18:15:08 -07:00
joevt 35bc1bcb44 poweropcodes: Fix sriq. 2024-02-20 18:07:38 -07:00
joevt 1438ebc12a poweropcodes: Fix compiler warnings. 2024-02-20 18:07:26 -07:00
dingusdev b160e38f8f Continued code clean-up 2024-02-16 06:55:13 -07:00
Maxim Poliakovski 819d475181 poweropcodes: fix div emulation.
Clean up power_doz and power_maskir as well.
2023-12-01 20:41:22 +01:00
Mihai Parparita 1b4de3b64e Fix emulation of doz, dozi, and nabs POWER instructions
doz and dozi were storing the result into the wrong register.

nabs was not taking into account two's complement storage of numbers
and was just setting the signed bit.

These two instructions are used in the implementation of text
measurement in native QuickDraw on 7.1.2/the PDM ROM, and the incorrect
values were resulting in nothing being rendered. With the fix text
appears when booting from the 7.1.2 CD.
2023-12-01 01:34:12 -08:00
Mihai Parparita 35c86ad6bf Clean up #includes
Result of running IWYU (https://include-what-you-use.org/) and
applying most of the suggestions about unncessary includes and
forward declarations.

Was motivated by observing that <thread> was being included in
ppcopcodes.cpp even though it was unused (found while researching
the use of threads), but seems generally good to help with build
times and correctness.
2023-11-03 00:33:47 -07:00
Maxim Poliakovski cf0d361918 Merge 'hard-disks' branch. 2023-04-17 01:20:38 +02:00
joevt 64fec88436 Fix compiler warnings: cast loses precision.
Use explicit cast when converting large integer types to smaller integer types when it is known that the most significant bytes are not required.
For pcidevice, check the ROM file size before casting to int. We'll allow expansion ROM sizes up to 4MB but usually they are 64K, sometimes 128K, rarely 256K.
for machinefactory, change the type to size_t so that it can correctly get the size of files that are larger than 4GB; it already checks the file size is 4MB before we need to cast to uint32_t.
For floppyimg, check the image size before casting to int. For raw images, only allow files up to 2MB. For DiskCopy42 images, it already checks the file size, so do the cast after that.
2023-01-11 01:17:12 -08:00
dingusdev a58ce8aeb3 Slight tweak to lscbx 2022-11-15 08:01:57 -07:00
dingusdev 8f99510af0 Fixed lscbx 2022-11-15 07:40:37 -07:00
dingusdev 647ae456e5 Slight typo squash for lscbx 2022-11-12 20:18:33 -07:00
dingusdev 1b7ff084ab Cleaned lscbx 2022-11-12 20:17:04 -07:00
Maxim Poliakovski c0cd6eb38f Add missing licence headers, update license date. 2021-10-23 21:00:31 +02:00
dingusdev 983e278498 Refactoring 601 opcode emulation - part 1
All opcodes should be emulated now. There was also a significant amount of clean-up, particularly with lscbx and the bit rotation/shifting instructions.
2021-10-01 22:37:28 -07:00
Maxim Poliakovski 84e111290f Fix includes for loguru and SDL. 2021-09-16 00:46:38 +02:00
Maxim Poliakovski 089645e830 Implement SoftTLB for writes. 2021-08-22 17:34:23 +02:00
dingusdev 1fe9ffe3e5 Further refactoring to clean up the interpreter 2020-10-17 21:46:38 -07:00
dingusdev dc58386237 Started re-refactoring opcode retrieval 2020-10-17 14:30:37 -07:00