Commit Graph

555 Commits

Author SHA1 Message Date
joevt
a8023bb41b ppcmmu: Remove last_dma_area.
DMA may happen on CPU and audio threads but update of last_dma_area is not thread safe.
2024-04-21 09:13:42 -07:00
joevt
5022ac89b4 ppcexec: Improve realtime. 2024-04-21 07:16:47 -07:00
joevt
e8ce805f2a poweropcodes: Remove power_setsoov.
None of the POWER opcodes uses it now, plus it is a duplicate of ppc_setsoov (though ppc_setsoov is inline so it would have to be moved to be able to use it in poweropcodes.cpp?
2024-04-10 07:30:06 -07:00
joevt
3d898ebdf3 poweropcodes: Cleanup power_rot_mask.
Use U instead of UL. U will use the smallest size that can fit all the unsigned bytes. Since 0xFFFFFFFF fits in 32 bits, the 0xFFFFFFFFU is a uint32_t.
2024-04-10 07:29:56 -07:00
joevt
f45b7c47c8 poweropcodes: Fix srq.
Test bit 26 of rB instead of testing for >= 0x20 to determine which operation to perform.
2024-04-10 07:29:46 -07:00
joevt
916cb47b9d poweropcodes: Fix srlq.
Test bit 26 of rB instead of testing for >= 0x20 to determine which operation to perform.
2024-04-10 07:29:37 -07:00
joevt
bce816139b poweropcodes: Fix sreq.
Including bits of rot_sh in the rA and MQ calculations is nonsensical since it is a rotation count and not a source of bits to be extracted or rotated.
The mask is not complicated, so we don't need to use power_rot_mask.
2024-04-10 07:29:28 -07:00
joevt
24bce16c4d poweropcodes: Fix srea.
Fix carry flag calculation. Anding with the rotation count (n = rB) is nonsensical.
(r & ~mask) is the rotated word ANDed with the complement of the generated mask of n zeros followed by 32 - n ones.
The manual says this 32-bit result is ORed together. This means all the bits are ORed together which is equivalent to saying 0 if all zeros and 1 if any ones. In other words: (r & ~mask) != 0.
This boolean is ANDed with bit 0 of rS to produce the carry. int32_t(rS) < 0 will test bit 0. The && operator will treat each side as a boolean so you can exclude "!= 0" tests.
2024-04-10 07:29:20 -07:00
joevt
a928c67913 poweropcodes: Fix sraq.
If bit 26 of rB is set then the mask should be all ones.
If bit 26 of rB is set then rA should be all ones or all zeros (depending on the sign bit of rA).
2024-04-10 07:29:11 -07:00
joevt
2b8f510603 poweropcodes: Fix slq.
Test bit 26 of rB instead of using >= 0x20 to determine which operation to perform.
The two operations need to be switched such that rA is cleared when bit 26 is set.
Don't forget to store the result in rA.
2024-04-10 07:28:58 -07:00
joevt
e8273ecc61 poweropcodes: Fix sllq.
Test bit 26 of rB instead of using >= 0x20 to determine which operation to perform.
Since the mask is not complicated, we don't need to use power_rot_mask.
2024-04-10 07:28:46 -07:00
joevt
e1f31a2da3 poweropcodes: Fix rrib.
It is redundant to test bit 0 of rS and then use bit 0 of rS in the case when bit 0 of rS is set.
In the case when bit 0 of rS is not set, using bit 0 or rS is incorrect since it results in no change of rA.
2024-04-10 07:26:52 -07:00
joevt
d897acfd3c poweropcodes: Fix nabs.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
2024-04-10 07:26:32 -07:00
joevt
1e57ac408a poweropcodes: Fix mul.
Operands are supposed to be twos complement numbers.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calcalation. It's supposed to depend on the low order 32 bits that are placed into MQ.
2024-04-10 07:26:24 -07:00
joevt
ef8522e101 poweropcodes: Fix maskg.
The condition code register depends on rA, not rD since rA contains the result.
2024-04-10 07:26:16 -07:00
joevt
c71d856a08 poweropcodes: Fix lscbx.
- Fix CR calculation. It depends on whether a match occurred and only the EQ flag is affected.
- Remove bytes_copied. We can subtract bytes_remaining from bytes_to_load to calculate that.
- Initialize ppc_result_d to zero so that bitmask is not needed to add new bytes to it. This is ok since the manual says that bytes that are not loaded are undefined.
2024-04-10 07:26:07 -07:00
joevt
df7ff76404 poweropcodes: Fix doz.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations. doz does a subtract but only if the result is supposed to be positive, therefore a negative result indicates an overflow.
2024-04-10 07:22:50 -07:00
joevt
0d1ce68d19 poweropcodes: Fix divs.
dividend and divisor are supposed to be a twos compliment numbers.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:41 -07:00
joevt
88aa249ce1 poweropcodes: Fix div.
dividend is supposed to be a twos compliment number.
Fix test for dividend = -0x80000000 and divisor = -1. Previously, the test was assuming dividend was a 32-bit value from rA.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:34 -07:00
joevt
ff626ae0b5 poweropcodes: Fix clcs.
For MPC601 CPUs, all values of rA return 64 though the manual says undefined values of rA produce undefined results.
For non-MPC601 CPUs, if this instruction is included (such as for risu DPPC) then return results that are obtained from a G4 running Mac OS 9.2.2.
2024-04-10 07:22:26 -07:00
joevt
529f23d836 poweropcodes: Fix abs.
Making a negative value positive requires unary negate operator rather than binary and operator since negative numbers are stored using twos compliment.
If ov is set then clear overflow when overflow doesn't happen.
2024-04-10 07:22:18 -07:00
joevt
cb88bab67d ppcopcodes: Fixes for SPRs.
- Rename DEC to DEC_S and add DEC_U.
- MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction.
- For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601.
- For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC.
- For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
2024-04-10 07:21:54 -07:00
joevt
67a5c39b1c ppcopcodes: Add Privileged exception for SPRs.
Accessing an SPR with bit 4 set (> 15) requires supervisor privilege and should cause a supervisor-level instruction exception (privileged instruction type program exception).
2024-04-10 07:21:23 -07:00
joevt
0273867c49 ppcopcodes: Cleanup ppc_changecrf0.
- Use one assignment to set ppc_state.cr.
- Use enums for CR and XER bits.
- Use < to check sign bit.
2024-04-10 06:47:10 -07:00
joevt
1e50d88183 ppcopcodes: Use macro to grab instruction fields. 2024-04-10 06:46:46 -07:00
joevt
29a832c68d ppcopcodes: Use < 0 instead of & 0x8000000. 2024-04-10 06:45:31 -07:00
joevt
cb05bd05eb cpu: Add ppc_grab_regssash macro.
This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
2024-04-10 06:43:34 -07:00
joevt
4f45d7de35 cpu: Add cpu options to ppc_cpu_init.
The first option is a flag that enables MPC601 (POWER) instructions for CPUs that are not MPC601.
This can be useful for the following reasons:
1) To produce results similar to classic Mac OS which emulates MPC601 instructions on CPUs that don't implement MPC601 instructions. This option is used to compare the risu traces produced in Mac OS 9 on a G3 or G4 with DPPC.
2) May increase performance in apps that use POWER instructions on emulated machines with CPUs that are not MPC601. It is not known if any such apps exist but there could be since Apple included MPC601 emulation in classic Mac OS.
2024-04-10 06:43:18 -07:00
dingusdev
9c95bc17fe Implement VX and FEX updates for mtfsfi 2024-04-09 21:11:09 -07:00
dingusdev
2c94cfee03 Removing currently unneeded functions 2024-04-09 18:34:36 -07:00
joevt
3c16870f86 ppcmmu: Replace defines.
They may interfere with system headers.
2024-04-09 07:57:48 -07:00
Maxim Poliakovski
524daa45a5 ppcexec.cpp: fix compilation with Apple Clang 10. 2024-04-07 20:39:24 +02:00
joevt
9ed1a118e6 ppcmmu: Check sizeof(T) explicitly.
I don't know if the compiler is smart enough to figure out that ((guest_va & 0xFFF) + sizeof(T)) > 0x1000) is always false when sizeof(T) == 1 so we'll add a check for sizeof(T) > 1.
2024-04-07 08:59:05 -07:00
dingusdev
a5a5410515 Continued fixing floating-point ops 2024-04-07 08:58:38 -07:00
dingusdev
40a4ca31b9 More minor floating-point clean-up 2024-04-07 07:23:30 -07:00
dingusdev
7f44ab2262 Minor fixes to floating point 2024-04-06 17:31:03 -07:00
dingusdev
123c927b1a Another refactor for floating points
FCMPO and FCMPU passes the tests now*
2024-04-06 11:02:03 -07:00
dingusdev
43d87b4791 Temp revert for icnt_factor
We should, at minimum, make icnt_factor adjustable. That said, powermax is suggesting we develop a more sophisticated scheduler.
2024-03-31 14:13:45 -07:00
joevt
6267685920 ppcexec: Make EXEF_TIMER separate variable. 2024-03-31 12:15:48 -07:00
joevt
48882f3fec ppcexec: Adjust icnt_factor.
So that 1000 ms takes ≈ 1 second in Open Firmware on 4 GHz Intel CPU.
2024-03-31 11:51:04 -07:00
joevt
0ac54ea1ea ppcexec: Add host time option. 2024-03-31 11:50:55 -07:00
joevt
d9b02ecd8d ppcmmu: Check 8 byte alignment spanning pages. 2024-03-28 07:53:03 -07:00
joevt
b9c12e44a4 ppcopcodes: Cleanup 3. 2024-03-28 07:36:40 -07:00
joevt
58ed5bb56e ppcexec: Opcode initialization to one function.
Move all opcode initialization to initialize_ppc_opcode_tables.
Some opcodes are illegal for some processors.
2024-03-28 07:35:57 -07:00
joevt
094f44e92c ppcopcodes: Make MQ read only on non-601 CPUs. 2024-03-28 07:29:50 -07:00
joevt
566706dd62 ppctests: Fix compiler warnings. 2024-03-28 07:17:38 -07:00
joevt
60a76e9348 ppcexec: Fix branch check in ppc_exec_single. 2024-03-28 07:17:13 -07:00
joevt
f55ad323b4 ppcdisasm: Fix order of operands.
For cntlzw, extsh, extsb.
2024-03-28 07:09:50 -07:00
joevt
78558e4c52 debugger: Ensure space between opcode and operand.
Instructions that are 8 characters or longer (such as mtdbat3l) did not have a space between opcode and operand. Now there is always a space. The width of the opcode column is unchanged except for those opcodes that have 8 or more characters.
2024-03-28 06:54:23 -07:00
joevt
c9d4cc3321 ppcmmu: Remove old and slow code. 2024-03-27 20:13:45 -07:00