Macintosh-Tools/dingusppc
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58 Commits

Author SHA1 Message Date
joevt
7007e002e6 macio: Make interrupt flags atomic. 
So they can be modified by other threads.
 2024-04-02 19:05:57 -07:00
joevt
1d9b0f7fa5 macio: Add MIO_AUX_CTRL enum. 2024-03-28 07:10:05 -07:00
joevt
052a47734f macio: Add DMA interrupts. 2024-03-06 21:19:04 -07:00
joevt
54767bf97d More interrupts. 
- Add all the interrupts including DMA.
- Modify the Interrupt to IRQ_ID translation so the interrupts belonging to the first set of 32 interrupts don't need to be shifted.
 2024-03-06 19:17:16 -07:00
joevt
e5bace03f7 Abort if register_dma_int. 
Make register_dma_int cause Abort for heathrow and ohare like it does for amic.
 2024-03-06 19:17:03 -07:00
joevt
c64fab6ecb heathrow: Align read/write messages. 2024-03-03 12:03:06 -07:00
joevt
569893861d heathrow: Don't set lat_timer. 
It will be set by firmware.
 2024-03-02 16:42:49 -07:00
joevt
1e78512c95 Rename Curio and Mesh. 2024-03-02 11:12:45 -07:00
joevt
b0dc893a05 dma: Add name to dma classes. 
For logging purposes, each DMA channel should have a name.
 2024-02-19 15:30:20 +01:00
Maxim Poliakovski
8ddbc9c427 Wire SCSI_MESH interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
fd92d86954 mesh: add MESH TNT variant. 2023-12-11 08:05:39 +01:00
Maxim Poliakovski
6cfde29f00 heathrow: implement native interrupt mode. 2023-09-25 12:22:17 +02:00
Maxim Poliakovski
c115a887d8 heathrow: fix processing of emulated interrupts. 2023-09-25 02:14:29 +02:00
Maxim Poliakovski
f4f7edcc28 heathrow: add Ethernet DBDMA channels. 2023-09-22 00:11:19 +02:00
Maxim Poliakovski
0ebcd15a3d heathrow: connect DMA channel for MESH. 2023-09-19 14:19:15 +02:00
Maxim Poliakovski
7bb7ff9f0f heathrow: human-readable DBDMA channel names. 2023-07-24 15:20:52 +02:00
Maxim Poliakovski
14c7d18bdb Revert "Prevents crashing for Big Mac" 
This reverts commit 5787d49e9b.
 2023-07-23 16:28:31 +02:00
dingusdev
5787d49e9b Prevents crashing for Big Mac 
For some reason, on Windows, whether it be VS2022 or Clang, it will crash when trying to write to a Big Mac register if you don't specify the exact name of the component within Heathrow.

This commit fixes that.
 2023-07-22 15:15:33 -07:00
Maxim Poliakovski
742003b6f3 Basic BigMac Ethernet controller emulation. 
Emulates MII and some PHY configuration registers.
 2023-07-08 01:27:01 +02:00
Maxim Poliakovski
f733859e28 heathrow: support for IDE interrupts. 2023-06-18 23:31:28 +02:00
Maxim Poliakovski
f809124a2e Improve SCSI bus registration. 2023-05-30 19:46:27 +02:00
Maxim Poliakovski
22798fe14e Fix compilation of the audio codec classes. 2023-04-23 21:04:24 +02:00
Maxim Poliakovski
44478b6937 heathrow: implement floppy DMA interrupts. 2023-04-22 22:53:20 +02:00
Maxim Poliakovski
03595c3940 Merge remote-tracking branch 'origin/machine-yosemite' 2023-04-21 12:49:58 +02:00
Maxim Poliakovski
cf0d361918 Merge 'hard-disks' branch. 2023-04-17 01:20:38 +02:00
Maxim Poliakovski
d76433f112 heathrow: properly relocate memory space. 2023-02-25 18:14:42 +01:00
Maxim Poliakovski
5d7450df90 heathrow: locate sound HW by type. 
That allows using sound codecs other than Screamer with Heathrow.
 2023-02-25 18:14:42 +01:00
Maxim Poliakovski
3234f21cab Overhaul audio codec classes. 2023-02-25 18:14:42 +01:00
Maxim Poliakovski
cc17035e67 pcidevice: improve BAR configuration. 2023-02-04 17:57:46 +01:00
joevt
2a64f547cc Add 64-bit BAR support. 
While dingusppc only emulates 32-bit Macs (for now), it is possible for a 32-bit Power Mac to use a PCIe card that has 64-bit BARs.

finish_config_bars is added to scan the cfg values of the BARs and determine their type. The type is stored separately so that it does not need to be determined again.
The type can be I/O (16 or 32 bit) or Mem (20 or 32 or 64 bit). A 64 bit bar is two BARs, the second contains the most significant 32 bits.

set_bar_value uses the stored type instead of trying to determine the type itself. It is always called even when the firmware is doing sizing. For sizing, It does the job of setting the bar value so do_bar_sizing is now just a stub.

Every PCIDevice that has a BAR needs to call finish_config_bars after setting up the cfg values just as they need to setup the cfg values. Since they need to do both, maybe the cfg values should be arguments of finish_config_bars, then finish_config_bars() should be renamed config_bars().
 2023-02-02 02:47:34 -08:00
Maxim Poliakovski
449cc96612 Basic MESH emulation. 2023-01-25 20:58:30 +01:00
Maxim Poliakovski
8002737124 Basic O'Hare I/O controller emulation. 2022-12-23 17:19:46 +01:00
Maxim Poliakovski
a892842b8f Refactor ATA/IDE classes. 2022-12-07 22:36:25 +01:00
dingusdev
58908621e6 IDE refinements 2022-12-05 08:42:51 -07:00
dingusdev
311538b81d Fix IDE functionality 2022-11-26 21:34:54 -07:00
Maxim Poliakovski
a0dd1884b3 macio: properly wire floppy DMA. 2022-11-17 18:03:18 +01:00
dingusdev
b480903c7a Slight code clean-up 
Prevents crashing
 2022-10-30 15:38:09 -07:00
dingusdev
aa1d23e08b Fixed hard disk support 
Compiles, still unfinished
 2022-10-22 11:41:52 -07:00
dingusdev
ee9573327c Reorganized hard disk code 
Not compiling yet.
 2022-10-08 16:51:54 -07:00
Maxim Poliakovski
6c59bf4203 heathrow: fix interrupt processing. 2022-08-24 14:58:07 +02:00
joevt
3ee2ea1871 Fix read/write argument names 
base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.
 2022-08-22 17:16:22 -07:00
joevt
b76bfedf4b Remove unnecessary linefeeds from log 
To remove blank lines in the dingusppc.log file or in the console output when -d is used.
 2022-08-14 05:26:56 -07:00
Maxim Poliakovski
56db0426a4 heathrow: fix EMMO bit. 2022-08-08 21:06:57 +02:00
Maxim Poliakovski
c3939e3b25 Gossamer: factory test control. 2022-07-20 20:08:37 +02:00
Maxim Poliakovski
c0078ce97d Refactor MachineBase and MachineFactory classes. 
Adding new machines is much easier now.
A significant amount of duplicated code has been reduced.
 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
9056d53474 macio: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
5668fc161f macio: fix SWIM3 register space accesses. 2022-06-13 23:15:48 +02:00
Maxim Poliakovski
d4c08bbe31 Fix ESCC register addressing. 2022-05-07 21:47:22 +02:00
Maxim Poliakovski
4d87ed9b38 Make NVRAM a full-fledged HW component. 2022-03-29 01:55:11 +02:00
Maxim Poliakovski
276cd37cfe Heathrow: interrupt registers & mode 1 interrupts. 2022-03-14 18:13:47 +01:00