Commit Graph

35 Commits

Author SHA1 Message Date
joevt
b0dc893a05 dma: Add name to dma classes.
For logging purposes, each DMA channel should have a name.
2024-02-19 15:30:20 +01:00
joevt
8a800062dd grandcentral: Add DMA channel enum. 2024-02-12 14:06:19 +01:00
Maxim Poliakovski
28e7a806b4 grandcentral: use MeshStub on machines without MESH. 2024-02-12 02:38:38 +01:00
Maxim Poliakovski
a0e56aa4cf grandcentral: connect external SCSI HW. 2024-02-12 02:17:09 +01:00
Maxim Poliakovski
b3e3b73159 grandcentral: connect MESH HW. 2024-02-12 02:17:09 +01:00
Maxim Poliakovski
e77b8785ff grandcentral: wire SWIM3 DMA interrupt. 2024-02-12 02:01:01 +01:00
Maxim Poliakovski
cb8c2cb450 Wire CONTROL interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
98d661eda1 Wire PLATINUM interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
5902cd5c28 Wire SCSI_CURIO interrupt. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
ce2f6ddadd grandcentral: cleanup interrupt acknowledgement. 2024-02-12 01:46:21 +01:00
Maxim Poliakovski
705dd390e9 grandcentral: respect size when reading from IOBus devices. 2023-12-10 00:19:44 +01:00
Maxim Poliakovski
078aa79270 grandcentral: remove board register 1 stub. 2023-12-10 00:19:44 +01:00
Maxim Poliakovski
f809124a2e Improve SCSI bus registration. 2023-05-30 19:46:27 +02:00
Maxim Poliakovski
3234f21cab Overhaul audio codec classes. 2023-02-25 18:14:42 +01:00
Maxim Poliakovski
cc17035e67 pcidevice: improve BAR configuration. 2023-02-04 17:57:46 +01:00
joevt
2a64f547cc Add 64-bit BAR support.
While dingusppc only emulates 32-bit Macs (for now), it is possible for a 32-bit Power Mac to use a PCIe card that has 64-bit BARs.

finish_config_bars is added to scan the cfg values of the BARs and determine their type. The type is stored separately so that it does not need to be determined again.
The type can be I/O (16 or 32 bit) or Mem (20 or 32 or 64 bit). A 64 bit bar is two BARs, the second contains the most significant 32 bits.

set_bar_value uses the stored type instead of trying to determine the type itself. It is always called even when the firmware is doing sizing. For sizing, It does the job of setting the bar value so do_bar_sizing is now just a stub.

Every PCIDevice that has a BAR needs to call finish_config_bars after setting up the cfg values just as they need to setup the cfg values. Since they need to do both, maybe the cfg values should be arguments of finish_config_bars, then finish_config_bars() should be renamed config_bars().
2023-02-02 02:47:34 -08:00
Maxim Poliakovski
8002737124 Basic O'Hare I/O controller emulation. 2022-12-23 17:19:46 +01:00
Maxim Poliakovski
a0dd1884b3 macio: properly wire floppy DMA. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
dac50fe0fb GrandCentral: fix DMA dispatching. 2022-11-17 18:03:18 +01:00
Maxim Poliakovski
bb77b2d525 grandcentral: fix interrupt processing. 2022-08-24 14:58:07 +02:00
joevt
3ee2ea1871 Fix read/write argument names
base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.
2022-08-22 17:16:22 -07:00
Maxim Poliakovski
cd1d0031e6 GC: implement attachable IOBus devices. 2022-08-07 15:25:58 +02:00
Maxim Poliakovski
f0553720d6 Catalyst: factory test control. 2022-07-20 01:36:45 +02:00
Maxim Poliakovski
c0078ce97d Refactor MachineBase and MachineFactory classes.
Adding new machines is much easier now.
A significant amount of duplicated code has been reduced.
2022-07-18 20:27:34 +02:00
Maxim Poliakovski
9056d53474 macio: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
5668fc161f macio: fix SWIM3 register space accesses. 2022-06-13 23:15:48 +02:00
Maxim Poliakovski
8889759f33 GrandCentral: improve error logging. 2022-05-21 14:45:33 +02:00
Maxim Poliakovski
533edf6ef5 GrandCentral: properly connect Curio SCSI. 2022-05-17 13:27:58 +02:00
Maxim Poliakovski
d4c08bbe31 Fix ESCC register addressing. 2022-05-07 21:47:22 +02:00
Maxim Poliakovski
4d87ed9b38 Make NVRAM a full-fledged HW component. 2022-03-29 01:55:11 +02:00
Maxim Poliakovski
d71a7b8694 GrandCentral: basic device interrupt handling. 2022-03-28 18:33:59 +02:00
Maxim Poliakovski
e01d0e3d59 GrandCentral: external SCSI (Curio style). 2022-03-28 18:26:47 +02:00
Maxim Poliakovski
4525fd50cc GrandCentral: fix access to NVRAM subdevice. 2022-03-28 18:26:47 +02:00
Maxim Poliakovski
29ce960dbf GrandCentral: access to ESCC and board reg 1. 2022-03-28 18:26:47 +02:00
Maxim Poliakovski
1500c63e26 Initial emulation of the GrandCentral I/O controller. 2022-03-14 18:13:47 +01:00