Commit Graph

16 Commits

Author SHA1 Message Date
Maxim Poliakovski
bb77b2d525 grandcentral: fix interrupt processing. 2022-08-24 14:58:07 +02:00
joevt
3ee2ea1871 Fix read/write argument names
base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.
2022-08-22 17:16:22 -07:00
Maxim Poliakovski
cd1d0031e6 GC: implement attachable IOBus devices. 2022-08-07 15:25:58 +02:00
Maxim Poliakovski
f0553720d6 Catalyst: factory test control. 2022-07-20 01:36:45 +02:00
Maxim Poliakovski
c0078ce97d Refactor MachineBase and MachineFactory classes.
Adding new machines is much easier now.
A significant amount of duplicated code has been reduced.
2022-07-18 20:27:34 +02:00
Maxim Poliakovski
9056d53474 macio: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
5668fc161f macio: fix SWIM3 register space accesses. 2022-06-13 23:15:48 +02:00
Maxim Poliakovski
8889759f33 GrandCentral: improve error logging. 2022-05-21 14:45:33 +02:00
Maxim Poliakovski
533edf6ef5 GrandCentral: properly connect Curio SCSI. 2022-05-17 13:27:58 +02:00
Maxim Poliakovski
d4c08bbe31 Fix ESCC register addressing. 2022-05-07 21:47:22 +02:00
Maxim Poliakovski
4d87ed9b38 Make NVRAM a full-fledged HW component. 2022-03-29 01:55:11 +02:00
Maxim Poliakovski
d71a7b8694 GrandCentral: basic device interrupt handling. 2022-03-28 18:33:59 +02:00
Maxim Poliakovski
e01d0e3d59 GrandCentral: external SCSI (Curio style). 2022-03-28 18:26:47 +02:00
Maxim Poliakovski
4525fd50cc GrandCentral: fix access to NVRAM subdevice. 2022-03-28 18:26:47 +02:00
Maxim Poliakovski
29ce960dbf GrandCentral: access to ESCC and board reg 1. 2022-03-28 18:26:47 +02:00
Maxim Poliakovski
1500c63e26 Initial emulation of the GrandCentral I/O controller. 2022-03-14 18:13:47 +01:00