Commit Graph

417 Commits

Author SHA1 Message Date
joevt
8764beba39 ppcopcodes: Fix lswx.
- Remove invalid form check unless you know for sure it's supposed to cause an exception.
- Add register skip for 601 CPU. This needs testing.
2024-02-20 01:57:00 +01:00
joevt
cf4ce01ddd ppcopcodes: set DSISR for alignment exception. 2024-02-20 01:22:55 +01:00
dingusdev
29f3ffd474 Continued clean-up, part 2 2024-02-18 07:06:27 -07:00
dingusdev
b160e38f8f Continued code clean-up 2024-02-16 06:55:13 -07:00
dingusdev
38d94e509f Further code cleanup 2024-02-14 22:19:08 -07:00
dingusdev
ec23a532f6 Minor clean-up for branching instructions 2024-02-12 20:59:04 -07:00
joevt
d0b0b8070c ppcopcodes: Fix l*ux? invalid form check.
Invalid form is (reg_a == reg_d) || reg_a == 0.
Therefore, valid form is (reg_a != reg_d) && reg_a != 0
!(a || b) == !a && !b
2024-02-11 07:41:13 -07:00
joevt
fd81d7b040 ppcfpopcodes: Fix load float.
Type casting an int to a float assigns the value of the int to the float which is not what is needed here.
2024-02-11 07:40:17 -07:00
joevt
267a9448ea ppctest: Fix floating-point tests.
genppctests.py
- Fix incorrect bits for some floating-point instruction opcodes or fields.
- Use separate register for FP results like DolphinPPCTests does.
- Remove extra FMULS.
- Use a regular expression for parsing ppcfloattest.txt. Don't parse the values, just put them in the output ppcloattests.csv file.

ppcfloattest.txt
- Clear crf0 and crf7 because we only care about crf1.
- Use values from DolphinPPCTests (0.0, 0.5, 1.0, 3.5, DBL_MAX, FLT_MAX, 2.4679999352, 4.9359998704, etc.). Some of the values were rounded. This will un-round them. Specify snan or qnan instead of nan.
- One of the FCMPO and FCMPU tests had qnan instead of snan input values.

ppcfloattest.csv
- Regenerate this file using the updated genppctests.py which uses the updated ppcfloattest.txt.

ppctests
- Update double_from_string to be able to parse the new values (snan, qnan, FLT_MAX, DBL_MAX).
2024-02-10 14:56:21 -07:00
joevt
01e45d656e ppcfpopcodes: Update header date. 2024-02-10 14:47:46 -07:00
joevt
9199b1e520 ppcfpopcodes: Fix multiply add opcodes.
Use std::fma for all of them for max accuracy.
For single precision opcodes, convert only the result, not the operands.
2024-02-10 14:19:09 -07:00
joevt
3be22dac99 ppcfpopcodes: No float cast for operand check. 2024-02-10 14:18:49 -07:00
joevt
ff895aa8a4 ppcfpopcodes: Remove some globals.
ppc_result64_d and ppc_dblresult64_d don't need to be globals. The rest are unused.
2024-02-10 13:56:07 -07:00
joevt
c9c4280e6e ppcfpopcodes: No float cast for operand check. 2024-02-10 13:02:49 -07:00
joevt
dac9c1e52c ppcfpopcodes: Fix fctiw* round to nearest.
0.3 should not round up to 1.
2024-02-10 12:58:58 -07:00
joevt
a7e6ab33a1 ppcfpopcodes: Make fctiw* results QNaN. 2024-02-10 12:58:29 -07:00
joevt
6c49b87a06 ppcopcodes: Fix rlwnm when shift > 31. 2024-02-10 12:54:41 -07:00
joevt
29e5bbdcc0 ppcopcodes: Fix divw. 2024-02-10 12:54:12 -07:00
joevt
4fcb357e2f ppcfpopcodes: add 601 variant of mffs. 2024-02-10 12:51:48 -07:00
joevt
ddb5259464 ppcexec: Make illegal operations per CPU model. 2024-02-10 12:51:00 -07:00
dingusdev
52dfc0cf93 Slightly faster typecasting 2024-01-31 08:06:33 -07:00
joevt
bf425884fb ppcopcodes: Add ppc_grab_dab.
For instructions that don't use the general purpose registers.
2024-01-19 12:09:24 +01:00
joevt
4430fd89a9 ppcopcodes: Fix subfic. 2024-01-19 12:00:55 +01:00
dingusdev
a0b1d6394a Another revert
This affects Virtus VR - With the lmw checks, the opening sign doesn't display and the intro crashes sooner
2024-01-07 17:45:05 -07:00
dingusdev
c6af1e31fe Partial revert of previous commit 2024-01-07 17:21:11 -07:00
dingusdev
a5ce6a806f CPU clean-up 2024-01-07 17:04:51 -07:00
dingusdev
a59475af1c Further lha(*) fixes 2024-01-05 19:10:05 -07:00
dingusdev
1cc1ac2e68 Fixing lha(*) opcodes 2024-01-05 17:19:03 -07:00
dingusdev
924b80574a Further fix from last commit 2024-01-05 15:53:56 -07:00
dingusdev
f3a759c80d CPU code clean-up 2024-01-05 15:11:37 -07:00
Maxim Poliakovski
9b30dfb474 ppcfpopcodes: refactor fctiw/fctiwz emulation. 2024-01-03 01:27:21 +01:00
joevt
0100e67ebf ppcfpopcodes: Fix fctiw/fctiwz. 2024-01-03 01:07:53 +01:00
joevt
bd419912b5 ppcfpopcodes: Fix stfs*.
It should try to convert its operand to a single precision
floating point number at least.
2024-01-02 21:53:03 +01:00
Maxim Poliakovski
cb85d358d1 Remove unused globals. 2024-01-02 17:51:12 +01:00
Maxim Poliakovski
5b114c2412 ppcopcodes: refactor mtcrf emulation. 2024-01-02 17:44:35 +01:00
Maxim Poliakovski
c25b027de4 ppcfpopcodes: fix mtfsf emulation. 2024-01-02 17:21:08 +01:00
Maxim Poliakovski
8595dd7d99 ppcfpopcodes: fix mtfsfi emulation. 2024-01-02 17:21:08 +01:00
joevt
61a90e2cfb ppcfpopcodes: Fix mcrfs. 2024-01-02 15:52:30 +01:00
Maxim Poliakovski
593508df22 Refactor subfze. 2024-01-02 13:44:56 +01:00
joevt
1f3505f371 ppcopcodes: Fix subfze. 2024-01-02 13:44:13 +01:00
Maxim Poliakovski
fef5bde0c7 Refactor recent subfme fix. 2023-12-24 02:56:47 +01:00
joevt
dc00879419 ppcopcodes: Fix subfme. 2023-12-24 02:36:34 +01:00
joevt
bae488fd97 ppcfpopcodes: Fix lfs* opcodes. 2023-12-22 13:11:13 +01:00
joevt
0a8c1df968 ppcopcodes: Fix sraw. 2023-12-19 16:30:02 +01:00
joevt
4c49558120 ppcopcodes: Fix subfe. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
750f91e339 ppcemu.h: add enum for XER bits. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
d24b5d21b8 CRx_bit enum stores masks for now. 2023-12-19 14:27:57 +01:00
Maxim Poliakovski
9dbfde1a4c Cleanup previous commit. 2023-12-19 13:15:10 +01:00
joevt
7f229b0fe8 ppcfpopcodes: Fix fcmpo/fcmpu.
It was always changing CR1 (starting at CR bit 4) instead of the CR selected by crfD.
Also, it was clearing all but the FL,FG,FE,FU bits of FPRF of FPSCR.
2023-12-19 13:15:10 +01:00
dingusdev
7cf3d9cd94
Merge pull request #72 from mihaip/upstream-ub
Avoid some undefined behavior
2023-12-08 06:45:44 -07:00