Commit Graph

121 Commits

Author SHA1 Message Date
joevt
cb88bab67d ppcopcodes: Fixes for SPRs.
- Rename DEC to DEC_S and add DEC_U.
- MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction.
- For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601.
- For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC.
- For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
2024-04-10 07:21:54 -07:00
joevt
4f45d7de35 cpu: Add cpu options to ppc_cpu_init.
The first option is a flag that enables MPC601 (POWER) instructions for CPUs that are not MPC601.
This can be useful for the following reasons:
1) To produce results similar to classic Mac OS which emulates MPC601 instructions on CPUs that don't implement MPC601 instructions. This option is used to compare the risu traces produced in Mac OS 9 on a G3 or G4 with DPPC.
2) May increase performance in apps that use POWER instructions on emulated machines with CPUs that are not MPC601. It is not known if any such apps exist but there could be since Apple included MPC601 emulation in classic Mac OS.
2024-04-10 06:43:18 -07:00
joevt
6267685920 ppcexec: Make EXEF_TIMER separate variable. 2024-03-31 12:15:48 -07:00
joevt
5b4ed01bec ppcexec: Make separate enum for shift instructions. 2024-03-27 18:43:46 -07:00
joevt
64df253053 ppcexec: Rename bool function enums.
Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
dingusdev
ec56dffd19 Adding missing includes 2024-03-26 19:25:05 -07:00
joevt
19ba15f2f1 ppc: Separate enums for separate fields. 2024-03-26 06:44:26 -07:00
dingusdev
1510c45ecb Fixed 601 flags 2024-03-26 06:36:32 -07:00
dingusdev
5631485465 Cleaning up templating 2024-03-24 14:06:07 -07:00
dingusdev
c281b27220 Attempted templating for interpreter 2024-03-24 12:21:19 -07:00
joevt
1d5502dc3c ppcemu: Make flags atomic.
For flags that might be accessed by other threads.
2024-03-22 19:04:51 -07:00
dingusdev
4ef3c792de Refactoring interpreter, pt. 1
Reduce the number of global variables used by interpreter
2024-03-22 08:01:29 -07:00
dingusdev
daeecbe99e Clean-up bc and bcl
Using templating to make the code a touch more readable
2024-03-08 19:22:25 -07:00
Mihai Parparita
57e6e90002 Add support for the CUDA_RESTART_SYSTEM command
There are cases where when it's necessary (e.g. given uninitialized NVRAM,
the Beige G3 with the 10.2 install CD inserted will update the boot
device and restart to boot from it).

Restart support was done by wrapping the ppc_exec function in a loop and
checking for a restart power off reason. We also need to disconnect all
event listeners, since they will be recreated when the machine is
re-initialized.
2024-03-07 23:32:23 -08:00
dingusdev
eb07a3c2f1 Templating bclr to match with bcctr 2024-03-07 20:44:36 -07:00
joevt
67bd47f11f ppcopcodes: Fixes for bcctr(l)?.
Add MPC601 variants. Variants that decrement and test the ctr are invalid bon't don't appear to trigger an exception. The manual says MPC601 can decrement the counter. Other CPUs do not decrement the counter but will branch based on the value.
2024-03-07 06:55:54 -07:00
joevt
e44676e491 ppcfpopcodes: Template mffs variants. 2024-03-07 06:45:46 -07:00
joevt
20b4a33c00 ppcexec: Remove EXHAUSTIVE_DEBUG. 2024-03-05 07:05:03 -07:00
joevt
177098c957 debugger: Fix interrupt signal.
Typing Control-C in Terminal app causes an interrupt signal that should enter the DPPC debugger but this only worked once since the signal handler never returned. Even if the signal handler reenabled the signal somehow, it calls enter_debugger recursively which is strange since the earlier calls to enter_debugger would never return.

Now the signal handler just sets a flag (power_on) which can be used to exit any loop (emulator loops, stepping loops, disassembly loops, dumping loops).

Main always calls enter_debugger now which calls the ppc_exec loop. The power_on flag will exit the ppc_exec loop to return to the debugger. Recursion of enter_debugger is eliminated except for calls to loguru's ABORT_F.

An enum power_off_reason is used to indicate why the power_on flag is set to false and to determine what happens next.
2024-03-02 12:57:02 -07:00
joevt
888df0ac53 debugger: Add more register names for reg_op.
So the debugger can output their values.
2024-02-29 07:46:16 -07:00
dingusdev
d71a213c4b Continued clean-up, part 3 2024-02-22 19:46:34 -07:00
dingusdev
8e9123bdce Slightly less clumsy check for compiler 2024-02-21 07:14:21 -07:00
joevt
cf4ce01ddd ppcopcodes: set DSISR for alignment exception. 2024-02-20 01:22:55 +01:00
joevt
ff895aa8a4 ppcfpopcodes: Remove some globals.
ppc_result64_d and ppc_dblresult64_d don't need to be globals. The rest are unused.
2024-02-10 13:56:07 -07:00
joevt
4fcb357e2f ppcfpopcodes: add 601 variant of mffs. 2024-02-10 12:51:48 -07:00
joevt
ddb5259464 ppcexec: Make illegal operations per CPU model. 2024-02-10 12:51:00 -07:00
dingusdev
a5ce6a806f CPU clean-up 2024-01-07 17:04:51 -07:00
dingusdev
f3a759c80d CPU code clean-up 2024-01-05 15:11:37 -07:00
joevt
0100e67ebf ppcfpopcodes: Fix fctiw/fctiwz. 2024-01-03 01:07:53 +01:00
Maxim Poliakovski
cb85d358d1 Remove unused globals. 2024-01-02 17:51:12 +01:00
Maxim Poliakovski
750f91e339 ppcemu.h: add enum for XER bits. 2023-12-19 14:57:41 +01:00
Maxim Poliakovski
d24b5d21b8 CRx_bit enum stores masks for now. 2023-12-19 14:27:57 +01:00
Maxim Poliakovski
9dbfde1a4c Cleanup previous commit. 2023-12-19 13:15:10 +01:00
joevt
7f229b0fe8 ppcfpopcodes: Fix fcmpo/fcmpu.
It was always changing CR1 (starting at CR bit 4) instead of the CR selected by crfD.
Also, it was clearing all but the FL,FG,FE,FU bits of FPRF of FPSCR.
2023-12-19 13:15:10 +01:00
Maxim Poliakovski
99ae0c3d31 ppcemu.h: add PVR definition for MPC604e. 2023-12-03 20:05:19 +01:00
Mihai Parparita
6582536591 Inline ppc_set_cur_instruction
It's used in the main emulator loop (ppc_exec_inner), and the function
call overhead adds up.

By inlining it, time to boot to the Finder using a 7.1.2 install CD
and a 6100 ROM goes from ~6700ms to ~6400ms (with clang 14 on a
M2 Max)
2023-12-02 15:12:02 -08:00
Maxim Poliakovski
a1d8f8aa4e ppctests: fix test cases with SNaN/QNaN operands. 2023-11-30 17:44:46 +01:00
Maxim Poliakovski
6abb07e61b Add rounding control for the host FPU. 2023-11-30 12:06:44 +01:00
Maxim Poliakovski
d49d03846f ppcemu: fix and beatify FPSCR enum. 2023-11-30 12:06:44 +01:00
dingusdev
7835aec034 Further CPU cleanup 2023-11-21 08:06:50 -07:00
dingusdev
d92ae6136a CPU code clean-up in progress
Happened to fix one case in the process.
2023-11-19 17:56:30 -07:00
Maxim Poliakovski
c47cbb354d Add is_601 flag for selecting MPC601 specific behavior. 2023-09-18 21:20:59 +02:00
joevt
300965ab10 Decrementer exception changes. 2023-08-10 00:46:04 +02:00
dingusdev
4364c89fd4 Slight clean-up for execution type 2023-06-19 22:36:27 -07:00
Maxim Poliakovski
597c077b19 Implement PPC decrementer. 2023-02-15 02:36:40 +01:00
Maxim Poliakovski
7ba8921649 ppcemu: add PVR for 603ev. 2022-12-23 17:19:46 +01:00
joevt
6f0d3b48ba Fix TBR range
Fixed an issue where TBR doesn't have full 64-bit range. The original calculation was 64 bit and ended with a ÷ 10^9. This means the max for the upper 32 bits is 2^32/10^9 = 4. The solution is to use a multiplication method that supports a 96 bit product. core/mathutils.h contains functions for that. TBR driving frequency is assumed to be less than 1 GHz. Some minor modification is required for future > 1 GHz support.
2022-09-15 21:22:37 -07:00
joevt
01d7d6bac3 Make accessing RTC or TBR not affect the other
Fixed an issue where the following would cause inconsistent results (tb in the left column would sometimes decrement instead of always incrementing):
2 0 do 2 0 do cr tb@ 8 u.r ." ." 8 u.r loop 2 0 do cr 12 spaces rtc@ 8 u.r ." ." 8 u.r loop 2 0 do cr tb@ 8 u.r ." ." 8 u.r space rtc@ 8 u.r ." ." 8 u.r loop loop

RTC and TBR could not be used simultaneously because they are both incremented by an amount based on the last time stamp but that time stamp can be changed by accessing either RTC or TBR. The solution is to have a different time stamp for each.
2022-09-15 20:21:54 -07:00
Maxim Poliakovski
b38d00ce2d cpu/ppc: improve support for external interrupts.
Support generating of external interrupt exception
in MTMSR and RFI when MSR[EE] is re-enabled and
external interrupt still pending.
2022-08-24 14:15:47 +02:00
Maxim Poliakovski
8c0f391548 ppcemu: add enums for HID0 and HID1. 2022-08-15 14:45:55 +02:00