joevt
67a5c39b1c
ppcopcodes: Add Privileged exception for SPRs.
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Accessing an SPR with bit 4 set (> 15) requires supervisor privilege and should cause a supervisor-level instruction exception (privileged instruction type program exception).
2024-04-10 07:21:23 -07:00
joevt
0273867c49
ppcopcodes: Cleanup ppc_changecrf0.
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- Use one assignment to set ppc_state.cr.
- Use enums for CR and XER bits.
- Use < to check sign bit.
2024-04-10 06:47:10 -07:00
joevt
1e50d88183
ppcopcodes: Use macro to grab instruction fields.
2024-04-10 06:46:46 -07:00
joevt
29a832c68d
ppcopcodes: Use < 0 instead of & 0x8000000.
2024-04-10 06:45:31 -07:00
joevt
cb05bd05eb
cpu: Add ppc_grab_regssash macro.
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This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
2024-04-10 06:43:34 -07:00
joevt
4f45d7de35
cpu: Add cpu options to ppc_cpu_init.
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The first option is a flag that enables MPC601 (POWER) instructions for CPUs that are not MPC601.
This can be useful for the following reasons:
1) To produce results similar to classic Mac OS which emulates MPC601 instructions on CPUs that don't implement MPC601 instructions. This option is used to compare the risu traces produced in Mac OS 9 on a G3 or G4 with DPPC.
2) May increase performance in apps that use POWER instructions on emulated machines with CPUs that are not MPC601. It is not known if any such apps exist but there could be since Apple included MPC601 emulation in classic Mac OS.
2024-04-10 06:43:18 -07:00
dingusdev
9c95bc17fe
Implement VX and FEX updates for mtfsfi
2024-04-09 21:11:09 -07:00
dingusdev
2c94cfee03
Removing currently unneeded functions
2024-04-09 18:34:36 -07:00
joevt
3c16870f86
ppcmmu: Replace defines.
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They may interfere with system headers.
2024-04-09 07:57:48 -07:00
Maxim Poliakovski
524daa45a5
ppcexec.cpp: fix compilation with Apple Clang 10.
2024-04-07 20:39:24 +02:00
joevt
9ed1a118e6
ppcmmu: Check sizeof(T) explicitly.
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I don't know if the compiler is smart enough to figure out that ((guest_va & 0xFFF) + sizeof(T)) > 0x1000) is always false when sizeof(T) == 1 so we'll add a check for sizeof(T) > 1.
2024-04-07 08:59:05 -07:00
dingusdev
a5a5410515
Continued fixing floating-point ops
2024-04-07 08:58:38 -07:00
dingusdev
40a4ca31b9
More minor floating-point clean-up
2024-04-07 07:23:30 -07:00
dingusdev
7f44ab2262
Minor fixes to floating point
2024-04-06 17:31:03 -07:00
dingusdev
123c927b1a
Another refactor for floating points
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FCMPO and FCMPU passes the tests now*
2024-04-06 11:02:03 -07:00
dingusdev
43d87b4791
Temp revert for icnt_factor
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We should, at minimum, make icnt_factor adjustable. That said, powermax is suggesting we develop a more sophisticated scheduler.
2024-03-31 14:13:45 -07:00
joevt
6267685920
ppcexec: Make EXEF_TIMER separate variable.
2024-03-31 12:15:48 -07:00
joevt
48882f3fec
ppcexec: Adjust icnt_factor.
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So that 1000 ms takes ≈ 1 second in Open Firmware on 4 GHz Intel CPU.
2024-03-31 11:51:04 -07:00
joevt
0ac54ea1ea
ppcexec: Add host time option.
2024-03-31 11:50:55 -07:00
joevt
d9b02ecd8d
ppcmmu: Check 8 byte alignment spanning pages.
2024-03-28 07:53:03 -07:00
joevt
b9c12e44a4
ppcopcodes: Cleanup 3.
2024-03-28 07:36:40 -07:00
joevt
58ed5bb56e
ppcexec: Opcode initialization to one function.
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Move all opcode initialization to initialize_ppc_opcode_tables.
Some opcodes are illegal for some processors.
2024-03-28 07:35:57 -07:00
joevt
094f44e92c
ppcopcodes: Make MQ read only on non-601 CPUs.
2024-03-28 07:29:50 -07:00
joevt
566706dd62
ppctests: Fix compiler warnings.
2024-03-28 07:17:38 -07:00
joevt
60a76e9348
ppcexec: Fix branch check in ppc_exec_single.
2024-03-28 07:17:13 -07:00
joevt
f55ad323b4
ppcdisasm: Fix order of operands.
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For cntlzw, extsh, extsb.
2024-03-28 07:09:50 -07:00
joevt
78558e4c52
debugger: Ensure space between opcode and operand.
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Instructions that are 8 characters or longer (such as mtdbat3l) did not have a space between opcode and operand. Now there is always a space. The width of the opcode column is unchanged except for those opcodes that have 8 or more characters.
2024-03-28 06:54:23 -07:00
joevt
c9d4cc3321
ppcmmu: Remove old and slow code.
2024-03-27 20:13:45 -07:00
joevt
0f8a464157
ppcmmu: Use MSR enums for calculating mmu_mode.
2024-03-27 18:44:59 -07:00
joevt
e4a675babb
ppcmmu: Remove line feed from log messages.
2024-03-27 18:44:42 -07:00
joevt
5b4ed01bec
ppcexec: Make separate enum for shift instructions.
2024-03-27 18:43:46 -07:00
joevt
64df253053
ppcexec: Rename bool function enums.
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Use "logical" since the functions deal with multiple bits instead of a single boolean value and because the 601 manual calls them Logical Instructions.
Use "ppc" for the enums because logical_and is defined elsewhere and because the original DPPC code used these names for those functions.
2024-03-27 18:43:35 -07:00
joevt
d8129bd643
ppcexec: Add comments for macros.
2024-03-27 18:43:15 -07:00
Maxim Poliakovski
6aa54b8dda
ppcexec: break long lines, improve indentation.
2024-03-27 13:55:05 +01:00
Maxim Poliakovski
0ff911cc26
poweropcodes: cosmetic improvements.
2024-03-27 03:45:22 +01:00
Maxim Poliakovski
b5b14b2f9d
ppcopcodes: cosmetic improvements.
2024-03-27 03:36:17 +01:00
Maxim Poliakovski
2b6f41e0d0
poweropcodes: use XER constants instead of magic numbers.
2024-03-27 03:36:17 +01:00
Maxim Poliakovski
9b429cc751
ppcopcodes: replace magic numbers with XER constants.
2024-03-27 03:36:17 +01:00
dingusdev
ec56dffd19
Adding missing includes
2024-03-26 19:25:05 -07:00
dingusdev
a09f2093b5
Optimize register initialization
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Courtesy of joevt, adapted to fit the C++ standard
2024-03-26 18:52:56 -07:00
dingusdev
b15d3be88a
Moving is_601 up, so the opcodes get initialized correctly
2024-03-26 18:41:16 -07:00
joevt
224ae50e91
ppcexec: Make more instructions illegal for 601.
2024-03-26 06:50:33 -07:00
joevt
03d7728d46
ppcexec: Use macros to assign subopcode functions.
2024-03-26 06:50:17 -07:00
joevt
19ba15f2f1
ppc: Separate enums for separate fields.
2024-03-26 06:44:26 -07:00
joevt
9da9967b83
ppcopcodes: Cleanup 2.
2024-03-26 06:37:45 -07:00
dingusdev
1510c45ecb
Fixed 601 flags
2024-03-26 06:36:32 -07:00
dingusdev
9b76c9fe3e
Fix for mffs in opcode table
2024-03-25 20:04:13 -07:00
dingusdev
3c3d0b46db
Merge branch 'master' into cpu-refactor2
2024-03-25 07:45:21 -07:00
joevt
f08d9ba81e
ppcexec: Fix templated lhzux.
2024-03-25 07:43:34 -07:00
joevt
b9aae48517
ppcopcodes: Fix templated st.
2024-03-25 07:37:54 -07:00
