Commit Graph

647 Commits

Author SHA1 Message Date
joevt b280da81bc ppc: Timing calculation changes.
Note: all timings are relative to virtual time which is 16 ns per instruction. 8 ns per instruction is too fast for the PDM 'mach' gestalt calculation in firmware.

- For MPC601, bit 7 of RTC and DEC changes at 7.8336 MHz so bit 0 would change at 1.0027008 GHz. Therefore multiply time base frequency by 128. For MPC601, DEC now changes at 1.0027008 GHz instead of 7.8336 MHz.
- Add tbr_freq_shift for cases where time base frequency exceeds 1GHz.
- Change calc_rtcl_value to use time base frequency. For MPC601, RTC now changes at 1.0027008 GHz instead 1GHz.
- For MPC601, the 7 least significant bits of DEC are not implemented so make them not getable or setable.
2025-04-08 19:46:48 -07:00
joevt 6363eef32f ppcexec: Make opcode macros depend on OPr. 2025-04-08 19:46:20 -07:00
joevt ba9bbb32c3 Catch all errors for debug read/write methods. 2025-03-23 16:14:31 -07:00
dingusdev 130beabf2a Re-insert code for tlbia
BeOS uses this as part of its boot handler.
2025-03-21 18:57:17 -07:00
dingusdev a7170f4956 Removing code for tlbia
Seems to be causing a regression in Mac OS X 10.0
2025-03-21 18:42:56 -07:00
joevt ae605157db debugger: Add fregs command. 2025-03-10 07:15:44 -07:00
dingusdev 6e74146466 Don't forget to update CR1 in edge case of fdiv 2025-03-02 10:42:31 -07:00
dingusdev a972bd26f7 Corrected handling of MMU Mode 1 2025-03-02 10:41:42 -07:00
dingusdev b09dfa22ec Fix regression in fdiv(s)(.) 2025-03-01 15:18:24 -07:00
dingusdev f3dec30c27 Add missing PR bit checks 2025-02-26 20:40:41 -07:00
dingusdev a848eb9e76 Fixed accidental removal in ppc_exec_until 2025-02-16 06:35:24 -07:00
dingusdev d82d9ac7b9 Added missing header - chrono 2025-02-15 16:02:32 -07:00
joevt 82a48899f0 Change ppc_opcode_grabber to a variable. 2025-02-10 07:01:32 -07:00
joevt 2f30395d00 Break long lines.
Make them 130 characters or less.
2025-01-30 06:30:51 -07:00
Mihai Parparita 134339ae9d Mitigate performance impact of respecting FP bit
In #135 we switched from a static OpcodeGrabber table to a
curOpcodeGrabber pointer in ppc_main_opcode. This results in an extra
indirection (as far as generated assembly having an additional load),
which reduces execution speed.

Switch to making the opcode grabber into a parameter to
ppc_main_opcode, and make ppc_exec_inner keep it up to date (via an
EXEF_OPCODE exception flag).

Also fixes FPU instructions in ppctests - we now need to set the FP
MSR bit when initializing the CPU.
2025-01-25 17:58:31 -08:00
Mihai Parparita acc6e77ec5 Respect FP bit in MSR when running floating point instructions
Rather than running them normally, they should trigger a "no FPU"
exception. This appears to be required to allow correct graphical
rendering under Mac OS X - the FP bit cleared via mtmsr and rfi
instructions and something else appears to be relying on the exception
to be thrown.

Implemented by maintaining a parallel version of the OpcodeGrabber
table (OpcodeGrabberNoFPU) which contains alternate implementations
for all the floating point instructions. We switch the table whenever
the MSR value changes. This should minimize the overhead of doing
these checks.
2025-01-20 23:19:37 -08:00
joevt e63f928a3c ppcexec: Simplify ppc_exec_inner.
One while loop instead of two.
One call to ppc_read_instruction instead of four.
2024-12-17 19:01:34 -07:00
joevt 7b1ea17fb8 ppcmmu: Fix compiler warning. 2024-12-17 18:46:53 -07:00
dingusdev 240ec95a74 bench1: Set power_off_reason. 2024-12-17 18:46:20 -07:00
joevt e4d9cb95b4 ppcexec: Make ppc_exec template functions. 2024-12-14 06:32:07 -07:00
joevt 98c7e224fe ppcmacros: Make rot_sh unsigned. 2024-12-14 06:31:59 -07:00
joevt ac0faf78fd poweropcodes: Fix more compiler warnings. 2024-12-14 06:31:51 -07:00
joevt d48eefceb0 poweropcodes: Remove undefined behavior.
Shift 32 is undefined.
-2^31 - 1 is undefined.
2024-12-12 08:03:47 -07:00
joevt 78f62c8db8 ppcfpopcodes: Use macros for ppcstate.
Helps with abstraction.
2024-12-10 18:18:32 -07:00
joevt a64b000459 ppcfpopcodes: Remove extra space. 2024-12-10 18:18:23 -07:00
joevt 1da7cb1c2f ppcmacros: Remove semicolon from one line macros. 2024-12-10 18:18:12 -07:00
joevt 49b8c4c39f ppcfpopcodes: Fix Revert Tweak.
Fixes lfsu, lfsux, lfdu, lfdux so they correctly update rA as before.
2024-12-11 00:19:06 +01:00
dingusdev 47969d9d50 Reverting tweak
Restoring Virtus Player back to 'normal'
2024-12-07 20:49:00 -07:00
Mihai Parparita ab5f7071ce Suppress Clang warnings about volatile being deprecated 2024-12-07 15:30:24 -08:00
joevt cea889bde5 ppcopcodes: Cleanup lzu lzux lhau lhaux. 2024-12-07 06:34:00 -07:00
dingusdev d22f926a8a Tweak s*u(x) and l*u(x) instructions for 601
These are what the instructions are supposed to do according the 601 manual.
2024-12-06 07:07:36 -07:00
joevt b512702fbb ppcopcodes: Fix indent in ppc_mtsr. 2024-12-03 06:52:20 -07:00
joevt 47fca9f4ff ppcexec: Fix absolute address comment. 2024-12-03 06:52:09 -07:00
joevt ee8c912397 poweropcodes: Fix clcs for MPC601.
These output values will pass the current set of risu tests which tests all 32 input values multiple times.
2024-12-03 06:51:56 -07:00
joevt 3fd422008e ppcfpopcodes: Use enums instead of literals. 2024-12-03 06:51:15 -07:00
joevt bce4c98475 ppcfpopcodes: Fix fdiv for MPC601. 2024-12-03 06:50:57 -07:00
joevt b45b0a8df4 ppcopcodes: Fix divw for MPC601. 2024-12-03 06:50:17 -07:00
joevt b8af8d387c ppcopcodes: Fix divu for MPC601. 2024-12-03 06:50:08 -07:00
joevt 84075c5988 ppcopcodes: Fix lswx for MPC601. 2024-12-03 06:49:53 -07:00
dingusdev 35919802f3 Tweak fsel
Inspired by a similar fix toxieainc committed for Supermodel
2024-12-03 06:49:08 -07:00
joevt 80b763ecc3 ppcexec: Fix OP59d.
Some of these accept a 4th register "C" so they exist in the opcode table 32 times.
Some of these don't accept a 4th register "C" so they exist in the opcode table once.
2024-12-03 12:12:56 +01:00
dingusdev f355fb0dfe Merge pull request #127 from mihaip/upstream-opcode-dispatcher
ppc: Use a unified opcode lookup table
2024-11-30 12:51:08 -07:00
Mihai Parparita b759f25d87 ppc: Use a unified opcode lookup table
Instead of a primary opcode lookup table with 64 entries and a few
smaller tables with 4-2048 entries, use a single 64 * 2048 (128K)
entry table to dispatch opcodes.

Helps with performance, since we avoid the function call overhead for
some frequently-used instructions (e.g. branch, integer, floating point).
Saves ~2 seconds from the time to Welcome to Macintosh (same measurement
methodology as #125)

Secondarily also makes opcode registration/decoding a bit more uniform,
and scannable, since it's now all in initialize_ppc_opcode_table.
2024-11-30 20:37:26 +01:00
Maxim Poliakovski aa17bf06de ppcmmu: implement mem_write_dbg method. 2024-11-30 11:55:16 +01:00
Mihai Parparita bf92b04d6c debugger: Use a named constant when we don't have a current instruction 2024-11-29 18:33:22 +01:00
Mihai Parparita 564c43c907 Remove ppc_cur_instruction global variable
Replace it wth an explicit opcode parameter that is passed around. That
is both slightly easier to reason about (to trace where it comes from)
and slightly faster, since it can be read from a register.

On my machine takes booting to "Welcome to Macintosh" being output in
a verbose boot of Mac OS X 10.2.8 from 31.8s to 30.6s (average of 5
runs, measured using deterministic mode and looking at when execution
reaches PC 0x90004a88).
2024-11-28 23:41:38 +01:00
Mihai Parparita 2d90aff408 ppc: Remove unncesessary function declarations
ppc_opcode16 and other functions are only needed in the implementation in
ppcexec.cpp, they don't need to be in the header.

fp_return_double and fp_return_uint64 have no uses (as of 2141a72b87)
can can thus be removed altogether.

Similarly ppc_fpu_off has no uses (as of bb3f4e596e)
and can be removed.
2024-11-28 22:12:16 +01:00
joevt 820da037da ppcmacros: Add missing space. 2024-11-28 07:25:23 -07:00
joevt 00f38133e9 ppcfpopcodes: fnabs fix.
fnabs sets the sign bit regardless of nan status.
2024-11-28 07:25:14 -07:00
joevt e231dc4dec ppcfpopcodes: fabs fix.
fabs clears the sign bit regardless of nan status.
2024-11-28 07:25:06 -07:00