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117 lines
7.3 KiB
Markdown
117 lines
7.3 KiB
Markdown
The PowerPC is the main processor used for Power Macs. Currently, DingusPPC only implements the 32-bit variant.
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# General Notes
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All instructions are 32 bits wide, regardless of whether the PowerPC is in 32-bit or 64-bit mode.
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# BATs
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The 601 BATs are emulated by the Open Firmware.
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# TLBs
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Up to 128 instruction entries and 128 data entries can be stored at a time.
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# Processor Revisions
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| Model | PVR Number | Notable Aspects |
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| :------------ | :---------- | :-------------------------- |
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| 601 | 0x00010001 | Supports POWER instructions |
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| 603 | 0x00030001 | Software-controlled TLBs |
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| 604 | 0x00040103 | Ability for Multiprocessing |
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| 603E | 0x00060101 | |
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| 750 (G3) | 0x00080200 | Built-in L2 data cache |
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| 7400 (G4) | 0x000C0101 | AltiVec/VMX support added |
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# Registers
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| Register Type | Number | Purpose |
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| :----------------------------------------- | :--------------------- | :------------------------------------------------------------------ |
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| General Purpose (GPR) | 32 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Floating Point (FPR) | 32 | Calculate, Store, and Load 32-bit or 64-bit floating-point numbers |
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| Special Purpose (SPR) | Up to 1024 (in theory) | Store and load specialized 32-bit fixed-point numbers |
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| Segment (SR) | 16 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Time Base Facility (TBR) | 2 | Calculate, Store, and Load 32-bit fixed-point numbers |
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| Condition Register | 1 | Stores conditions based on the results of fixed-point operations |
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| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
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| Vector Status and Control Register (VSCR) | 1 | Stores conditions based on the results of vector operations |
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| Machine State Register (MSR) | 1 | Stores the state of the processor |
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# Special Registers
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| Register Name | Register Number | Purpose |
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| :-------------------------------- | :------------------- | :---------------------------------------------------- |
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| Multiply Quotient Register (MQ) | 0 | (601 only) |
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| Integer Exception (XER) | 1 | |
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| RTC Upper Register (RTCU) | 4 | (601 only) |
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| RTC Lower Register (RTCL) | 5 | (601 only) |
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| Link Register (LR) | 8 | |
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| Counter Quotient Register (CTR) | 9 | |
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| Search Description Register (SDR1)| 25 | Specifies starting address of the page table |
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| Save and Restore Register 0 (SRR0)| 26 | |
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| Save and Restore Register 1 (SRR1)| 27 | |
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| Vector Save/Restore | 256 | (G4+) |
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| Time Base Lower (TBL) | 268 | (603+) |
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| Time Base Upper (TBU) | 269 | (603+) |
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| External Access (EAR) | 282 | |
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| Processor Version (PVR) | 287 | |
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| Hardware Implementation 0 (HID0) | 1008 | |
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| Hardware Implementation 1 (HID1) | 1009 | |
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## HID 0
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| Model | Bits Enabled |
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| :------------ | :------------------ |
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| 601 | (NOT PRESENT) |
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| 603 | NHR, DOZE/NAP/SLEEP |
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| 604 | NHR |
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| 603E | NHR, DOZE/NAP/SLEEP |
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| 603EV | NHR, DOZE/NAP/SLEEP |
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| 604E | NHR |
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| 750 (G3) | NHR, DOZE/NAP/SLEEP |
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# Exceptions
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nnn is either 0x000 or 0xFFF, depending on the 25th bit (0x40) set in the MSR. Usually, the 25th bit is set when booting up a system and unset after it is set.
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| Exception | Address |
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| :------------------------------------ | :--------- |
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| System Reset | 0xnnn00100 |
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| Machine Check | 0xnnn00200 |
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| DSI | 0xnnn00300 |
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| ISI | 0xnnn00400 |
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| External Interrupt | 0xnnn00500 |
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| Alignment | 0xnnn00600 |
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| Program | 0xnnn00700 |
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| Floating Point Unavailable | 0xnnn00800 |
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| Decrementer | 0xnnn00900 |
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| System Call | 0xnnn00C00 |
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| Trace | 0xnnn00D00 |
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| Performance Monitor (G3+) | 0xnnn00F00 |
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| AltiVec Unavailable (G4+) | 0xnnn00F20 |
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| Instruction Address Breakpoint (G3+) | 0xnnn01300 |
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| System Management Interrupt (G3+) | 0xnnn01400 |
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| AltiVec Assist (G4+) | 0xnnn01600 |
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| Thermal Management Interrupt (G3+) | 0xnnn01700 |
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# Endianness
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PowerPC supports both big-endian and little-endian modes. Mac OS largely operates in big-endian mode, due to its 68k heritage.
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# Eccentricities
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* The HW Init routine used in the ROMs uses the DEC (decrement; SPR 22) register to measure CPU speed. With a PowerPC 601, the DEC register operates on the same frequency as RTC - 7.8125 MHz but uses only 25 most significant bits. In other words, it decrements by 128 at 1/7.8125 MHz.
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* Apple's memcpy routine uses double floating-point registers rather than general purpose registers to load and store 2 32-bit values at once. As the PowerPC usually operates on at least a 64-bit bus and floating-point processing comes with the processors by default, this saves some instructions and results in slightly faster speeds.
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* As the PowerPC does not have an instruction to load an immediate 32-bit value, it's common to see a lis/ori coding pattern.
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* The 603 relies on the instructions tlbld and tlbli to assist in TLB reloading.
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* To accommodate for early programs compiled on PowerPC 601 Macs, the classic Mac OS has to emulate the POWER instructions that were removed from later processors.
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# References
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http://www.ibmfiles.com/ibmfiles/powerpc/itso_powerpc_inside_view.pdf
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