Macintosh-Tools/macemu
1
0
Fork 0
mirror of https://github.com/kanjitalk755/macemu.git synced 2025-08-07 20:25:23 +00:00
Code Issues Projects Releases Wiki Activity

Remove even more obsolete code. Drop TBL/TBU registers, they are manually

Browse Source 
handled through the mftb instruction accessor.
This commit is contained in:
gbeauche
2003-11-11 11:44:34 +00:00
parent cf0ed72f24
commit e9f3546539
4 changed files with 4 additions and 209 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.cpp
View File

@@ -50,13 +50,11 @@ void powerpc_cpu::set_register(int id, any_register const & value)
case powerpc_registers::XER: xer().set(value.i); break;
case powerpc_registers::LR: lr() = value.i; break;
case powerpc_registers::CTR: ctr() = value.i; break;
case powerpc_registers::TBL: tbl() = value.i; break;
case powerpc_registers::TBU: tbu() = value.i; break;
case basic_registers::PC:
case powerpc_registers::PC: pc() = value.i; break;
case basic_registers::SP:
case powerpc_registers::SP: gpr(1)= value.i; break;
default: abort(); break;
default: abort(); break;
}
}
@@ -77,13 +75,11 @@ any_register powerpc_cpu::get_register(int id)
case powerpc_registers::XER: value.i = xer().get(); break;
case powerpc_registers::LR: value.i = lr(); break;
case powerpc_registers::CTR: value.i = ctr(); break;
case powerpc_registers::TBL: value.i = tbl(); break;
case powerpc_registers::TBU: value.i = tbu(); break;
case basic_registers::PC:
case powerpc_registers::PC: value.i = pc(); break;
case basic_registers::SP:
case powerpc_registers::SP: value.i = gpr(1); break;
default: abort(); break;
default: abort(); break;
}
return value;
}
@@ -104,8 +100,6 @@ void powerpc_cpu::init_registers()
lr() = 0;
ctr() = 0;
pc() = 0;
tbl() = 0;
tbu() = 0;
}
void powerpc_cpu::init_flight_recorder()

4
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-cpu.hpp
View File

@@ -56,10 +56,6 @@ protected:
uint32 & pc() { return regs.pc; }
uint32 pc() const { return regs.pc; }
void increment_pc(int o) { pc() += o; }
uint32 & tbl() { return regs.tbl; }
uint32 tbl() const { return regs.tbl; }
uint32 & tbu() { return regs.tbu; }
uint32 tbu() const { return regs.tbu; }
friend class pc_operand;
friend class lr_operand;

2
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-execute.cpp
View File

@@ -1075,7 +1075,7 @@ void powerpc_cpu::execute_mftbr(uint32 opcode)
uint32 d;
switch (tbr) {
case 268: d = clock(); break;
case 269: d = tbu(); break;
case 269: d = 0; break;
default: execute_illegal(opcode);
}
operand_RD::set(this, opcode, d);

197
SheepShaver/src/kpx_cpu/src/cpu/ppc/ppc-registers.hpp
View File

@@ -25,161 +25,9 @@
* Condition Register
**/
#ifdef PPC_HAVE_SPLIT_CR
class powerpc_crf_register
{
union {
struct {
uint8 lt;
uint8 gt;
uint8 eq;
uint8 so;
} parts;
uint32 value;
};
#ifdef PPC_LAZY_CC_UPDATE
bool lazy_mode;
int32 cc_dest;
#endif
public:
powerpc_crf_register() { clear(); }
void set_so(bool v) { parts.so = v; }
bool is_overflow() const { return parts.so; }
bool is_less() const;
bool is_greater() const;
bool is_zero() const;
void clear();
bool test(int condition) const;
void set(uint32 v);
uint32 get() const;
void compute(int32 v);
};
inline void
powerpc_crf_register::clear()
{
value = 0;
#ifdef PPC_LAZY_CC_UPDATE
lazy_mode = false;
cc_dest = 0;
#endif
}
inline bool
powerpc_crf_register::is_less() const
{
#ifdef PPC_LAZY_CC_UPDATE
if (lazy_mode)
return cc_dest < 0;
#endif
return parts.lt;
}
inline bool
powerpc_crf_register::is_greater() const
{
#ifdef PPC_LAZY_CC_UPDATE
if (lazy_mode)
return cc_dest > 0;
#endif
return parts.gt;
}
inline bool
powerpc_crf_register::is_zero() const
{
#ifdef PPC_LAZY_CC_UPDATE
if (lazy_mode)
return cc_dest == 0;
#endif
return parts.eq;
}
inline bool
powerpc_crf_register::test(int condition) const
{
switch (condition) {
case 0: return is_less();
case 1: return is_greater();
case 2: return is_zero();
case 3: return is_overflow();
}
abort();
return false;
}
inline void
powerpc_crf_register::set(uint32 v)
{
parts.so = standalone_CR_SO_field::extract(v);
#ifdef PPC_LAZY_CC_UPDATE
const uint32 rd = v & (standalone_CR_LT_field::mask() |
standalone_CR_GT_field::mask() |
standalone_CR_EQ_field::mask());
lazy_mode = false;
if (rd == standalone_CR_LT_field::mask()) {
lazy_mode = true;
cc_dest = -1;
return;
}
if (rd == standalone_CR_GT_field::mask()) {
lazy_mode = true;
cc_dest = 1;
return;
}
if (rd == standalone_CR_EQ_field::mask()) {
lazy_mode = true;
cc_dest = 0;
return;
}
#endif
parts.lt = standalone_CR_LT_field::extract(v);
parts.gt = standalone_CR_GT_field::extract(v);
parts.eq = standalone_CR_EQ_field::extract(v);
}
inline uint32
powerpc_crf_register::get() const
{
uint32 value = parts.so;
#ifdef PPC_LAZY_CC_UPDATE
if (lazy_mode) {
if ((int32)cc_dest < 0)
value |= standalone_CR_LT_field::mask();
else if ((int32)cc_dest > 0)
value |= standalone_CR_GT_field::mask();
else
value |= standalone_CR_EQ_field::mask();
return value;
}
#endif
return (parts.lt << 3) | (parts.gt << 2) | (parts.eq << 1) | value;
}
inline void
powerpc_crf_register::compute(int32 v)
{
#ifdef PPC_LAZY_CC_UPDATE
lazy_mode = true;
cc_dest = v;
#else
if (v < 0)
parts.lt = 1, parts.gt = 0, parts.eq = 0;
else if (v > 0)
parts.lt = 0, parts.gt = 1, parts.eq = 0;
else
parts.lt = 0, parts.gt = 0, parts.eq = 1;
#endif
}
#endif
class powerpc_cr_register
{
#ifdef PPC_HAVE_SPLIT_CR
powerpc_crf_register crf[8];
#else
uint32 cr;
#endif
public:
bool test(int condition) const;
void set(uint32 v);
@@ -194,51 +42,32 @@ public:
inline void
powerpc_cr_register::clear(int crfd)
{
#ifdef PPC_HAVE_SPLIT_CR
crf[crfd].clear();
#else
cr &= ~(0xf << (28 - 4 * crfd));
#endif
}
inline void
powerpc_cr_register::set(int crfd, uint32 v)
{
#ifdef PPC_HAVE_SPLIT_CR
crf[crfd].set(v);
#else
clear(crfd);
cr |= v << (28 - 4 * crfd);
#endif
}
inline uint32
powerpc_cr_register::get(int crfd) const
{
#ifdef PPC_HAVE_SPLIT_CR
return crf[crfd].get();
#else
return (cr >> (28 - 4 * crfd)) & 0xf;
#endif
}
inline void
powerpc_cr_register::set_so(int crfd, bool v)
{
#ifdef PPC_HAVE_SPLIT_CR
crf[crfd].set_so(v);
#else
const uint32 m = standalone_CR_SO_field::mask() << (28 - 4 * crfd);
cr = (cr & ~m) | (v ? m : 0);
#endif
}
inline void
powerpc_cr_register::compute(int crfd, int32 v)
{
#ifdef PPC_HAVE_SPLIT_CR
crf[crfd].compute(v);
#else
const uint32 m = (standalone_CR_LT_field::mask() |
standalone_CR_GT_field::mask() |
standalone_CR_EQ_field::mask() ) << (28 - 4 * crfd);
@@ -249,45 +78,24 @@ powerpc_cr_register::compute(int crfd, int32 v)
cr |= standalone_CR_GT_field::mask() << (28 - 4 * crfd);
else
cr |= standalone_CR_EQ_field::mask() << (28 - 4 * crfd);
#endif
}
inline void
powerpc_cr_register::set(uint32 v)
{
#ifdef PPC_HAVE_SPLIT_CR
crf[0].set(CR_field<0>::extract(v));
crf[1].set(CR_field<1>::extract(v));
crf[2].set(CR_field<2>::extract(v));
crf[3].set(CR_field<3>::extract(v));
crf[4].set(CR_field<4>::extract(v));
crf[5].set(CR_field<5>::extract(v));
crf[6].set(CR_field<6>::extract(v));
crf[7].set(CR_field<7>::extract(v));
#else
cr = v;
#endif
}
inline uint32
powerpc_cr_register::get() const
{
#ifdef PPC_HAVE_SPLIT_CR
uint32 cr = crf[0].get();
for (int i = 1; i < 8; i++)
cr = (cr << 4) | crf[i].get();
#endif
return cr;
}
inline bool
powerpc_cr_register::test(int condition) const
{
#ifdef PPC_HAVE_SPLIT_CR
return crf[condition / 4].test(condition % 4);
#else
return (cr << condition) & 0x80000000;
#endif
}
@@ -354,9 +162,8 @@ union powerpc_fpr {
};
/**
* VEA Register Set
* User Environment Architecture (UEA) Register Set
**/
struct powerpc_registers
@@ -368,7 +175,6 @@ struct powerpc_registers
FPSCR,
XER,
LR, CTR,
TBL, TBU,
PC,
SP = GPR_BASE + 1
};
@@ -384,7 +190,6 @@ struct powerpc_registers
uint32 lr; // Link Register (SPR 8)
uint32 ctr; // Count Register (SPR 9)
uint32 pc; // Program Counter
uint32 tbl, tbu; // Time Base
powerpc_spcflags spcflags; // Special CPU flags
static uint32 reserve_valid;
static uint32 reserve_addr;