gbeauche
3f535d30da
Add support for comma-separated elements in "jitblacklist" item.
2007-06-15 07:55:03 +00:00
gbeauche
f20c1ca30b
Remove dead code, B2 doesn't use valid_address()
2007-06-13 15:57:46 +00:00
gbeauche
3c100abdb2
Fix CMOV emulation on x86_64 in case the CPU doesn't support that instruction
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(which is very unlikely).
2007-01-14 13:23:36 +00:00
gbeauche
8d2f2a335b
The older code generator is now deprecated on x86-32 too.
2007-01-14 13:07:22 +00:00
gbeauche
1f2e561a6f
Use SAHF_SETO_PROFITABLE wherever possible on x86-64, it's faster. This can't
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be the default because some very ancient CPUs don't support LAHF in long mode
2007-01-14 12:23:29 +00:00
gbeauche
2e95c43bf2
Remove the 33-bit addressing hack as it's overly complex for not much gain.
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Rather, use an address override prefix (0x67) though Intel Core optimization
reference guide says to avoid LCP prefixes. In practise, impact on performance
is measurably marginal on e.g. Speedometer tests.
2007-01-13 18:21:30 +00:00
gbeauche
9e252b413e
Fix 64-bit builds in REAL_ADDRESSING mode with gcc4.1.
2007-01-13 17:21:08 +00:00
gbeauche
7af6665619
icc9.1 & gcc4.1 warning fixes
2006-07-23 10:20:23 +00:00
gbeauche
53f79caf8c
Add LEALQmr, EMMS, SSE CMP and a series of new SSE opcodes (auto-generated)
2006-07-17 04:07:41 +00:00
gbeauche
9e64c3af94
Add more SSE templates for new SheepShaver's code generator -- though it
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should be made independent of this file.
2006-07-14 16:53:48 +00:00
gbeauche
b4768fc62c
Run-time assembler fixes:
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- Check for RIP register only in 64-bit mode
- Add missing macros and arguments (BT*im)
- MOVSWQ/MOVZWQ are 64-bit mode instructions only
2006-07-14 09:09:12 +00:00
gbeauche
24af8d27c3
Fix for LAZY_FLUSH_ICACHE_RANGE. Blocks are indexed by native addresses.
2006-05-08 16:56:07 +00:00
gbeauche
4f07113555
Patch SynchIdleTime() to implement new "idlewait" prefs item.
2006-04-30 21:16:48 +00:00
gbeauche
0222915bc4
Fix long double support for x86 targets if -m128bit-long-double.
2006-04-09 13:40:27 +00:00
gbeauche
dbc467e316
prefer lower indexes in register allocation, this avoids REX prefixes on
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x86_64 when %r8 - %r15 are used (very light speedup expected)
2006-02-26 18:58:18 +00:00
gbeauche
91babf4bb5
fix FETOX & FTWOTOX translations for x86_64
2006-02-26 18:49:55 +00:00
gbeauche
294664b726
Fix SAHF_SETO_PROFITABLE code for x86-64 platforms.
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This was only an experiment. Improvement was marginal: only +3% on AMD64
(an Athlon 64 3200+). However, it may be interesting to test it on EM64T
(e.g. newer P4s) since an older P3/800, hence in 32-bit mode, got a +15%
improvement in Speedometer 4 benchmarks.
Rationale: lahf/seto sequences avoid load/stores to the stack (push/pop)
and it was thus hoped to be faster.
Anyhow, SAHF_SETO_PROFITABLE can only be enabled manually at this time.
Edit your generated Makefile for testing, but first make sure your CPU
supports lahf in 64-bit mode (lahf_lm flag in /proc/cpuinfo).
2006-02-06 23:06:54 +00:00
gbeauche
3b94dfb1a9
Cosmetics, fix %rh cases in !X86_FLAT_REGISTERS mode, lahf/sahf are now
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valid instructions in long mode (recent enough CPU revisions: lahf_lm).
2006-02-06 22:57:18 +00:00
gbeauche
9ccf62f7b0
Manually emit LAHF instructions so that 64-bit assemblers can grok it
2006-02-06 22:55:44 +00:00
gbeauche
e534b07a70
more precise callee-saved register set
2006-01-16 21:31:41 +00:00
gbeauche
12f103a83a
JIT generated code is not guaranteed to be leaf, e.g. there could be a call
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to a generic instruction handler (untranslated code). This caused problems
on MacOS X for Intel where the unaligned stack conditions turned out to be
more visible. Performance loss is really neglectable and this is the right
fix now anyway.
2006-01-16 21:31:08 +00:00
gbeauche
1b99c9501f
fix stack alignment (theoritically but it was OK in practise) in generated
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functions, move m68k_compile_execute() to compiler/ dir since it's JIT
generic and it now depends on USE_PUSH_POP (as it should)
2006-01-15 22:42:51 +00:00
gbeauche
ba5ef9cd31
Stop abort()'ing when we fail to recognize the underlying processor, assume
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an obsolete i386 instead. Keep report on stderr though.
2005-07-24 14:57:11 +00:00
gbeauche
ef5a50e2af
recognize more P4 cores
2005-07-24 14:48:27 +00:00
gbeauche
12eb8b670f
Avoid C99-isms in C code for old compilers (e.g. gcc "2.96" on MDK 8.1)
2005-06-22 08:51:04 +00:00
gbeauche
0f0b06b099
Much improved responsiveness on NetBSD systems.
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On those systems, it's really hard to get high resolution timings and the
system oftens fails to honour a timeout in less than 20 ms. The idea here
is to have an average m68k instruction count (countdown quantum) that
triggers real interrupt checks. The quantum is calibrated every 10 ticks
and has a 1000 Hz resolution on average.
2005-06-11 06:43:24 +00:00
gbeauche
c0cc43a87b
Really make translation through constant jumps functional. This can be
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disabled with the new prefs item "jitinline". Some rapid Speedometer 4
benchmarks showed only a 4% improvement.
2005-06-06 19:22:56 +00:00
gbeauche
83b228cf30
Add support for hardware locks on x86_64 too
2005-06-06 18:49:51 +00:00
gbeauche
6c65ae370e
Fix build with NO_INLINE_MEMORY_ACCESS set
2005-06-05 07:32:23 +00:00
gbeauche
08c4acd21f
Enable FLIGHT_RECORDER for generated code but don't record registers in
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that case (yet).
2005-06-04 16:47:14 +00:00
gbeauche
d91e8b2a8f
fix "banks" addressing mode for 64-bit platforms
2005-05-13 11:05:56 +00:00
gbeauche
380a9ed970
ensure allocated code fits under 32-bit boundaries
2005-04-24 23:02:48 +00:00
gbeauche
165b32da39
Fix build with gcc4 on x86-64: ignore errors when casting pointers to int
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from regs & fpu members + code cache. This is possible because data is
allocated in 32-bit space and we force allocation of translation cache to
those bounds too.
2005-04-24 23:00:08 +00:00
gbeauche
57169c7923
Recognize lahf_lm from Dual Core Opterons. This enables use of LAHF/SETO
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instructions in long mode (64-bit). However, there seems to be another bug
in the JIT preventing it from being fully supported. m68k.h & codegen_x86.h
are easily fixed bug another patch is still needed.
2005-04-21 09:08:57 +00:00
gbeauche
5c001ba645
Allocate executable space to detect cpu features (cpuid). aka don't crash
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on non-executable .data sections on x86-64 with NX support enabled.
2005-03-22 16:12:18 +00:00
gbeauche
608c1f65bd
close opened files and make sure to flush stdout on exit, this used to
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cause weird results on windows otherwise
2005-03-17 00:21:36 +00:00
gbeauche
30632aed4f
Happy New Year!
2005-01-30 21:42:16 +00:00
gbeauche
a6bf2d0928
add some code to gather stats on m68k registers used in translated blocks
2004-11-20 23:35:16 +00:00
gbeauche
6774a0821d
fix tester for BSF flags handling
2004-11-11 07:07:55 +00:00
gbeauche
20f5f531ca
fix inline dispatcher to really generate a cmove on x86-64 (silly bug!)
2004-11-08 23:24:54 +00:00
gbeauche
0c255e1fbd
Merge BSF simulation on P4 from Amithlon. Use 33-bit memory addressing model.
2004-11-08 21:10:46 +00:00
gbeauche
0ba075050c
Enable RIP-relative addressing, optimize REX conditions processing in
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! X86_FLAT_REGISTERS mode, fix __REX_mem encodings (e.g. POPLm)
2004-11-08 20:48:19 +00:00
gbeauche
c21650b7a8
fix protection changes on translation cache + cosmetic fixlet
2004-11-02 23:52:00 +00:00
gbeauche
3fcceb052c
fix JIT FPU for x86_64
2004-11-02 23:28:19 +00:00
gbeauche
129f80faf6
preserve r11 as the register used to resolve pointers to functions
2004-11-01 18:40:30 +00:00
gbeauche
b3bd00f159
- affine need_to_preserve[] to get close to linux/x86_64 ABI
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- optimize NOP fillers on x86-64 (based on GNU as implementation)
2004-11-01 17:12:55 +00:00
gbeauche
e58fbc745b
revive and fix almost two-year old port to x86_64
2004-11-01 16:01:51 +00:00
gbeauche
730364ac1e
- optimize absolute addresses into RIP relative, if possible
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- fix MOVQir as the operand is 64-bit
- fix IMULWrr, IMULLrr, IMULQrr, MOVSBWrr, MOVZBWrr
2004-11-01 15:37:40 +00:00
gbeauche
c12d2fa0ea
add dumb but handy brute-force runtime assembler verifier, someone will
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probably want to rewrite it to use BFD/opcodes internals for checks
2004-11-01 15:30:46 +00:00
gbeauche
33be2e8ace
Reorder SPL, BPL, SIL, DIL IDs so that 8-bit register allocation is simpler
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Fix MOVZBL and MOVSBL encodings with those extended 8-bit registers
2004-10-31 16:02:04 +00:00
