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b150b42fc6
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54 Commits

Author SHA1 Message Date
Alexei Svitkine
b150b42fc6 Fix some string conversion warnings. 2017-12-10 11:27:08 -05:00
Alexei Svitkine
181634ab31 Fix more Xcode8 warnings and tweak project settings. 2016-12-17 23:31:03 -05:00
Alexei Svitkine
d19e757e1c Fix some more Xcode8 warnings & analyze warnings. 2016-12-17 22:24:00 -05:00
Alexei Svitkine
70f9c4dab9 Remove unused labels. 2012-06-21 21:48:32 -04:00
asvitkine
d6db773362 [patch from Darik Horn <dajhorn@vanadac.com> ] 
Makes SheepShaver compatible with Ubuntu Intrepid and
other distros that bundle the gcc-4.3 compiler.

The patch changes two things:

1. Renames the block_cache where its name collides with its class
definition.

2. Fixes the "explicit template specialization cannot have a storage
class" error in the ppc-dyngen-ops.cpp file.
 2009-01-15 23:25:08 +00:00
asvitkine
5505a5dc62 Change < to - in qsort compare functions to correctly return 0 for equality. 2008-09-14 19:54:36 +00:00
gbeauche
efa32be9ec Optimize invalidate_cache_range() for short ranges. 2007-07-21 10:25:51 +00:00
gbeauche
b20a76f580 merge PPC_PROFILE_REGS_USE fixes from KPX branch 2007-02-17 09:01:31 +00:00
gbeauche
9999881c78 Enable JIT in non-constructor so that a user-defined value can be set later 2007-01-21 13:44:27 +00:00
gbeauche
3b6a579f33 Optimize lwarx/stwcx for uniprocessors and generate code for them. There is 
no performance increase even though those two instructions represented approx
18M of untranslated instructions on a simple boot to MacOS.
 2007-01-18 07:02:35 +00:00
gbeauche
5b0b60da76 Remove specialised decoders. This will be done differently, if necessary. 2007-01-17 06:20:36 +00:00
gbeauche
022d09375f Merge from KPX: new exit() handling code; make "syscall" illegal for MacOS 
emulation (SheepShaver)
 2006-01-28 21:57:52 +00:00
gbeauche
dd2b9a95d5 Align PowerPC registers struct manually, i.e. don't depend on non-portable 
compiler extensions (e.g. GCC __attribute__((aligned(N)))).
 2005-12-06 22:25:13 +00:00
gbeauche
ec8661f431 Fix a damn silly bug. On some occasions, we could have spcflags() set to 
EXEC_RETURN | HANDLE_INTERRUPT. And then, we handled the interrupt, but
EXEC_RETURN was set so we returned very quickly without completing the
interrupt routine. As a side effect, this occasionnaly hung the emulator
most likely with {ethernet,audio}-based applications that trigger a lot
of interrupts.

The fix is to always honour EXEC_RETURN flag at first, of course.
 2005-06-30 15:29:11 +00:00
gbeauche
c9b044aeaf Completely avoid any form of nested interrupt processing. 2005-06-30 09:09:59 +00:00
gbeauche
2deca51ca4 Add code to gather some stats on register usage. 2005-06-23 11:37:01 +00:00
gbeauche
9019e71cfc Preserve all necessary registers on interrupt, thus also permitting nested 
interrupts to occur. SheepShaver locks should now be reduced.
 2005-03-05 15:25:10 +00:00
gbeauche
df0d5d2a41 Happy New Year 2005! 2005-01-30 21:48:22 +00:00
gbeauche
e1bbf0714b PPC_REENTRANT_JIT is only valid with JIT enabled 2004-11-22 22:09:05 +00:00
gbeauche
18a039b610 Notify upper execution levels that we invalidated the translation cache, 
even partially. i.e. Always get out of compiled code on any cache invalidate
 2004-07-11 06:44:52 +00:00
gbeauche
ddd6402a16 fix jump crossing init of start_time 2004-07-02 15:38:54 +00:00
gbeauche
72b26d7ff7 Stop forced compilation when entering a new JIT execution level. 2004-06-15 21:27:46 +00:00
gbeauche
f376933138 Attempt to fix direct block chaining code in corner cases. e.g. really 
chain only blocks within page boundaries (compare against block entry point)
 2004-05-22 17:57:36 +00:00
gbeauche
c3f2342f47 Make NativeOp() handler a sheepshaver_cpu handler, thus getting rid of ugly 
GPR macro definition.

Make the JIT engine somewhat reentrant. This brings a massive performance
boost for applications that cause many Execute68k(). e.g. audio in PlayerPRO.
 2004-05-19 21:23:17 +00:00
gbeauche
81ae2fee40 Direct block chaining on x86 and amd64 too. Optimize do_execute_branch_bo<> 
No need to update Program Counter if we have direct linked blocks.

TODO: remove obsolete PC-related generators
 2004-05-12 10:44:04 +00:00
gbeauche
08bcd2653d direct block chaining, aka faster block dispatcher 2004-05-11 20:53:25 +00:00
gbeauche
d10a3586f1 Year got increased "recently". ;-) 2004-02-16 10:57:07 +00:00
gbeauche
313cddeeb2 AltiVec emulation! ;-) 2004-02-15 17:17:37 +00:00
gbeauche
8afa65cc96 Inline fast basic block lookups. Only check top tag as it is a hit more than 
95% of the time. Overall, this improves performance by more than 2x on a P4.
 2004-01-27 13:54:51 +00:00
gbeauche
561046449a Fix no JIT & no decode cache case to default to interpretive mode only. 2003-12-25 23:33:15 +00:00
gbeauche
5dca41d253 Add gen_invoke_CPU_im_im() to invoke do_record_step(pc, opcode). 2003-12-04 17:53:04 +00:00
gbeauche
0c2735dbcc fix stats reports 2003-12-03 10:59:43 +00:00
gbeauche
7ebe0347bf Add "jit" prefs item. Fix PPC_DECODE_CACHE version to fill in new min_pc & 
max_pc members of block info. Increase -finline-limit to 10000 for older gcc
 2003-12-03 10:52:50 +00:00
gbeauche
dd956c78db gather some stats on untranslated instructions 2003-12-01 13:07:26 +00:00
gbeauche
4a3cd024ed better handling of static translation cache allocation, handle nested 
execution paths from the cpu core, cleanups for KPX_MAX_CPUS == 1.
 2003-11-30 17:21:53 +00:00
gbeauche
2eba241021 self credit cpu emulator ;-) 2003-11-25 10:27:59 +00:00
gbeauche
73d51962f6 Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC. 
The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.

Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.
 2003-11-24 23:45:52 +00:00
gbeauche
e9f3546539 Remove even more obsolete code. Drop TBL/TBU registers, they are manually 
handled through the mftb instruction accessor.
 2003-11-11 11:44:34 +00:00
gbeauche
cf0ed72f24 Remove obsolete code related to PPC_NO_FPSCR_UPDATE, PPC_LAZY_PC_UPDATE, 
PPC_LAZY_CC_UPDATE, PPC_HAVE_SPLIT_CR defines.
 2003-11-11 11:32:27 +00:00
gbeauche
42e1cabc94 Move variables for compile statistics to powerpc_cpu private data 2003-11-04 20:45:46 +00:00
gbeauche
30bd089279 PowerPC floating-point registers are now an union of uint64 & double. This 
eases FP load/stores.
 2003-11-04 15:03:15 +00:00
gbeauche
a42281aad1 Implement partial block cache invalidation. Rewrite core cached blocks 
execution loop with a Duff's device. Gather some predecode time statistics.
This shows that only around 2% of total emulation time is spent for
predecoding the instructions.
 2003-11-03 21:28:32 +00:00
gbeauche
f0ea192460 Optimized pointers to non virtual member functions. This reduces space 
and overhead since runtime checks are eliminated. Actually, it yields
up to 10% performance improvement with specialized decoders.
 2003-11-02 14:48:20 +00:00
gbeauche
d956d3c4ca add specialized instruction decoders (disabled for now) 2003-11-01 17:07:17 +00:00
gbeauche
89d0f9ca29 Integrate spcflags handling code to kpx_cpu core. We can also remove 
oldish EXEC_RETURN handling with a throw/catch mechanism since we
do have a dependency on extra conditions (invalidated cache) that
prevents fast execution loops.
 2003-11-01 15:15:31 +00:00
gbeauche
60d34a6816 Rewrite interrupts handling code so that the emulator can work with a 
predecode cache. This implies to run in interpreted mode only while
processing EmulOps or other native (nested) runs.

Note that the FLIGHT_RECORDER with a predecode cache gets slower than
without caching at all.
 2003-10-26 13:59:04 +00:00
gbeauche
cb13fe3007 Log both r24 (m68k emulator PC) & stack pointer in SheepShaver mode only 2003-10-19 21:36:21 +00:00
gbeauche
9a05805a27 - Fix ADDME & ADDZE decoders, add RA==R0 testers 
- Increase predecode cache size to 32K entries
- Enable PPC_EXECUTE_DUMP_STATE for predecode cache as well
 2003-10-18 13:43:25 +00:00
gbeauche
1b9876889e - Record address range of block to invalidate. i.e. icbi records ranges 
and isync actually invalidate caches
 2003-10-12 06:44:04 +00:00
gbeauche
7e20a8d205 - Add support for FLIGHT_RECORDER with predecode cache 
- Always enable predecode cache & flight recorder for now
 2003-10-11 09:57:52 +00:00