moa/todo.txt

* should SharedData be HostData, or something else?  I don't think the name is very informative
* can you make the connections between things (like memory adapters), be expressed in a way that's more similar to the electrical design?
  like specifying that address pins 10-7 should be ignored/unconnected, pin 11 will connect to "chip select", etc

* movem still isn't working (for genesis)
* fix movem tests

* modify the frame swapper and frontend to avoid the extra buffer copy
* I had to remove the mask colour from blit because it doesn't work with the mac... need a new solution

* add more m68k tests and try to test against a working impl
* maybe see about a Mac 128k or something

* should you rename devices.rs traits.rs?



* how can you do devices that change their address map during operation, like mac which puts rom at 0 and ram at 600000 temporarily 
* i need a better way of handling disperate reads/writes to I/O spaces, rather than having multiple devices or having a massive chunk of address space allocated, continuously
* should you modify Addressable to also take the absolute address as input?  I'm thinking of how the same device could be mapped to multiple addresses in memory instead
  of taking up a whole range of addresses
* could have a remapper device, which takes a big swath of addresses in and maps them to another set of addresses (for Mac VIA generic to bus-hookup-in-mac adapter)
* could you use a generic sharable signal thing for sharing data, such as the VIA in mac128 where a single output bit determines the video mode (which would be a separate device)
  So both could share the same Signal, one setting it and the other reading it, but how would you actually configure/build that?


* you could modify read()/write() in Addressable to return the number of bytes read or written for dynamic bus sizing used by the MC68020+
* should you simulate bus arbitration?


Genesis/Mega Drive:
    * fix ym7101 to better handle V/H interrupts (right now it sets and then the next step will clear, but it'd be nice if it could 'edge trigger')
    * YM7101 timing is causing it to be very slow... speeding this up increasing rendering speed a lot, even though the frame shouldn't be drawn that often... not sure what's wrong with the timing
    * make the ym7101 set/reset the v_int occurred flag based on the interrupt controller


68000:
    * add instruction timing to M68k
    * make tests for each instruction
    * check all instructions in the docs

    * unimplemented: ABCD, ADDX, BFFFO, BFINS, BKPT, CHK, ILLEGAL, MOVEfromCCR,, RTR, RTD, SBCD, SUBX
    * >=MC68020 undecoded & unimplemented: CALLM, CAS, CAS2, CHK2, CMP2, RTM, PACK, TRAPcc, UNPK

    * add support for MMU
    * add support for FPU
    * Coprocessor instructions: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc

Z80:
    * add instruction timings to Z80



* how can you have multiple CPUs
* can you eventually make the system connections all configurable via a config file?