Added log crate

This commit is contained in:
transistor 2022-10-09 09:40:20 -07:00
parent 43f655cdb4
commit 925a4e0750
20 changed files with 120 additions and 90 deletions

58
Cargo.lock generated
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@ -238,6 +238,17 @@ dependencies = [
"cc",
]
[[package]]
name = "colored"
version = "2.0.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b3616f750b84d8f0de8a58bda93e08e2a81ad3f523089b05f1dffecab48c6cbd"
dependencies = [
"atty",
"lazy_static",
"winapi",
]
[[package]]
name = "combine"
version = "4.6.6"
@ -588,6 +599,7 @@ dependencies = [
name = "moa_console"
version = "0.1.0"
dependencies = [
"log",
"moa_common",
"moa_computie",
"moa_core",
@ -595,11 +607,15 @@ dependencies = [
"moa_m68k",
"moa_peripherals_generic",
"moa_peripherals_motorola",
"simple_logger",
]
[[package]]
name = "moa_core"
version = "0.1.0"
dependencies = [
"log",
]
[[package]]
name = "moa_genesis"
@ -633,6 +649,7 @@ name = "moa_minifb"
version = "0.1.0"
dependencies = [
"clap 3.2.22",
"log",
"minifb",
"moa_common",
"moa_computie",
@ -641,6 +658,7 @@ dependencies = [
"moa_macintosh",
"moa_peripherals_yamaha",
"moa_trs80",
"simple_logger",
]
[[package]]
@ -844,6 +862,15 @@ dependencies = [
"syn",
]
[[package]]
name = "num_threads"
version = "0.1.6"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2819ce041d2ee131036f4fc9d6ae7ae125a3a40e97ba64d04fe799ad9dabbb44"
dependencies = [
"libc",
]
[[package]]
name = "oboe"
version = "0.4.6"
@ -1143,6 +1170,19 @@ version = "1.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "43b2853a4d09f215c24cc5489c992ce46052d359b5109343cbafbf26bc62f8a3"
[[package]]
name = "simple_logger"
version = "2.3.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "48047e77b528151aaf841a10a9025f9459da80ba820e425ff7eb005708a76dc7"
dependencies = [
"atty",
"colored",
"log",
"time",
"winapi",
]
[[package]]
name = "smallvec"
version = "1.9.0"
@ -1236,6 +1276,24 @@ dependencies = [
"syn",
]
[[package]]
name = "time"
version = "0.3.15"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "d634a985c4d4238ec39cacaed2e7ae552fbd3c476b552c1deac3021b7d7eaf0c"
dependencies = [
"itoa",
"libc",
"num_threads",
"time-macros",
]
[[package]]
name = "time-macros"
version = "0.2.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "42657b1a6f4d817cda8e7a0ace261fe0cc946cf3a80314390b22cc61ae080792"
[[package]]
name = "toml"
version = "0.5.9"

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@ -4,4 +4,5 @@ version = "0.1.0"
edition = "2021"
[dependencies]
log = "0.4"

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@ -48,55 +48,3 @@ impl Error {
}
}
#[derive(Copy, Clone, Debug, PartialEq, PartialOrd)]
pub enum LogLevel {
Error,
Warning,
Info,
Debug,
}
static mut LOG_LEVEL: LogLevel = LogLevel::Warning;
pub fn log_level() -> LogLevel {
unsafe { LOG_LEVEL }
}
#[macro_export]
macro_rules! printlog {
($level:expr, $($arg:tt)*) => ({
if $level <= $crate::log_level() {
println!($($arg)*);
}
})
}
#[macro_export]
macro_rules! error {
($($arg:tt)*) => ({
$crate::printlog!($crate::LogLevel::Error, $($arg)*);
})
}
#[macro_export]
macro_rules! warning {
($($arg:tt)*) => ({
$crate::printlog!($crate::LogLevel::Warning, $($arg)*);
})
}
#[macro_export]
macro_rules! info {
($($arg:tt)*) => ({
$crate::printlog!($crate::LogLevel::Info, $($arg)*);
})
}
#[macro_export]
macro_rules! debug {
($($arg:tt)*) => ({
$crate::printlog!($crate::LogLevel::Debug, $($arg)*);
})
}

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@ -13,10 +13,12 @@ pub mod host;
pub mod parser;
pub mod timers;
pub use log::{trace, debug, info, warn, error};
pub use crate::debugger::Debugger;
pub use crate::devices::{Clock, ClockElapsed, Address, Addressable, Steppable, Interruptable, Debuggable, Inspectable, Transmutable, TransmutableBox};
pub use crate::devices::{read_beu16, read_beu32, read_leu16, read_leu32, write_beu16, write_beu32, write_leu16, write_leu32, wrap_transmutable};
pub use crate::error::{Error, ErrorType, LogLevel, log_level};
pub use crate::error::{Error, ErrorType};
pub use crate::interrupts::InterruptController;
pub use crate::memory::{MemoryBlock, AddressRightShifter, AddressRepeater, Bus, BusPort, dump_slice};
pub use crate::signals::{Observable, Signal, EdgeSignal, ObservableSignal, ObservableEdgeSignal};

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@ -3,6 +3,7 @@ use std::fs;
use std::rc::Rc;
use std::cell::RefCell;
use crate::info;
use crate::error::Error;
use crate::devices::{Address, Addressable, Transmutable, TransmutableBox, read_beu16};

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@ -3,7 +3,7 @@ use std::sync::{Arc, Mutex};
use std::collections::VecDeque;
use cpal::{Stream, SampleRate, SampleFormat, StreamConfig, traits::{DeviceTrait, HostTrait, StreamTrait}};
use moa_core::{Clock, warning, error};
use moa_core::{Clock, warn, error};
use moa_core::host::{Audio, ClockedQueue};
const SAMPLE_RATE: usize = 48000;
@ -236,11 +236,11 @@ impl AudioOutput {
pub fn add_frame(&mut self, frame: AudioFrame) {
self.output.push_back(frame);
self.sequence_num = self.sequence_num.wrapping_add(1);
println!("added frame {}", self.sequence_num);
//println!("added frame {}", self.sequence_num);
}
pub fn pop_next(&mut self) -> Option<AudioFrame> {
println!("frame {} sent", self.sequence_num);
//println!("frame {} sent", self.sequence_num);
self.output.pop_front()
}
@ -284,12 +284,12 @@ impl CpalAudioOutput {
if let Some(frame) = result {
let (start, middle, end) = unsafe { frame.data.align_to::<f32>() };
if start.len() != 0 || end.len() != 0 {
warning!("audio: frame wasn't aligned");
warn!("audio: frame wasn't aligned");
}
let length = middle.len().min(data.len());
data[..length].copy_from_slice(&middle[..length]);
} else {
warning!("missed an audio frame");
warn!("missed an audio frame");
}
};

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@ -1,10 +1,13 @@
[package]
name = "moa_console"
version = "0.1.0"
edition = "2018"
edition = "2021"
default-run = "moa-computie"
[dependencies]
log = "0.4"
simple_logger = "2.3.0"
moa_core = { path = "../../core" }
moa_common = { path = "../common", features = ["tty"] }

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@ -3,6 +3,11 @@ use moa_console::ConsoleFrontend;
use moa_computie::build_computie;
fn main() {
simple_logger::SimpleLogger::new()
.with_level(log::Level::Debug.to_level_filter())
.without_timestamps()
.init().unwrap();
let mut frontend = ConsoleFrontend;
let mut system = build_computie(&mut frontend).unwrap();

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@ -5,10 +5,13 @@ edition = "2021"
default-run = "moa-genesis"
[dependencies]
moa_core = { path = "../../core" }
moa_common = { path = "../common", features = ["audio"] }
log = "0.4"
minifb = "0.19"
clap = "3.2.20"
simple_logger = "2.3.0"
moa_core = { path = "../../core" }
moa_common = { path = "../common", features = ["audio"] }
moa_genesis = { path = "../../systems/genesis" }
moa_computie = { path = "../../systems/computie" }

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@ -205,6 +205,11 @@ impl MiniFrontend {
}
pub fn start(&mut self, matches: ArgMatches, mut system: Option<System>) {
simple_logger::SimpleLogger::new()
.with_level(log::Level::Warn.to_level_filter())
.without_timestamps()
.init().unwrap();
if matches.occurrences_of("debugger") > 0 {
system.as_mut().map(|system| system.enable_debugging());
}

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@ -1,5 +1,5 @@
use moa_core::{Error, System, ClockElapsed, Address, Addressable, Steppable, Transmutable, Signal, ObservableSignal, Observable, debug, warning};
use moa_core::{Error, System, ClockElapsed, Address, Addressable, Steppable, Transmutable, Signal, ObservableSignal, Observable, debug, warn};
const REG_OUTPUT_B: Address = 0x00;
@ -66,7 +66,7 @@ impl Addressable for Mos6522 {
REG_INT_FLAGS => { data[0] = self.interrupt_flags; },
REG_INT_ENABLE => { data[0] = self.interrupt_enable | 0x80; },
_ => {
warning!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
warn!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
},
}
debug!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
@ -91,7 +91,7 @@ impl Addressable for Mos6522 {
},
REG_OUTPUT_A_NHS => { self.port_a.borrow_mut().data = data[0]; self.port_a.notify(); },
_ => {
warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
},
}
Ok(())

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@ -1,5 +1,5 @@
use moa_core::{info, warning, debug};
use moa_core::{info, warn, debug};
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable};
use moa_core::host::{Host, Audio};
use moa_core::host::audio::{SquareWave};
@ -143,13 +143,13 @@ impl Addressable for Sn76489 {
}
fn read(&mut self, _addr: Address, _data: &mut [u8]) -> Result<(), Error> {
warning!("{}: !!! device can't be read", DEV_NAME);
warn!("{}: !!! device can't be read", DEV_NAME);
Ok(())
}
fn write(&mut self, addr: Address, data: &[u8]) -> Result<(), Error> {
if addr != 0 {
warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
return Ok(());
}

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@ -2,7 +2,7 @@
use std::num::NonZeroU8;
use std::collections::VecDeque;
use moa_core::{debug, warning};
use moa_core::{debug, warn};
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable};
use moa_core::host::{Host, Audio};
use moa_core::host::audio::{SineWave};
@ -198,6 +198,7 @@ impl Ym2612 {
}
pub fn set_register(&mut self, bank: usize, reg: usize, data: u8) {
warn!("{}: set reg {}{:x} to {:x}", DEV_NAME, bank, reg, data);
match reg {
0x24 => {
self.timer_a = (self.timer_a & 0x3) | ((data as u16) << 2);
@ -271,7 +272,7 @@ impl Ym2612 {
},
_ => {
warning!("{}: !!! unhandled write to register {:0x} with {:0x}", DEV_NAME, reg, data);
warn!("{}: !!! unhandled write to register {:0x} with {:0x}", DEV_NAME, reg, data);
},
}
}
@ -352,7 +353,7 @@ impl Addressable for Ym2612 {
data[0] = 0 | ((self.timer_a_overflow as u8) << 1) | (self.timer_b_overflow as u8);
}
_ => {
warning!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
warn!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
},
}
debug!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
@ -379,7 +380,7 @@ impl Addressable for Ym2612 {
}
},
_ => {
warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
},
}
Ok(())

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@ -1,5 +1,5 @@
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable, warning, debug};
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable, warn, debug};
const DEV_NAME: &'static str = "z8530";
@ -23,7 +23,7 @@ impl Addressable for Z8530 {
fn read(&mut self, addr: Address, data: &mut [u8]) -> Result<(), Error> {
match addr {
_ => {
warning!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
warn!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
},
}
debug!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
@ -34,7 +34,7 @@ impl Addressable for Z8530 {
debug!("{}: write to register {:x} with {:x}", DEV_NAME, addr, data[0]);
match addr {
_ => {
warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
},
}
Ok(())

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@ -1,5 +1,5 @@
use moa_core::{warning, info};
use moa_core::{warn, info};
use moa_core::{System, Error, Clock, ClockElapsed, Address, Addressable, Steppable, Transmutable};
use moa_core::host::{Host, ControllerUpdater, HostData, ControllerDevice, ControllerEvent};
@ -169,7 +169,7 @@ impl Addressable for GenesisControllers {
REG_S_CTRL1 => { data[i] = self.port_1.s_ctrl | 0x02; },
REG_S_CTRL2 => { data[i] = self.port_2.s_ctrl | 0x02; },
REG_S_CTRL3 => { data[i] = self.expansion.s_ctrl | 0x02; },
_ => { warning!("{}: !!! unhandled reading from {:0x}", DEV_NAME, addr); },
_ => { warn!("{}: !!! unhandled reading from {:0x}", DEV_NAME, addr); },
}
info!("{}: read from register {:x} the value {:x}", DEV_NAME, addr, data[0]);
Ok(())
@ -189,7 +189,7 @@ impl Addressable for GenesisControllers {
REG_S_CTRL1 => { self.port_1.s_ctrl = data[0] & 0xF8; },
REG_S_CTRL2 => { self.port_2.s_ctrl = data[0] & 0xF8; },
REG_S_CTRL3 => { self.expansion.s_ctrl = data[0] & 0xF8; },
_ => { warning!("{}: !!! unhandled write of {:0x} to {:0x}", DEV_NAME, data[0], addr); },
_ => { warn!("{}: !!! unhandled write of {:0x} to {:0x}", DEV_NAME, data[0], addr); },
}
Ok(())
}

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@ -2,7 +2,7 @@
use std::rc::Rc;
use std::cell::RefCell;
use moa_core::{warning, info};
use moa_core::{warn, info};
use moa_core::{Bus, Signal, Error, Address, Addressable, Transmutable};
@ -33,7 +33,7 @@ impl Addressable for CoprocessorCoordinator {
0x100 => {
data[0] = if self.bus_request.get() && self.reset.get() { 0x01 } else { 0x00 };
},
_ => { warning!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr); },
_ => { warn!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr); },
}
info!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
Ok(())
@ -49,7 +49,7 @@ impl Addressable for CoprocessorCoordinator {
0x200 => {
self.reset.set(data[0] == 0);
},
_ => { warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr); },
_ => { warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr); },
}
Ok(())
}

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@ -1,5 +1,5 @@
use moa_core::{debug, warning, error};
use moa_core::{debug, warn, error};
use moa_core::{System, Error, EdgeSignal, Clock, ClockElapsed, Address, Addressable, Steppable, Inspectable, Transmutable, TransmutableBox, read_beu16, dump_slice};
use moa_core::host::{Host, BlitableSurface, HostData};
use moa_core::host::gfx::{Frame, FrameQueue};
@ -257,7 +257,7 @@ impl Ym7101Memory {
self.transfer_remain -= 1;
}
},
_ => { warning!("{}: !!! error unexpected transfer mode {:x}", DEV_NAME, self.transfer_type); },
_ => { warn!("{}: !!! error unexpected transfer mode {:x}", DEV_NAME, self.transfer_type); },
}
self.set_dma_mode(DmaType::None);
@ -831,7 +831,7 @@ impl Addressable for Ym7101 {
self.sn_sound.borrow_mut().as_addressable().unwrap().write(0, data)?;
},
_ => { warning!("{}: !!! unhandled write to {:x} with {:?}", DEV_NAME, addr, data); },
_ => { warn!("{}: !!! unhandled write to {:x} with {:?}", DEV_NAME, addr, data); },
}
Ok(())
}

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@ -1,5 +1,5 @@
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable, info, warning};
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable, info, warn};
//const CA0: u8 = 0x01;
@ -71,7 +71,7 @@ impl Addressable for IWM {
panic!("");
},
_ => {
warning!("{}: !!! unhandled read of {:0x} with state {:x}", DEV_NAME, addr, self.state);
warn!("{}: !!! unhandled read of {:0x} with state {:x}", DEV_NAME, addr, self.state);
},
}
info!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
@ -93,7 +93,7 @@ impl Addressable for IWM {
self.mode = data[i] & 0x1f;
},
_ => {
warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
},
}
Ok(())

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@ -1,7 +1,7 @@
use std::sync::{Arc, Mutex};
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable, debug, warning};
use moa_core::{System, Error, ClockElapsed, Address, Addressable, Steppable, Transmutable, debug, warn};
use moa_core::host::gfx::{Frame, FrameQueue};
use moa_core::host::{Host, BlitableSurface, KeyboardUpdater, KeyEvent};
@ -80,7 +80,7 @@ impl Addressable for Model1Peripherals {
} else if addr >= 0x420 && addr <= 0x820 {
data[0] = self.video_mem[addr as usize - 0x420];
} else {
warning!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
warn!("{}: !!! unhandled read from {:0x}", DEV_NAME, addr);
}
debug!("{}: read from register {:x} of {:?}", DEV_NAME, addr, data);
Ok(())
@ -91,7 +91,7 @@ impl Addressable for Model1Peripherals {
if addr >= 0x420 && addr < 0x820 {
self.video_mem[addr as usize - 0x420] = data[0];
} else {
warning!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
warn!("{}: !!! unhandled write {:0x} to {:0x}", DEV_NAME, data[0], addr);
}
Ok(())
}

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@ -1,4 +1,8 @@
* add log crate to core
* need to re-add a mechanism for audio frame dialation, either based on speed, or somehow automatic
* fix ym2612 sound generation
* fix glitching (possibly due to borrowing) in the audio mixer
* can you get audio working without the need to lock during an update? Use the ClockedQueue like frames do... but should the queue be used for the mixer-to-output,
@ -13,7 +17,6 @@
* make the keys easier to config...
* add log crate to core
* can you make the debugger more accessible, so a web interface could access the data and display it, in light of the fact that println isn't available in wasm
Web Assembly: