Zane Kaminski
2bc381ebc5
Removed state counter reset
2019-12-21 01:46:05 -05:00
Zane Kaminski
f471e04244
New PLD revision
...
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00
Zane Kaminski
ebaef9824f
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2019-10-13 01:42:28 -04:00
Zane Kaminski
4ef5acf2d3
Register reset/initial values set syntax changed
2019-10-13 01:40:25 -04:00
Zane Kaminski
7f581f6ba0
24-bit counter, CAS fixed
2019-10-11 20:34:51 -04:00
Zane Kaminski
66fc09b402
Made AddrH high bit variable with mode input
2019-09-07 21:16:23 -04:00
Zane Kaminski
f52c6e4781
Pipelined addition
2019-09-04 21:45:56 -04:00
Zane Kaminski
a87ee9c819
Trying again with RamFactor firmware
2019-09-02 20:56:37 -04:00
Zane Kaminski
215f5ca2c6
Clarifications and bugfixes, will try again
2019-09-02 01:42:07 -04:00
Zane Kaminski
6b2378f99a
1MB CPLD design seems to work, fails Apple BIST
2019-09-01 21:18:44 -04:00
Zane Kaminski
396cc3c03c
CPLD firmware compiles
2019-08-31 22:55:04 -04:00