4 Commits

Author	SHA1	Message	Date
Zane Kaminski	f471e04244	New PLD revision ... For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.	2019-10-18 15:07:38 -04:00
Zane Kaminski	3b0ca6584a	New schematic revision	2019-10-13 01:40:49 -04:00
Zane Kaminski	dac5bdb451	Submitted to JLCPCB	2019-07-30 17:11:31 -04:00
Zane Kaminski	62ff891412	Release candidate PCB	2019-07-21 17:53:22 -04:00