idk

This reverts commit 691c076b4d.

.gitignore

@@ -14,6 +14,7 @@ _autosave-*
 *-save.pro
 *-save.kicad_pcb
 fp-info-cache
+GR8RAM-backups/*
 
 # Netlist files (exported from Eeschema)
 *.net
@@ -23,3 +24,7 @@ fp-info-cache
 *.ses
 
 *.DS_Store
+cpld/db/GR8RAM.db_info
+cpld/db/GR8RAM.tmw_info
+cpld/GR8RAM.qws
+Documentation/~$4205AManual.docx

Documentation/Initialization Sequence

@@ -1,139 +1,13 @@
 Init sequence
 
-Init State			SDRAM				Flash					IS		Other
+LS				SDRAM					Flash					IS
---------------------------------------------------------------------------------
+-------------------------------------------------------------------
-$00000-$0FFBF		Nothing				Nothing					0
+$0000-$1FCE		Nothing					Nothing					0
-$00000				NOP	CKE				/CS hi, CLK lo
+$1FCF			Init: Precharge			Nothing					1
-...
+$1FD0-$1FFA		Init: AREF Pause		SPI Select				4
-$0FF90				NOP	CKE				/CS hi, CLK lo					InitActv <= ~BODf
+$1FFB			Init: AREF Pause		Dual Read (0x3B)		5
-....
+$1FFC			Init: AREF Pause		A[23:16] (0)			5
-$0FFA0				NOP	CKE				/CS lo, CLK lo
+$1FFD			Init: AREF Pause		A[15:08] (FW in 14:13)	5
-...
+$1FFE			Init: AREF Pause		A[07:00] (0)			5
-$0FFAF				NOP	CKE				/CS lo, CLK lo
+$1FFF			Init: AREF Pause		Dummy					5
-
+$2000-$3FFF		Init: Write ROM			Shift MISO into WRD		6
-$0FFB0-$0FFBF		Init: Precharge		Send read cmd ($03)		1
-$0FFB0				NOP	CKE				CLK lo, MOSI 0 (b7)
-$0FFB1				NOP CKE				CLK hi
-$0FFB2				NOP	CKE				CLK lo, MOSI 0 (b6)
-$0FFB3				PC all				CLK hi
-$0FFB4				NOP	CKE				CLK lo, MOSI 0 (b5)
-$0FFB5				NOP	CKE				CLK hi
-$0FFB6				NOP	CKE				CLK lo, MOSI 0 (b4)
-$0FFB7				NOP	CKE				CLK hi
-$0FFB8				NOP	CKE				CLK lo, MOSI 0 (b3)
-$0FFB9				NOP	CKE				CLK hi
-$0FFBA				NOP	CKE				CLK lo, MOSI 0 (b2)
-$0FFBB				Load mode			CLK hi
-$0FFBC				NOP	CKE				CLK lo, MOSI 1 (b1)
-$0FFBD				NOP	CKE				CLK hi
-$0FFBE				NOP	CKE				CLK lo, MOSI 1 (b0)
-$0FFBF				NOP CKE				CLK hi
-
-$0FFC0-$0FFEF		Init: mode & ref	Send address ($000000)	2
-$0FFC0				NOP	CKE				CLK lo, MOSI 0 (b23)
-$0FFC1				NOP CKE				CLK hi
-$0FFC2				NOP	CKE				CLK lo, MOSI 0 (b22)
-$0FFC3				AREF				CLK hi
-$0FFC4				NOP	CKE				CLK lo, MOSI Firmware[1] (b21)
-$0FFC5				NOP	CKE				CLK hi
-$0FFC6				NOP	CKE				CLK lo, MOSI Firmware[0] (b20)
-$0FFC7				NOP	CKE				CLK hi
-$0FFC8				NOP	CKE				CLK lo, MOSI 0 (b19)
-$0FFC9				NOP	CKE				CLK hi
-$0FFCA				NOP	CKE				CLK lo, MOSI 0 (b18)
-$0FFCB				AREF				CLK hi
-$0FFCC				NOP CKE				CLK lo, MOSI 0 (b17)
-$0FFCD				NOP CKE				CLK hi
-$0FFCE				NOP	CKE				CLK lo, MOSI 0 (b16)
-$0FFCF				NOP CKE				CLK hi
-$0FFD0				NOP	CKE				CLK lo, MOSI 0 (b15)
-$0FFD1				NOP CKE				CLK hi
-$0FFD2				NOP	CKE				CLK lo, MOSI 0 (b14)
-$0FFD3				AREF				CLK hi
-$0FFD4				NOP	CKE				CLK lo, MOSI 0 (b13)
-$0FFD5				NOP	CKE				CLK hi
-$0FFD6				NOP	CKE				CLK lo, MOSI 0 (b12)
-$0FFD7				NOP	CKE				CLK hi
-$0FFD8				NOP	CKE				CLK lo, MOSI 0 (b11)
-$0FFD9				NOP	CKE				CLK hi
-$0FFDA				NOP	CKE				CLK lo, MOSI 0 (b10)
-$0FFDB				AREF				CLK hi
-$0FFDC				NOP CKE				CLK lo, MOSI 0 (b9)
-$0FFDD				NOP CKE				CLK hi
-$0FFDE				NOP	CKE				CLK lo, MOSI 0 (b8)
-$0FFDF				NOP CKE				CLK hi
-$0FFE0				NOP	CKE				CLK lo, MOSI 0 (b7)
-$0FFE1				NOP CKE				CLK hi
-$0FFE2				NOP	CKE				CLK lo, MOSI 0 (b6)
-$0FFE3				AREF				CLK hi
-$0FFE4				NOP	CKE				CLK lo, MOSI 0 (b5)
-$0FFE5				NOP	CKE				CLK hi
-$0FFE6				NOP	CKE				CLK lo, MOSI 0 (b4)
-$0FFE7				NOP	CKE				CLK hi
-$0FFE8				NOP	CKE				CLK lo, MOSI 0 (b3)
-$0FFE9				NOP	CKE				CLK hi
-$0FFEA				NOP	CKE				CLK lo, MOSI 0 (b2)
-$0FFEB				AREF				CLK hi
-$0FFEC				NOP CKE				CLK lo, MOSI 0 (b1)
-$0FFED				NOP CKE				CLK hi
-$0FFEE				NOP	CKE				CLK lo, MOSI 0 (b0)
-$0FFEF				NOP CKE				CLK hi
-
-$0FFF0-$0FFFF		Init: mode & ref	8 dummy clocks			2
-$0FFF0				NOP	CKE				CLK lo, MOSIOE 0
-$0FFF1				NOP CKE				CLK hi
-$0FFF2				NOP	CKE				CLK lo
-$0FFF3				AREF				CLK hi
-$0FFF4				NOP CKE				CLK lo
-$0FFF5				NOP	CKE				CLK hi
-$0FFF6				NOP	CKE				CLK lo
-$0FFF7				NOP	CKE				CLK hi
-$0FFF8				NOP	CKE				CLK lo
-$0FFF9				NOP	CKE				CLK hi
-$0FFFA				NOP	CKE				CLK lo
-$0FFFB				AREF				CLK hi
-$0FFFC				NOP CKE				CLK lo
-$0FFFD				NOP CKE				CLK hi
-$0FFFE				NOP	CKE				CLK lo
-$0FFFF				NOP CKE				CLK hi
-
-$10000-$2FFFF		Write ROM data		Shift in read data		3
-$10000				NOP CKE				CLK lo
-$10001				NOP CKE				CLK hi, get b7:6 of $000000
-$10002				NOP CKE				CLK lo
-$10003				AREF				CLK hi, get b5:4 of $000000
-$10004				NOP CKE				CLK lo
-$10005				ACT					CLK hi, get b3:2 of $000000
-$10006				NOP CKE				CLK lo
-$10007				WR AP				CLK hi, get b1:0 of $000000
-$10008				NOP CKE				CLK lo
-$10009				NOP CKE				CLK hi, get b7:6 of $000001
-$1000A				NOP CKE				CLK lo
-$1000B				AREF				CLK hi, get b5:4 of $000001
-$1000C				NOP CKE				CLK lo
-$1000D				ACT					CLK hi, get b3:2 of $000001
-$1000E				NOP CKE				CLK lo
-$1000F				WR AP				CLK hi, get b1:0 of $000001
-...
-$2FFF0				NOP CKE				CLK lo
-$2FFF1				NOP CKE				CLK hi, get b7:6 of $003FFE
-$2FFF2				NOP CKE				CLK lo
-$2FFF3				AREF				CLK hi, get b5:4 of $003FFE
-$2FFF4				NOP CKE				CLK lo
-$2FFF5				ACT					CLK hi, get b3:2 of $003FFE
-$2FFF6				NOP CKE				CLK lo
-$2FFF7				WR AP				CLK hi, get b1:0 of $003FFE
-$2FFF8				NOP CKE				CLK lo
-$2FFF9				NOP CKE				CLK hi, get b7:6 of $003FFF
-$2FFFA				NOP CKE				CLK lo
-$2FFFB				AREF				CLK hi, get b5:4 of $003FFF
-$2FFFC				NOP CKE				CLK lo
-$2FFFD				ACT					CLK hi, get b3:2 of $003FFF
-$2FFFE				NOP CKE				CLK lo
-$2FFFF				WR AP				CLK hi, get b1:0 of $003FFF
-
-$30000				NOP CKE				CLK lo, /CS hi			3
-$30001				NOP CKE				CLK lo, /CS hi			3
-$30002				NOP CKE				CLK lo, /CS hi			3		SDRAMActv <= InitActv && ~InitInterrupted
-
-

Documentation/RAM Map

@@ -1,64 +1,32 @@
 GR8RAM/LibraryCard Slinky RAM memory map
 			-----------------------------
 1 FF FFFF	|							|
-. .. ....	| LibCrd sect. cache (8 MB) |
+. .. ....	|    reserved (16,376 kB)   |
-1 80 0000	|							|
+1 00 2000	|							|
 			-----------------------------
-1 7F FFFF	|							|
+1 00 1FFF	|							|
-. .. ....	|  LibCrd registers (1 MB)  |
+. .. ....	|      firmware (8 kB)      |
-1 70 0000	|							|
-			-----------------------------
-1 6F FFFF	|							|
-. .. ....	|    reserved (5.9375 MB)   |
-1 11 0000	|							|
-			-----------------------------
-1 10 FFFF	|							|
-. .. ....	|     RAM shadow (64 kB)    |
-1 10 0000	|							|
-			-----------------------------
-1 0F FFFF	|							|
-. .. ....	|      firmware (1 MB)      |
 1 00 0000	|							|
 			-----------------------------
 0 FF FFFF	|							|
-. .. ....	|   RAMFactor RAM (16 MB)   |
+. .. ....	|     Slinky RAM (16 MB)    |
 0 00 0000	|							|
 			-----------------------------
 
-Firmware area map (X == 0, 1, 2, or 3)
 			-----------------------------
-1 0F FFFF	|							|
+1 00 1FFF	|							|
-. .. ....	|     reserved (510 kB)     |
+....		|    IOSTRB bank 1 (2 kB)   |
-1 08 0800	|							|
+1 00 1800	|							|
 			-----------------------------
-1 08 07FF	|							|
+1 00 17FF	|							|
-. .. ....	|     IOSEL area (2 kB)     |
+....		|    IOSEL bank 1 (2 kB)    |
-1 08 0000	|							|
+1 00 1000	|							|
 			-----------------------------
-1 07 FFFF	|							|
+1 00 0FFF	|							|
-. .. ....	| 256x IOSTRB area (512 kB) |
+....		|    IOSTRB bank 0 (2 kB)   |
+1 00 0800	|							|
+			-----------------------------
+1 00 07FF	|							|
+....		|    IOSEL bank 0 (2 kB)    |
 1 00 0000	|							|
 			-----------------------------
-
-Library Card register space
-			-----------------------------
-1 7F FFFF	|							|
-. .. ....	|     reserved (768 kB)     |
-1 74 0000	|							|
-			-----------------------------
-1 73 FFFF	|							|
-. .. ....	|    response B (64 kB)     |
-1 73 0000	|							|
-			-----------------------------
-1 72 FFFF	|							|
-. .. ....	|     command B (64 kB)     |
-1 72 0000	|							|
-			-----------------------------
-1 71 FFFF	|							|
-. .. ....	|    response A (64 kB)     |
-1 71 0000	|							|
-			-----------------------------
-1 70 FFFF	|							|
-. .. ....	|     command A (64 kB)     |
-1 70 0000	|							|
-			-----------------------------

Flash.kicad_sch

@@ -0,0 +1,711 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 338db033-7222-493c-b07e-a7cf97c3103c)
+
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+
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+    (property "Value" "GND" (id 1) (at 74.93 66.04 0))
+    (property "Footprint" "" (id 2) (at 74.93 62.23 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 74.93 62.23 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 1cecbf72-1147-457f-a6fd-d4a166ff67d2))
+  )
+
+  (symbol (lib_id "power:GND") (at 93.98 90.17 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid e0072c1b-6727-4e16-9dba-1bf65c7024c3)
+    (property "Reference" "#PWR?" (id 0) (at 93.98 96.52 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 93.98 93.98 0))
+    (property "Footprint" "" (id 2) (at 93.98 90.17 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 93.98 90.17 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 0b3b63b6-6205-4188-9ef9-e689bcd5562d))
+  )
+)

GR8RAM

@@ -0,0 +1,21 @@
+Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
+C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
+C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
+FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
+H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
+H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
+J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
+J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
+J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
+R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
+R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
+RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
+RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
+SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
+U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
+U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
+U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
+U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
+U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
+U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
+U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"

GR8RAM.kicad_prl

@@ -0,0 +1,75 @@
+{
+  "board": {
+    "active_layer": 31,
+    "active_layer_preset": "All Layers",
+    "auto_track_width": true,
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      8,
+      9,
+      10,
+      11,
+      12,
+      13,
+      14,
+      15,
+      16,
+      17,
+      18,
+      19,
+      20,
+      21,
+      22,
+      23,
+      24,
+      25,
+      26,
+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "GR8RAM.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

GR8RAM.kicad_pro

@@ -0,0 +1,481 @@
+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.15,
+        "copper_line_width": 0.15,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.0,
+          "height": 0.4,
+          "width": 0.65
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.15239999999999998
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_copper_edge_clearance": 0.075,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.19999999999999998,
+        "min_track_width": 0.15,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.5,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.2,
+        0.25,
+        0.3,
+        0.35,
+        0.4,
+        0.45,
+        0.5,
+        0.6,
+        0.762,
+        0.8,
+        1.0,
+        1.27,
+        1.524
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        },
+        {
+          "diameter": 0.6,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.4
+        },
+        {
+          "diameter": 1.0,
+          "drill": 0.5
+        },
+        {
+          "diameter": 1.524,
+          "drill": 0.762
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
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+      ],
+      [
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+        0,
+        0,
+        0,
+        0,
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+        0,
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+      ],
+      [
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+        0,
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+        0,
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+      ],
+      [
+        1,
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+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "GR8RAM.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.15,
+        "via_diameter": 0.5,
+        "via_drill": 0.2,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "GR8RAM.net",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Pcbnew",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "a29f8df0-3fae-4edf-8d9c-bd5a875b13e3",
+      ""
+    ],
+    [
+      "5d5cfbc1-a859-408c-aee8-9a6703975d80",
+      "BODMenu"
+    ],
+    [
+      "42756051-0be2-4880-864b-fa79351a044a",
+      "RAM"
+    ],
+    [
+      "c2580631-96cd-4aba-83d1-d73c0d0a7eb8",
+      "Flash"
+    ],
+    [
+      "b0ddb503-a391-46dd-bf77-8b8b2cf30231",
+      "Bus"
+    ],
+    [
+      "f81ef440-950e-4d05-b370-6421f2c33ca7",
+      "Prog"
+    ],
+    [
+      "b30763ef-424b-4a57-9138-82e38c28db28",
+      "Control"
+    ]
+  ],
+  "text_variables": {}
+}

GR8RAM.pro

@@ -1,269 +0,0 @@
-update=Wednesday, January 06, 2021 at 01:09:33 AM
-version=1
-last_client=kicad
-[general]
-version=1
-RootSch=
-BoardNm=
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-[pcbnew]
-version=1
-PageLayoutDescrFile=
-LastNetListRead=GR8RAM.net
-CopperLayerCount=4
-BoardThickness=1.6
-AllowMicroVias=0
-AllowBlindVias=0
-RequireCourtyardDefinitions=0
-ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.15
-MinViaDiameter=0.5
-MinViaDrill=0.2
-MinMicroViaDiameter=0.2
-MinMicroViaDrill=0.09999999999999999
-MinHoleToHole=0.25
-TrackWidth1=0.15
-TrackWidth2=0.2
-TrackWidth3=0.25
-TrackWidth4=0.3
-TrackWidth5=0.35
-TrackWidth6=0.4
-TrackWidth7=0.45
-TrackWidth8=0.5
-TrackWidth9=0.6
-TrackWidth10=0.762
-TrackWidth11=0.8
-TrackWidth12=1
-TrackWidth13=1.27
-TrackWidth14=1.524
-ViaDiameter1=0.5
-ViaDrill1=0.2
-ViaDiameter2=0.6
-ViaDrill2=0.3
-ViaDiameter3=0.8
-ViaDrill3=0.4
-ViaDiameter4=1
-ViaDrill4=0.5
-ViaDiameter5=1.524
-ViaDrill5=0.762
-dPairWidth1=0.2
-dPairGap1=0.25
-dPairViaGap1=0.25
-SilkLineWidth=0.15
-SilkTextSizeV=1
-SilkTextSizeH=1
-SilkTextSizeThickness=0.15
-SilkTextItalic=0
-SilkTextUpright=1
-CopperLineWidth=0.15
-CopperTextSizeV=1.5
-CopperTextSizeH=1.5
-CopperTextThickness=0.3
-CopperTextItalic=0
-CopperTextUpright=1
-EdgeCutLineWidth=0.15
-CourtyardLineWidth=0.05
-OthersLineWidth=0.15
-OthersTextSizeV=1
-OthersTextSizeH=1
-OthersTextSizeThickness=0.15
-OthersTextItalic=0
-OthersTextUpright=1
-SolderMaskClearance=0.07619999999999999
-SolderMaskMinWidth=0.127
-SolderPasteClearance=-0.03809999999999999
-SolderPasteRatio=0
-[pcbnew/Layer.F.Cu]
-Name=F.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.In1.Cu]
-Name=In1.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.In2.Cu]
-Name=In2.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.In3.Cu]
-Name=In3.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In4.Cu]
-Name=In4.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In5.Cu]
-Name=In5.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In6.Cu]
-Name=In6.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In7.Cu]
-Name=In7.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In8.Cu]
-Name=In8.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In9.Cu]
-Name=In9.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In10.Cu]
-Name=In10.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In11.Cu]
-Name=In11.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In12.Cu]
-Name=In12.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In13.Cu]
-Name=In13.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In14.Cu]
-Name=In14.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In15.Cu]
-Name=In15.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In16.Cu]
-Name=In16.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In17.Cu]
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Power.kicad_sch

@@ -0,0 +1,10 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid b3ed0c9f-df03-4199-8370-2f60373cb654)
+
+  (paper "A4")
+
+  (lib_symbols
+  )
+
+)

RAM.kicad_sch

@@ -0,0 +1,951 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
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+
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+  )
+  (label "RA0" (at 140.97 99.06 180)
+    (effects (font (size 1.27 1.27)) (justify right bottom))
+    (uuid f6f3acb1-1a2e-40a6-9eba-12e97533fc3c)
+  )
+
+  (hierarchical_label "RBA[1..0]" (shape input) (at 130.81 129.54 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid 0a97c494-9fa6-4758-b55d-ab0c1c9ae24c)
+  )
+  (hierarchical_label "RD[7..0]" (shape input) (at 189.23 97.79 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 2b179112-1be9-47df-a7db-a06fdfddbd4b)
+  )
+  (hierarchical_label "RCKE" (shape input) (at 140.97 139.7 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid 2de07676-3139-4375-81cd-7c83419660f8)
+  )
+  (hierarchical_label "R~{WE}" (shape input) (at 166.37 144.78 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 391915af-0708-47e9-998b-80b571f5d1c7)
+  )
+  (hierarchical_label "RCLK" (shape input) (at 140.97 142.24 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid 39e5997a-987a-4ee7-a817-249890977648)
+  )
+  (hierarchical_label "RA[12..0]" (shape input) (at 132.08 96.52 180)
+    (effects (font (size 1.27 1.27)) (justify right))
+    (uuid 4a15f762-3076-4556-99c9-a92c0bc29f9d)
+  )
+  (hierarchical_label "RDQMH" (shape input) (at 166.37 134.62 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 5223f601-c64f-4833-848f-b7c60a751a90)
+  )
+  (hierarchical_label "RDQML" (shape input) (at 166.37 132.08 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 53b8355b-6fa2-40e6-9714-416f0a3a7354)
+  )
+  (hierarchical_label "R~{CAS}" (shape input) (at 166.37 147.32 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 9f1a8992-6540-4c89-a41d-cb4944736c44)
+  )
+  (hierarchical_label "R~{CS}" (shape input) (at 166.37 142.24 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid acdf4cbd-6248-44cc-8126-25861ccf67ff)
+  )
+  (hierarchical_label "R~{RAS}" (shape input) (at 166.37 149.86 0)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid ff3fc25e-b595-445e-a10d-880e2b8a8d75)
+  )
+
+  (symbol (lib_id "power:+3V3") (at 140.97 91.44 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid 699837c5-d32c-474a-b63b-e59d4fab46b6)
+    (property "Reference" "#PWR?" (id 0) (at 140.97 95.25 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "+3V3" (id 1) (at 140.97 87.63 0))
+    (property "Footprint" "" (id 2) (at 140.97 91.44 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 140.97 91.44 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 1036f0aa-c9fb-4459-a225-a14342b963c3))
+  )
+
+  (symbol (lib_id "GW_RAM:SDRAM-16Mx16-TSOP2-54") (at 153.67 116.84 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid c12d46d6-ecc3-44af-b09c-722c28846223)
+    (property "Reference" "U?" (id 0) (at 153.67 87.63 0))
+    (property "Value" "W9825" (id 1) (at 153.67 116.84 90))
+    (property "Footprint" "stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm" (id 2) (at 153.67 158.75 0)
+      (effects (font (size 1.27 1.27) italic) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 153.67 123.19 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "LCSC Part" "C62246" (id 4) (at 153.67 116.84 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 43f38cde-1aa5-4f77-83c4-d68e96ea82b7))
+    (pin "10" (uuid 6323dd2d-2d2f-4256-ae4a-08f977490a2f))
+    (pin "11" (uuid e971215b-97be-482e-a349-b9fb0b6cfe23))
+    (pin "12" (uuid 4bd92852-0728-4d28-aa21-ffb40480284a))
+    (pin "13" (uuid cc3706ed-d983-4feb-9a9d-9d9a0fac8924))
+    (pin "14" (uuid a464cfe5-e8ef-43b8-ae36-818510dbf288))
+    (pin "15" (uuid 9f6b2e25-9bc5-4bbe-bd8f-bc9201cf7685))
+    (pin "16" (uuid 6d064820-4c42-4eb1-a29c-f811ee9015be))
+    (pin "17" (uuid f2c1b5f7-a866-484c-a0f0-952511bd0dff))
+    (pin "18" (uuid 79c11c66-c14c-4b7c-947d-d65140cb857d))
+    (pin "19" (uuid e1e2d925-6225-40c0-b96b-3e86f8b59de6))
+    (pin "2" (uuid b276eaf6-50c9-49f8-b6c7-e329d384be2e))
+    (pin "20" (uuid cfa10b09-9fb5-4f62-ae9f-ac29f980fad9))
+    (pin "21" (uuid b97466d2-86c3-4397-a9c5-687ec81193bb))
+    (pin "22" (uuid 14578331-7ba4-4679-ad80-f91b78645231))
+    (pin "23" (uuid 9f851a5f-1f35-42a6-bf6b-9faabe3e1480))
+    (pin "24" (uuid 8cd3e5a3-9f52-4727-867f-af1fe5fc7f35))
+    (pin "25" (uuid 10a5d9a1-37fb-4ca7-8b33-ebc0baeff3e9))
+    (pin "26" (uuid bd84d7a0-905e-47d4-ac69-f8f4e70ebc60))
+    (pin "27" (uuid 096bb759-d542-4bcc-9aa9-d07670e05015))
+    (pin "28" (uuid ba45f92b-952a-4c16-bb45-647b740e1b81))
+    (pin "29" (uuid b4c9ccd1-df36-46a3-acdc-58971fd0ac10))
+    (pin "3" (uuid caadf4e6-a882-41ce-bce3-1503aab67f27))
+    (pin "30" (uuid 98165bba-75c3-49a3-97ab-8396c0b2f213))
+    (pin "31" (uuid d219e2c7-5a05-472e-992a-2063498e46c7))
+    (pin "32" (uuid 58570fb8-6218-4695-9e98-67cedafebf15))
+    (pin "33" (uuid b7312235-1068-4387-b6cc-9cf1e6471d3c))
+    (pin "34" (uuid ecced02d-dad6-4972-b872-8c07a735455c))
+    (pin "35" (uuid e0f95cbd-acde-4aa6-90ff-67a29620af10))
+    (pin "36" (uuid 8f54feb2-864d-4bc7-9ad6-a79f8edeab8d))
+    (pin "37" (uuid 921dc129-be15-44d9-957f-51a37c3d35c7))
+    (pin "38" (uuid be1ec3b7-1273-4935-af0d-a6011f4ee0dc))
+    (pin "39" (uuid 3b02efe1-9524-473c-a425-ead60f2ed559))
+    (pin "4" (uuid fbaeb772-fad2-4ce9-b888-8e7cdc031283))
+    (pin "41" (uuid 3a7e7fd9-95dc-437b-b708-b9f30b3ed23a))
+    (pin "42" (uuid 8598dbed-1b83-492f-b511-1334e6560a8e))
+    (pin "43" (uuid d345be69-4679-40ca-aee8-4f7db099fc6c))
+    (pin "44" (uuid e35463ec-d3e0-40d9-bcd1-bb47921904c8))
+    (pin "45" (uuid 532ae820-5022-4fd1-9185-4422ea18e815))
+    (pin "46" (uuid 207c5eaa-8e8f-4b08-900e-5d0444ba2bc5))
+    (pin "47" (uuid dc3eaaa3-bdcc-4c6d-860c-f2bf34346000))
+    (pin "48" (uuid fc4a0c56-9281-422e-b219-b812033da3e9))
+    (pin "49" (uuid d0b6b3c4-ce20-4253-8156-b1dd66010f26))
+    (pin "5" (uuid 6adc92bc-39bc-4ff7-bc8e-357d3a47f9e1))
+    (pin "50" (uuid 9a539a06-c001-4d2e-96f9-47df884db7ce))
+    (pin "51" (uuid 34b8deea-4727-4e0d-a15c-bdbae4787f4a))
+    (pin "52" (uuid 97fb6b11-eae7-452b-98c6-55ac4d4ada3b))
+    (pin "53" (uuid 571e76a0-d90e-4a83-be4c-326f7777d382))
+    (pin "54" (uuid 0e18a115-5538-421a-8c28-4d9323a2ed78))
+    (pin "6" (uuid 8be94113-0455-4a10-a2d3-30cbc6eac3aa))
+    (pin "7" (uuid 5a7ee362-1502-49d0-8aea-a86252673b98))
+    (pin "8" (uuid e7beeb1d-8200-4278-8357-5ff3c8572d20))
+    (pin "9" (uuid c851050b-3f04-470e-a6c4-bc3b82e5b0eb))
+  )
+
+  (symbol (lib_id "power:GND") (at 140.97 149.86 0) (unit 1)
+    (in_bom yes) (on_board yes)
+    (uuid d02f169e-c016-45f9-9f0f-9e28e2bb4925)
+    (property "Reference" "#PWR?" (id 0) (at 140.97 156.21 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 140.97 153.67 0))
+    (property "Footprint" "" (id 2) (at 140.97 149.86 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 140.97 149.86 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid c5e38eae-5298-45a3-bb3b-e1ae7eba8fcc))
+  )
+)

cpld/GR8RAM.dpf

@@ -1,20 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<pin_planner>
-	<pin_info>
-		<pin name="Ddor" source="Pin Planner" >
-		</pin>
-		<pin name="SDp1[" source="Pin Planner" >
-		</pin>
-		<pin name="sa[10[" source="Pin Planner" >
-		</pin>
-		<pin name="fw[0]" source="Pin Planner" >
-		</pin>
-	</pin_info>
-	<buses>
-	</buses>
-	<group_file_association>
-	</group_file_association>
-	<pin_planner_file_specifies>
-	</pin_planner_file_specifies>
-</pin_planner>

cpld/GR8RAM.qsf

@@ -84,7 +84,6 @@ set_location_assignment PIN_12 -to FCK
 set_location_assignment PIN_14 -to RA[10]
 set_location_assignment PIN_15 -to MOSI
 set_location_assignment PIN_16 -to MISO
-set_location_assignment PIN_17 -to Ddir
 set_location_assignment PIN_30 -to nRESout
 set_location_assignment PIN_34 -to RA[11]
 set_location_assignment PIN_35 -to RA[12]
@@ -142,4 +141,132 @@ set_location_assignment PIN_98 -to RA[1]
 set_location_assignment PIN_96 -to SetFW[0]
 set_location_assignment PIN_95 -to SetFW[1]
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO
+set_location_assignment PIN_21 -to nDMAout
+set_location_assignment PIN_19 -to RAdir
+set_location_assignment PIN_20 -to INTout
+set_location_assignment PIN_26 -to nNMIout
+set_location_assignment PIN_27 -to nINHout
+set_location_assignment PIN_28 -to nRDYout
+set_location_assignment PIN_29 -to nIRQout
+set_location_assignment PIN_33 -to RWout
+set_location_assignment PIN_48 -to DMAin
+set_location_assignment PIN_49 -to INTin
+set_location_assignment PIN_17 -to RDdir
+set_location_assignment PIN_18 -to DMAout
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
+set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nWE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nDEVSEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSTRB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRES
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK
+set_instance_assignment -name SLOW_SLEW_RATE ON -to FCK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH
+set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML
+set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
+set_global_assignment -name SDC_FILE GR8RAM.sdc

cpld/GR8RAM.sdc

@@ -0,0 +1,3 @@
+create_clock -period 40 [get_ports C25M]
+create_clock -period 978 [get_ports PHI0]
+set_clock_groups -asynchronous -group C25M -group PHI0

cpld/GR8RAM.v

@@ -1,7 +1,7 @@
-module GR8RAM(C25M, PHI0, nRES, nRESout,
+module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
-			  nIOSEL, nDEVSEL, nIOSTRB,
+			  INTin, INTout, DMAin, DMAout, 
-			  SetFW,
+			  nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
-			  RA, nWE, RD, RDdir,
+			  RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
 			  SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
 			  nFCS, FCK, MISO, MOSI);
 
@@ -9,11 +9,38 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 	input C25M, PHI0;
 	reg PHI0r1, PHI0r2;
 	always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
-
+	
-	/* Reset/brown-out detect synchronized inputs */
+	/* Reset filter */
 	input nRES;
-	reg nRESr0, nRESr;
+	reg [3:0] nRESf = 0;
-	always @(posedge C25M) begin nRESr0 <= nRES; nRESr <= nRESr0; end
+	reg nRESr = 0;
+	always @(posedge C25M) begin 
+		nRESf[3:0] <= { nRESf[2:0], nRES };
+		nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
+	end
+
+	/* Firmware select */
+	input [1:0] SetFW;
+	reg [1:0] SetFWr;
+	reg SetFWLoaded = 0;
+	always @(posedge C25M) begin
+		if (~SetFWLoaded) begin
+			SetFWLoaded <= 1;
+			SetFWr[1:0] <= SetFW[1:0];
+		end
+	end
+	wire [1:0] SetROM = ~SetFWr[1:0];
+	wire SetEN16MB = SetROM[1:0]==2'b11;
+	wire SetEN24bit = SetROM[1];
+
+	/* State counter from PHI0 rising edge */
+	reg [3:0] PS = 0;
+	wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
+	always @(posedge C25M) begin
+		if (PSStart) PS <= 1;
+		else if (PS==0) PS <= 0;
+		else PS <= PS+1;
+	end
 
 	/* Long state counter: counts from 0 to $3FFF */
 	reg [13:0] LS = 0;
@@ -38,48 +65,52 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 
 	/* Apple address bus */
 	input [15:0] RA; input nWE;
+	reg   [11:0] RAr; reg nWEr;
+	reg CXXXr;
+	always @(posedge PHI0) begin
+		CXXXr <= RA[15:12]==4'hC;
+		RAr[11:0] <= RA[11:0];
+		nWEr <= nWE;
+	end
 
 	/* Apple select signals */
-	wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0;
+	wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
-	wire BankSpecSEL = RA[3:0]==4'hF;
+	wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
-	wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN;
+	wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
-	wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3 && (~SetLim1M || Addr[23:20]==0) && (~SetLim8M || ~Addr[23]);
+	wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
-	wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2;
+	wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
-	wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1;
+	wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
-	wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0;
+	wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
-	reg ROMSpecSELr, RAMSpecSELr, nWEr;
+	wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
 	wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
-	wire RAMSEL = ~nDEVSEL && RAMSpecSELr;
+	wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL;
+	wire RAMSEL = ~nDEVSEL && RAMSpecSEL;
 	wire RAMWR = RAMSEL && ~nWEr;
 	wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
 	wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
 	wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
-	always @(posedge PHI0) begin
-		ROMSpecSELr <= ROMSpecSEL;
-		RAMSpecSELr <= RAMSpecSEL;
-		nWEr <= nWE;
-	end
 	
 	/* IOROMEN and REGEN control */
 	reg IOROMEN = 0;
 	reg REGEN = 0;
+	reg nIOSTRBr;
+	wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr;
 	always @(posedge C25M, negedge nRESr) begin
-		if (~nRESr) begin
+		if (~nRESr) REGEN <= 0;
-			IOROMEN <= 0;
+		else if (PS==8 && ~nIOSEL) REGEN <= 1;
-			REGEN <= 0;
+	end
-		end else if (PS==8 && ~nIOSTRB && RA[10:0]==11'h7FF) begin
+	always @(posedge C25M) begin
-			IOROMEN <= 0;
+		nIOSTRBr <= nIOSTRB;
-		end else if (PS==8 && ~nIOSEL) begin
+		if (~nRESr) IOROMEN <= 0;
-			IOROMEN <= 1;
+		else if (PS==8 && IOROMRES) IOROMEN <= 0;
-			REGEN <= 1;
+		else if (PS==8 && ~nIOSEL) IOROMEN <= 1;
-		end
 	end
 
 	/* Apple data bus */
 	inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
 	reg [7:0] RDD;
 	output RDdir = ~(PHI0r2 && nWE && PHI0 &&
-		(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)));
+		(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
 
 	/* Slinky address registers */
 	reg [23:0] Addr = 0;
@@ -93,7 +124,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 			AddrIncM <= 0;
 			AddrIncH <= 0;
 		end else begin
-			if (PS==8 && RAMSEL) AddrIncL <= 1;
+			if (PS==8 && RAMRegSEL) AddrIncL <= 1;
 			else AddrIncL <= 0;
 
 			if (PS==8 && AddrLSEL && ~nWEr) begin
@@ -129,57 +160,61 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 		end
 	end
 
-	/* SPI flash */
+	/* SPI flash control signals */
-	output nFCS = ~FCS;
+	output nFCS = FCKOE ? ~FCS : 1'bZ;
 	reg FCS = 0;
-	output reg FCK = 0;
+	output FCK = FCKOE ? FCKout : 1'bZ;
+	reg FCKOE = 0;
+	reg FCKout = 0;
 	inout MOSI = MOSIOE ? MOSIout : 1'bZ;
 	reg MOSIOE = 0;
-	reg MOSIout;
 	input MISO;
 	always @(posedge C25M) begin
 		case (PS[3:0])
 			0: begin // NOP CKE
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 1: begin // ACT
-				FCK <= ~(IS==5 || IS==6);
+				FCKout <= ~(IS==5 || IS==6);
 			end 2: begin // RD
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 3: begin // NOP CKE
-				FCK <= ~(IS==5 || IS==6);
+				FCKout <= ~(IS==5 || IS==6);
 			end 4: begin // NOP CKE
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 5: begin // NOP CKE
-				FCK <= ~(IS==5 || IS==6);
+				FCKout <= ~(IS==5 || IS==6);
 			end 6: begin // NOP CKE
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 7: begin // NOP CKE
-				FCK <= ~(IS==5 || IS==6);
+				FCKout <= ~(IS==5 || IS==6);
 			end 8: begin // WR AP
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 9: begin // NOP CKE
-				FCK <= ~(IS==5);
+				FCKout <= ~(IS==5);
 			end 10: begin // PC all
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 11: begin // AREF
-				FCK <= ~(IS==5);
+				FCKout <= ~(IS==5);
 			end 12: begin // NOP CKE
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 13: begin // NOP CKE
-				FCK <= ~(IS==5);
+				FCKout <= ~(IS==5);
 			end 14: begin // NOP CKE
-				FCK <= 1'b1;
+				FCKout <= 1'b1;
 			end 15: begin // NOP CKE
-				FCK <= ~(IS==5);
+				FCKout <= ~(IS==5);
 			end
 		endcase
 		FCS <= IS==4 || IS==5 || IS==6;
 		MOSIOE <= IS==5;
+		FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
 	end
 
+	/* SPI flash MOSI control */
+	reg MOSIout = 0;
 	always @(posedge C25M) begin
 		case (PS[3:0])
-			1, 2: begin
+			1: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b0; // Command bit 7
 					3'h4: MOSIout <= 1'b0; // Address bit 23
@@ -187,23 +222,23 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 					3'h6: MOSIout <= 1'b0; // Address bit 7
 					default MOSIout <= 1'b0;
 				endcase
-			end 3, 4: begin
+			end 3: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b0; // Command bit 6
 					3'h4: MOSIout <= 1'b0; // Address bit 22
-					3'h5: MOSIout <= SetFW[1]; // Address bit 14
+					3'h5: MOSIout <= SetROM[1]; // Address bit 14
 					3'h6: MOSIout <= 1'b0; // Address bit 6
 					default MOSIout <= 1'b0;
 				endcase
-			end 5, 6: begin
+			end 5: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b1; // Command bit 5
 					3'h4: MOSIout <= 1'b0; // Address bit 21
-					3'h5: MOSIout <= SetFW[0]; // Address bit 13
+					3'h5: MOSIout <= SetROM[0]; // Address bit 13
 					3'h6: MOSIout <= 1'b0; // Address bit 5
 					default MOSIout <= 1'b0;
 				endcase
-			end 7, 8: begin
+			end 7: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b1; // Command bit 4
 					3'h4: MOSIout <= 1'b0; // Address bit 20
@@ -211,7 +246,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 					3'h6: MOSIout <= 1'b0; // Address bit 4
 					default MOSIout <= 1'b0;
 				endcase
-			end 9, 10: begin
+			end 9: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b1; // Command bit 3
 					3'h4: MOSIout <= 1'b0; // Address bit 19
@@ -219,7 +254,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 					3'h6: MOSIout <= 1'b0; // Address bit 3
 					default MOSIout <= 1'b0;
 				endcase
-			end 11, 12: begin
+			end 11: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b0; // Command bit 2
 					3'h4: MOSIout <= 1'b0; // Address bit 18
@@ -227,7 +262,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 					3'h6: MOSIout <= 1'b0; // Address bit 2
 					default MOSIout <= 1'b0;
 				endcase
-			end 13, 14: begin
+			end 13: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b1; // Command bit 1
 					3'h4: MOSIout <= 1'b0; // Address bit 16
@@ -235,7 +270,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 					3'h6: MOSIout <= 1'b0; // Address bit 1
 					default MOSIout <= 1'b0;
 				endcase
-			end 15, 0: begin
+			end 15: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b1; // Command bit 0
 					3'h4: MOSIout <= 1'b0; // Address bit 15
@@ -247,11 +282,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 		endcase
 	end
 
-	input [1:0] SetFW;
-	wire SetRF = SetFW[1:0] != 2'b11;
-	wire SetLim1M = SetFW[1];
-	wire SetLim8M = SetFW[1:0] != 2'b00;
-
 	/* SDRAM data bus */
 	inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
 	reg [7:0] WRD;
@@ -259,55 +289,52 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 	always @(posedge C25M) begin
 		case (PS[3:0])
 			0: begin // NOP CKE
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
 				else WRD[7:0] <= RD[7:0];
 			end 1: begin // ACT
 			end 2: begin // RD
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
 				else WRD[7:0] <= RD[7:0];
 			end 3: begin // NOP CKE
 			end 4: begin // NOP CKE
-				if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
-				else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
-				else if (AddrHSpecSEL && SetRF) RDD[7:0] <= Addr[23:16];
-				else if (AddrHSpecSEL && ~SetRF) RDD[7:0] <= {4'hF, Addr[19:16]};
-				else RDD[7:0] <= SD[7:0];
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
 				else WRD[7:0] <= RD[7:0];
 			end 5: begin // NOP CKE
 			end 6: begin // NOP CKE
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
 				else WRD[7:0] <= RD[7:0];
 			end 7: begin // NOP CKE
 			end 8: begin // WR AP
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
 				else WRD[7:0] <= RD[7:0];
 			end 9: begin // NOP CKE
 			end 10: begin // PC all
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
 				else WRD[7:0] <= RD[7:0];
 			end 11: begin // AREF
 			end 12: begin // NOP CKE
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
 				else WRD[7:0] <= RD[7:0];
 			end 13: begin // NOP CKE
 			end 14: begin // NOP CKE
-				if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
 				else WRD[7:0] <= RD[7:0];
 			end 15: begin // NOP CKE
 			end
 		endcase
 	end
 
-	reg [3:0] PS = 0;
+	/* Apple data bus from SDRAM */
-	wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
+	always @(negedge C25M) begin
-	always @(posedge C25M) begin
+		if (PS==5) begin
-		if (PSStart) PS <= 1;
+			if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
-		else if (PS==0) PS <= 0;
+			else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
-		else PS <= PS+1;
+			else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
+			else RDD[7:0] <= SD[7:0];
+		end
 	end
 
-	/* SDRAM address/command */
+	/* SDRAM command */
 	output reg RCKE = 1;
 	output reg nRCS = 1;
 	output reg nRAS = 1;
@@ -316,125 +343,102 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 	wire RefReqd = LS[1:0] == 2'b11;
 	always @(posedge C25M) begin
 		case (PS[3:0])
-			0: begin // NOP CKE / CKD
+			0: begin // NOP CKE / NOP CKD
-				RCKE <= PSStart;
+				RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
-				nRCS <= 1'b1;
+				nRCS <= 1;
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b1;	
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
-			end 1: begin // ACT CKE / NOP CKD
+			end 1: begin // ACT CKE / NOP CKD (ACT)
-				RCKE <= IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7);
+				RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
-				nRCS <= ~(IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7));
+				nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
-				nRAS <= 1'b0;
+				nRAS <= 0;
-				nCAS <= 1'b1;
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
-			end 2: begin // RD CKE / NOP CKD
+			end 2: begin // RD CKE / NOP CKD (RD)
-				RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
-				nRCS <= ~((ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7);
+				nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b0;
+				nCAS <= 0;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
 			end 3: begin // NOP CKE / CKD
-				RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
-				nRCS <= 1'b1;
+				nRCS <= 1;
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b1;
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
 			end 4: begin // NOP CKD
-				RCKE <= 1'b0;
+				RCKE <= 0;
-				nRCS <= 1'b1;
+				nRCS <= 1;
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b1;
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
 			end 5: begin // NOP CKD
-				RCKE <= 1'b0;
+				RCKE <= 0;
-				nRCS <= 1'b1;
+				nRCS <= 1;
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b1;
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
 			end 6: begin // NOP CKD
-				RCKE <= 1'b0;
+				RCKE <= 0;
-				nRCS <= 1'b1;
+				nRCS <= 1;
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b1;
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
 			end 7: begin // NOP CKE / CKD
 				RCKE <= IS==6 || (RAMWR && IS==7);
-				nRCS <= 1'b1;
+				nRCS <= 1;
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b1;
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
 				SDOE <= 0;
-			end 8: begin // WR AP / NOP CKE (WR AP)
+			end 8: begin // WR AP CKE / NOP CKD (WR AP)
-				// NOP CKD / WR AP
 				RCKE <= IS==6 || (RAMWR && IS==7);
 				nRCS <= ~(IS==6 || (RAMWR && IS==7));
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b0;
+				nCAS <= 0;
-				nSWE <= 1'b0;
+				nSWE <= 0;
 				SDOE <= IS==6 || (RAMWR && IS==7);
 			end 9: begin // NOP CKE / NOP CKD
-				RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) || 
+				RCKE <= 1;
-					 (RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
+				nRCS <= 1;
-				nRCS <= 1'b1;
+				nRAS <= 1;
-				nRAS <= 1'b1;
+				nCAS <= 1;
-				nCAS <= 1'b1;
+				nSWE <= 1;
-				nSWE <= 1'b1;
 				SDOE <= 0;
-			end 10: begin // PC all / NOP CKD (PC all)
+			end 10: begin // PC all CKE / PC all CKD
-				RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
-					(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
+				nRCS <= 0;
-				nRCS <= ~((IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
+				nRAS <= 0;
-					(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7)));
+				nCAS <= 1;
-				nRAS <= 1'b0;
+				nSWE <= 0;
-				nCAS <= 1'b1;
-				nSWE <= 1'b0;
 				SDOE <= 0;
-			end 11: begin // AREF / NOP CKD (AREF)
+			end 11: begin // LDM CKE / AREF CKE / NOP CKD
-				RCKE <= RefReqd && (IS==4 || IS==5 || IS==6 || IS==7);
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
-				nRCS <= ~(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
+				nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
-				nRAS <= 1'b0;
+				nRAS <= 0;
-				nCAS <= 1'b0;
+				nCAS <= 0;
-				nSWE <= 1'b1;
+				nSWE <= ~(IS==1);
 				SDOE <= 0;
-			end 12: begin // NOP CKD
+			end default: begin // NOP CKD
-				RCKE <= 1'b0;
+				RCKE <= 0;
-				nRCS <= 1'b1;
+				nRCS <= 1;
-				nRAS <= 1'b1;
+				nRAS <= 1;
-				nCAS <= 1'b1;
+				nCAS <= 1;
-				nSWE <= 1'b1;
+				nSWE <= 1;
-				SDOE <= 0;
-			end 13: begin // NOP CKD
-				RCKE <= 1'b0;
-				nRCS <= 1'b1;
-				nRAS <= 1'b1;
-				nCAS <= 1'b1;
-				nSWE <= 1'b1;
-				SDOE <= 0;
-			end 14: begin // NOP CKD
-				RCKE <= 1'b0;
-				nRCS <= 1'b1;
-				nRAS <= 1'b1;
-				nCAS <= 1'b1;
-				nSWE <= 1'b1;
-				SDOE <= 0;
-			end 15: begin // NOP CKD
-				RCKE <= 1'b0;
-				nRCS <= 1'b1;
-				nRAS <= 1'b1;
-				nCAS <= 1'b1;
-				nSWE <= 1'b1;
 				SDOE <= 0;
 			end
 		endcase
 	end
+
+	/* SDRAM address */
 	output reg DQML = 1;
 	output reg DQMH = 1;
 	output reg [1:0] SBA;
@@ -452,24 +456,25 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 				if (IS==6) begin
 					SBA[1:0] <= { 2'b10 };
 					SA[12:0] <= { 10'b0011000100, LS[12:10] };
-				end else if (RAMSpecSELr) begin
+				end else if (RAMSpecSEL) begin
-					SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
-					SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]};
+					SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
+					SA[9:0] <= Addr[19:10];
 				end else begin
 					SBA[1:0] <= 2'b10;
-					SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
+					SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
 				end
 			end 2: begin // RD
-				if (RAMSpecSELr) begin
+				if (RAMSpecSEL) begin
-					SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
 					SA[12:0] <= { 4'b0011, Addr[9:1] };
 					DQML <= Addr[0];
 					DQMH <= ~Addr[0];
 				end else begin
 					SBA[1:0] <= 2'b10;
-					SA[12:0] <= { 4'b0011, RA[9:1]};
+					SA[12:0] <= { 4'b0011, RAr[9:1]};
-					DQML <= RA[0];
+					DQML <= RAr[0];
-					DQMH <= ~RA[0];
+					DQMH <= ~RAr[0];
 				end
 			end 3: begin // NOP CKE
 				DQML <= 1'b1;
@@ -503,7 +508,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 					DQML <= LS[0];
 					DQMH <= ~LS[0];
 				end else begin
-					SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
 					SA[12:0] <= { 4'b0011, Addr[9:1] };
 					DQML <= Addr[0];
 					DQMH <= ~Addr[0];
@@ -546,4 +551,18 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
 			end
 		endcase
 	end
+
+	/* DMA/INT in/out */
+	input INTin, DMAin;
+	output INTout = INTin;
+	output DMAout = DMAin;
+
+	/* Unused Pins */
+	output RAdir = 1;
+	output nDMAout = 1;
+	output nNMIout = 1;
+	output nINHout = 1;
+	output nRDYout = 1;
+	output nIRQout = 1;
+	output RWout = 1;
 endmodule

cpld/db/GR8RAM.asm.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161759471 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597731746 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:38 2021 " "Processing started: Sun Apr 11 13:22:38 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:31 2021 " "Processing started: Tue Sep 14 01:35:31 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618161760940 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1631597731986 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618161760971 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1631597731986 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:41 2021 " "Processing ended: Sun Apr 11 13:22:41 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618161761456 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing ended: Tue Sep 14 01:35:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1631597732146 ""}

cpld/db/GR8RAM.db_info

@@ -1,3 +0,0 @@
-Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-Version_Index = 302049280
-Creation_Time = Sun Apr 11 00:06:29 2021

cpld/db/GR8RAM.fit.qmsg

@@ -1,44 +1,38 @@
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618161749377 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1631597728526 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618161749440 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1631597728536 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618161749627 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618161749627 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618161750455 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1631597728726 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618161750486 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1631597728736 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618161750955 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1631597728876 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 69 " "No exact pin location assignment(s) for 1 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 82 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 356 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618161750971 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618161750971 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1631597729026 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618161751096 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1631597729036 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618161751096 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1631597729036 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618161751111 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618161751111 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         C25M " "   1.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI0 " "   1.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618161751111 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618161751127 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729046 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618161751127 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618161751143 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 418 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618161751205 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618161751205 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 350 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1631597729086 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618161751221 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618161751252 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618161751377 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618161751393 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618161751393 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729186 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618161751393 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1631597729306 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618161751408 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618161751408 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618161751408 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729566 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 26 12 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618161751424 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618161751424 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618161751424 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618161751424 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1631597729576 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "Ddir" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618161751455 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618161751455 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1631597730096 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161751455 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730096 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618161751674 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1631597730126 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161752080 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1631597730346 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1631597730346 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618161752111 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730656 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618161753690 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1631597730666 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161753690 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730666 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618161753752 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1631597730716 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618161754096 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618161754096 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1631597730776 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161754737 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "544 " "Peak virtual memory: 544 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:30 2021 " "Processing ended: Tue Sep 14 01:35:30 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1631597730806 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618161754737 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161754752 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618161754768 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618161754768 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618161754893 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:35 2021 " "Processing ended: Sun Apr 11 13:22:35 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618161755065 ""}

cpld/db/GR8RAM.hier_info

@@ -22,18 +22,6 @@ C25M => nCAS~reg0.CLK
 C25M => nRAS~reg0.CLK
 C25M => nRCS~reg0.CLK
 C25M => RCKE~reg0.CLK
-C25M => PS[0].CLK
-C25M => PS[1].CLK
-C25M => PS[2].CLK
-C25M => PS[3].CLK
-C25M => RDD[0].CLK
-C25M => RDD[1].CLK
-C25M => RDD[2].CLK
-C25M => RDD[3].CLK
-C25M => RDD[4].CLK
-C25M => RDD[5].CLK
-C25M => RDD[6].CLK
-C25M => RDD[7].CLK
 C25M => WRD[0].CLK
 C25M => WRD[1].CLK
 C25M => WRD[2].CLK
@@ -43,9 +31,10 @@ C25M => WRD[5].CLK
 C25M => WRD[6].CLK
 C25M => WRD[7].CLK
 C25M => MOSIout.CLK
+C25M => FCKOE.CLK
 C25M => MOSIOE.CLK
 C25M => FCS.CLK
-C25M => FCK~reg0.CLK
+C25M => FCKout.CLK
 C25M => Bank.CLK
 C25M => AddrIncH.CLK
 C25M => AddrIncM.CLK
@@ -74,8 +63,9 @@ C25M => Addr[20].CLK
 C25M => Addr[21].CLK
 C25M => Addr[22].CLK
 C25M => Addr[23].CLK
-C25M => REGEN.CLK
 C25M => IOROMEN.CLK
+C25M => nIOSTRBr.CLK
+C25M => REGEN.CLK
 C25M => nRESout~reg0.CLK
 C25M => LS[0].CLK
 C25M => LS[1].CLK
@@ -91,85 +81,86 @@ C25M => LS[10].CLK
 C25M => LS[11].CLK
 C25M => LS[12].CLK
 C25M => LS[13].CLK
+C25M => PS[0].CLK
+C25M => PS[1].CLK
+C25M => PS[2].CLK
+C25M => PS[3].CLK
+C25M => SetFWr[0].CLK
+C25M => SetFWr[1].CLK
+C25M => SetFWLoaded.CLK
 C25M => nRESr.CLK
-C25M => nRESr0.CLK
+C25M => nRESf[0].CLK
+C25M => nRESf[1].CLK
+C25M => nRESf[2].CLK
+C25M => nRESf[3].CLK
 C25M => PHI0r2.CLK
 C25M => PHI0r1.CLK
 C25M => IS~7.DATAIN
+C25M => RDD[0].CLK
+C25M => RDD[1].CLK
+C25M => RDD[2].CLK
+C25M => RDD[3].CLK
+C25M => RDD[4].CLK
+C25M => RDD[5].CLK
+C25M => RDD[6].CLK
+C25M => RDD[7].CLK
 PHI0 => comb.IN1
 PHI0 => nWEr.CLK
-PHI0 => RAMSpecSELr.CLK
+PHI0 => RAr[0].CLK
-PHI0 => ROMSpecSELr.CLK
+PHI0 => RAr[1].CLK
+PHI0 => RAr[2].CLK
+PHI0 => RAr[3].CLK
+PHI0 => RAr[4].CLK
+PHI0 => RAr[5].CLK
+PHI0 => RAr[6].CLK
+PHI0 => RAr[7].CLK
+PHI0 => RAr[8].CLK
+PHI0 => RAr[9].CLK
+PHI0 => RAr[10].CLK
+PHI0 => RAr[11].CLK
+PHI0 => CXXXr.CLK
 PHI0 => PHI0r1.DATAIN
-nRES => nRESr0.DATAIN
+nRES => nRESf[0].DATAIN
 nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nIOSEL => comb.IN0
+SetFW[0] => SetFWr[0].DATAIN
-nIOSEL => always5.IN1
+SetFW[1] => SetFWr[1].DATAIN
-nDEVSEL => comb.IN1
+INTin => INTout.DATAIN
-nDEVSEL => RAMSEL.IN1
+INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
-nDEVSEL => comb.IN1
+DMAin => DMAout.DATAIN
-nIOSTRB => comb.IN1
+DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
-nIOSTRB => always5.IN1
+nNMIout <= <VCC>
-SetFW[0] => Mux1.IN10
+nIRQout <= <VCC>
-SetFW[0] => Equal18.IN1
+nRDYout <= <VCC>
-SetFW[0] => Equal19.IN1
+nINHout <= <VCC>
-SetFW[1] => MOSIout.DATAB
+RWout <= <VCC>
-SetFW[1] => comb.IN1
+nDMAout <= <VCC>
-SetFW[1] => Equal18.IN0
+RA[0] => RAr[0].DATAIN
-SetFW[1] => Equal19.IN0
+RA[0] => Equal16.IN10
-RA[0] => DQML.DATAA
+RA[1] => RAr[1].DATAIN
-RA[0] => Equal6.IN3
+RA[1] => Equal16.IN9
-RA[0] => Equal9.IN1
+RA[2] => RAr[2].DATAIN
-RA[0] => Equal11.IN3
+RA[2] => Equal16.IN8
-RA[0] => Equal12.IN0
+RA[3] => RAr[3].DATAIN
-RA[0] => Equal13.IN3
+RA[3] => Equal16.IN7
-RA[0] => Equal14.IN10
+RA[4] => RAr[4].DATAIN
-RA[0] => DQMH.DATAA
+RA[4] => Equal16.IN6
-RA[1] => SA.DATAA
+RA[5] => RAr[5].DATAIN
-RA[1] => Equal6.IN2
+RA[5] => Equal16.IN5
-RA[1] => Equal9.IN0
+RA[6] => RAr[6].DATAIN
-RA[1] => Equal11.IN0
+RA[6] => Equal16.IN4
-RA[1] => Equal12.IN3
+RA[7] => RAr[7].DATAIN
-RA[1] => Equal13.IN2
+RA[7] => Equal16.IN3
-RA[1] => Equal14.IN9
+RA[8] => RAr[8].DATAIN
-RA[2] => SA.DATAA
+RA[8] => Equal16.IN2
-RA[2] => Equal6.IN1
+RA[9] => RAr[9].DATAIN
-RA[2] => Equal9.IN3
+RA[9] => Equal16.IN1
-RA[2] => Equal11.IN2
+RA[10] => RAr[10].DATAIN
-RA[2] => Equal12.IN2
+RA[10] => Equal16.IN0
-RA[2] => Equal13.IN1
+RA[11] => RAr[11].DATAIN
-RA[2] => Equal14.IN8
+RA[12] => Equal8.IN1
-RA[3] => SA.DATAA
+RA[13] => Equal8.IN0
-RA[3] => Equal6.IN0
+RA[14] => Equal8.IN3
-RA[3] => Equal9.IN2
+RA[15] => Equal8.IN2
-RA[3] => Equal11.IN1
-RA[3] => Equal12.IN1
-RA[3] => Equal13.IN0
-RA[3] => Equal14.IN7
-RA[4] => SA.DATAA
-RA[4] => Equal14.IN6
-RA[5] => SA.DATAA
-RA[5] => Equal14.IN5
-RA[6] => SA.DATAA
-RA[6] => Equal14.IN4
-RA[7] => comb.IN1
-RA[7] => SA.DATAA
-RA[7] => Equal14.IN3
-RA[8] => SA.DATAA
-RA[8] => Equal8.IN3
-RA[8] => Equal14.IN2
-RA[9] => SA.DATAA
-RA[9] => Equal8.IN2
-RA[9] => Equal14.IN1
-RA[10] => SA.DATAA
-RA[10] => Equal8.IN1
-RA[10] => Equal14.IN0
-RA[11] => SA.DATAA
-RA[11] => Equal8.IN0
-RA[12] => Equal7.IN3
-RA[13] => Equal7.IN2
-RA[14] => Equal7.IN1
-RA[15] => Equal7.IN0
 nWE => comb.IN1
 nWE => nWEr.DATAIN
 RD[0] <> RD[0]
@@ -180,7 +171,17 @@ RD[4] <> RD[4]
 RD[5] <> RD[5]
 RD[6] <> RD[6]
 RD[7] <> RD[7]
+RAdir <= <VCC>
 RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nIOSEL => comb.IN0
+nIOSEL => always7.IN1
+nDEVSEL => comb.IN1
+nDEVSEL => RAMSEL.IN1
+nDEVSEL => comb.IN1
+nDEVSEL => RAMRegSEL.IN1
+nIOSTRB => nIOSTRBr.DATAIN
+nIOSTRB => comb.IN1
+nIOSTRB => comb.IN1
 SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
@@ -211,8 +212,8 @@ SD[4] <> SD[4]
 SD[5] <> SD[5]
 SD[6] <> SD[6]
 SD[7] <> SD[7]
-nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
+nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
-FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
 MISO => WRD.DATAB
 MOSI <> MOSI
 

cpld/db/GR8RAM.map.qmsg

@@ -1,18 +1,19 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161736158 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597725836 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:15 2021 " "Processing started: Sun Apr 11 13:22:15 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:25 2021 " "Processing started: Tue Sep 14 01:35:25 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161737908 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597726126 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 110 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 286 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618161738314 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1631597726256 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738330 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618161740127 ""}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1631597726806 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618161740877 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RAdir"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1631597726986 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618161740986 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618161740986 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1631597727226 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618161741470 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1631597727256 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1631597727256 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:21 2021 " "Processing ended: Sun Apr 11 13:22:21 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1631597727336 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "422 " "Peak virtual memory: 422 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:27 2021 " "Processing ended: Tue Sep 14 01:35:27 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}

cpld/db/GR8RAM.rpp.qmsg

@@ -1,4 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616386555172 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616386555172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 00:15:54 2021 " "Processing started: Mon Mar 22 00:15:54 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616386555172 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555172 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom " "Command: quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555172 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "207 " "Peak virtual memory: 207 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 00:15:55 2021 " "Processing ended: Mon Mar 22 00:15:55 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555922 ""}

cpld/db/GR8RAM.sta.qmsg

@@ -1,23 +1,20 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161764909 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597733226 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:43 2021 " "Processing started: Sun Apr 11 13:22:43 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing started: Tue Sep 14 01:35:32 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618161765159 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1631597733306 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161765987 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597733426 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618161766331 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1631597733536 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618161766815 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1631597733876 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618161767003 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1631597733926 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618161767003 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1631597733926 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.419         0.000 C25M  " "   12.419         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618161767050 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.393         0.000 C25M  " "    1.393         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618161767331 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.300         0.000 C25M  " "   33.300         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -9.908      -697.920 C25M  " "   -9.908      -697.920 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.302        -1.302 PHI0  " "   -1.302        -1.302 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.146         0.000 C25M  " "    6.146         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.012         0.000 PHI0  " "    1.012         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.288         0.000 C25M  " "    1.288         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734         0.000 C25M  " "   19.734         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734         0.000 PHI0  " "  488.734         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.389      -131.670 C25M  " "   -4.389      -131.670 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1631597733996 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.835         0.000 C25M  " "    4.835         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 C25M  " "   -2.289        -2.289 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI0  " "   -2.289        -2.289 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618161767706 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:34 2021 " "Processing ended: Tue Sep 14 01:35:34 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:48 2021 " "Processing ended: Sun Apr 11 13:22:48 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""}

cpld/db/GR8RAM.tmw_info

@@ -1,6 +0,0 @@
-start_full_compilation:s:00:00:32
-start_analysis_synthesis:s:00:00:07-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:12-start_full_compilation
-start_assembler:s:00:00:06-start_full_compilation
-start_timing_analyzer:s:00:00:07-start_full_compilation

cpld/db/prev_cmp_GR8RAM.qmsg

@@ -1,99 +1,91 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618116856343 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049425619 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:16 2021 " "Processing started: Sun Apr 11 00:54:16 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:05 2021 " "Processing started: Wed Apr 21 19:57:05 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049425635 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618116858062 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049427276 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618116858250 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618116858250 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618116858250 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618116858250 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618116858344 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049427557 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427589 "|GR8RAM"}
-{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618116859969 ""}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049429167 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618116861047 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RAdir"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049429543 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618116861078 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618116861078 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049430027 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618116861313 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049430074 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049430074 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:21 2021 " "Processing ended: Sun Apr 11 00:54:21 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049430324 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618116865000 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:10 2021 " "Processing ended: Wed Apr 21 19:57:10 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116865016 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:23 2021 " "Processing started: Sun Apr 11 00:54:23 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116865016 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618116865016 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049433591 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618116865016 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:12 2021 " "Processing started: Wed Apr 21 19:57:12 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618116865219 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
-{ "Info" "0" "" "Project  = GR8RAM" {  } {  } 0 0 "Project  = GR8RAM" 0 0 "Fitter" 0 0 1618116865219 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619049433810 ""}
-{ "Info" "0" "" "Revision = GR8RAM" {  } {  } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618116865219 ""}
+{ "Info" "0" "" "Project  = GR8RAM" {  } {  } 0 0 "Project  = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618116865922 ""}
+{ "Info" "0" "" "Revision = GR8RAM" {  } {  } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618116865938 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049434576 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618116866110 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049434607 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618116866110 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618116866391 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618116866422 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049435826 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618116866766 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049435873 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 69 " "No exact pin location assignment(s) for 1 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 82 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 356 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618116866766 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618116866766 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049436217 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618116866938 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049436389 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618116866938 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049436436 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618116866954 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049436451 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         C25M " "   1.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000         PHI0 " "   1.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618116866954 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436467 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618116866969 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618116866985 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618116866985 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 350 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049436529 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618116866985 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049436592 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618116867032 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436654 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618116867110 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436670 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618116867126 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049436670 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618116867126 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049436670 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618116867126 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049436701 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618116867141 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049436967 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 26 12 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618116867141 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618116867141 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618116867141 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049437342 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "Ddir" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618116867188 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618116867188 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049437373 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116867188 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049438593 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618116867376 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049438593 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116867719 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049438686 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618116867751 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049439186 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049439186 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618116869157 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439702 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116869157 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049439718 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618116869204 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439718 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618116869595 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618116869595 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049439765 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116870251 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049440124 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618116870267 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:20 2021 " "Processing ended: Wed Apr 21 19:57:20 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049440312 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116870282 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1619049443282 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618116870329 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:22 2021 " "Processing started: Wed Apr 21 19:57:22 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618116870329 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618116870501 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049444797 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:30 2021 " "Processing ended: Sun Apr 11 00:54:30 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618116870720 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049444985 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618116872954 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:26 2021 " "Processing ended: Wed Apr 21 19:57:26 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049446001 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116872954 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:32 2021 " "Processing started: Sun Apr 11 00:54:32 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116872954 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618116872954 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1619049446923 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618116872954 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1619049449251 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618116874064 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:27 2021 " "Processing started: Wed Apr 21 19:57:27 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618116874079 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:34 2021 " "Processing ended: Sun Apr 11 00:54:34 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618116874548 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049449455 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618116875298 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049450502 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618116877189 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:36 2021 " "Processing started: Sun Apr 11 00:54:36 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049450877 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618116877408 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049451408 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618116878158 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049451564 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618116878314 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049451627 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618116878314 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.419         0.000 C25M  " "   12.419         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618116878502 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.393         0.000 C25M  " "    1.393         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618116879064 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.300         0.000 C25M  " "   33.300         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618116879220 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.146         0.000 C25M  " "    6.146         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734         0.000 C25M  " "   19.734         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734         0.000 PHI0  " "  488.734         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049451861 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618116879236 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451924 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618116879361 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451939 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -9.908      -697.920 C25M  " "   -9.908      -697.920 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.302        -1.302 PHI0  " "   -1.302        -1.302 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:32 2021 " "Processing ended: Wed Apr 21 19:57:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.012         0.000 PHI0  " "    1.012         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.288         0.000 C25M  " "    1.288         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049453283 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.389      -131.670 C25M  " "   -4.389      -131.670 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.835         0.000 C25M  " "    4.835         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 C25M  " "   -2.289        -2.289 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289        -2.289 PHI0  " "   -2.289        -2.289 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618116879611 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618116879705 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618116879705 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:39 2021 " "Processing ended: Sun Apr 11 00:54:39 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116880814 ""}

cpld/output_files/GR8RAM.asm.rpt

@@ -1,6 +1,6 @@
 Assembler report for GR8RAM
-Sun Apr 11 13:22:41 2021
+Tue Sep 14 01:35:32 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
+  5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
   6. Assembler Messages
 
 
@@ -37,7 +37,7 @@ applicable agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Sun Apr 11 13:22:41 2021 ;
+; Assembler Status      ; Successful - Tue Sep 14 01:35:32 2021 ;
 ; Revision Name         ; GR8RAM                                ;
 ; Top-level Entity Name ; GR8RAM                                ;
 ; Family                ; MAX II                                ;
@@ -75,40 +75,40 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+-----------+---------------+
 
 
-+----------------------------------------------+
++-------------------------------------------------------------------+
-; Assembler Generated Files                    ;
+; Assembler Generated Files                                         ;
-+----------------------------------------------+
++-------------------------------------------------------------------+
-; File Name                                    ;
+; File Name                                                         ;
-+----------------------------------------------+
++-------------------------------------------------------------------+
-; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+----------------------------------------------+
++-------------------------------------------------------------------+
 
 
-+------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------+
-; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+; Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+----------------+-------------------------------------------------------+
++----------------+----------------------------------------------------------------------------+
-; Option         ; Setting                                               ;
+; Option         ; Setting                                                                    ;
-+----------------+-------------------------------------------------------+
++----------------+----------------------------------------------------------------------------+
-; Device         ; EPM240T100C5                                          ;
+; Device         ; EPM240T100C5                                                               ;
-; JTAG usercode  ; 0x00162982                                            ;
+; JTAG usercode  ; 0x00161CF0                                                                 ;
-; Checksum       ; 0x00162E02                                            ;
+; Checksum       ; 0x001620E8                                                                 ;
-+----------------+-------------------------------------------------------+
++----------------+----------------------------------------------------------------------------+
 
 
 +--------------------+
 ; Assembler Messages ;
 +--------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
+Info: Running Quartus II 64-Bit Assembler
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Sun Apr 11 13:22:38 2021
+    Info: Processing started: Tue Sep 14 01:35:31 2021
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 293 megabytes
+    Info: Peak virtual memory: 381 megabytes
-    Info: Processing ended: Sun Apr 11 13:22:41 2021
+    Info: Processing ended: Tue Sep 14 01:35:32 2021
-    Info: Elapsed time: 00:00:03
+    Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:03
+    Info: Total CPU time (on all processors): 00:00:01
 
 

cpld/output_files/GR8RAM.cdf

@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Vfy)
+		Device PartName(EPM240T100) Path("C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(2) SEC_Device(EPM240T100) Child_OpMask(2 2 2));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;

cpld/output_files/GR8RAM.done

@@ -1 +1 @@
-Sun Apr 11 13:22:49 2021
+Tue Sep 14 01:35:34 2021

cpld/output_files/GR8RAM.fit.summary

@@ -1,11 +1,11 @@
-Fitter Status : Successful - Sun Apr 11 13:22:34 2021
+Fitter Status : Successful - Tue Sep 14 01:35:30 2021
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX II
 Device : EPM240T100C5
 Timing Models : Final
-Total logic elements : 227 / 240 ( 95 % )
+Total logic elements : 234 / 240 ( 98 % )
-Total pins : 69 / 80 ( 86 % )
+Total pins : 80 / 80 ( 100 % )
 Total virtual pins : 0
 UFM blocks : 0 / 1 ( 0 % )

cpld/output_files/GR8RAM.flow.rpt

@@ -1,6 +1,6 @@
 Flow report for GR8RAM
-Sun Apr 11 13:22:47 2021
+Tue Sep 14 01:35:34 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -40,15 +40,15 @@ applicable agreement for further details.
 +-----------------------------------------------------------------------------+
 ; Flow Summary                                                                ;
 +---------------------------+-------------------------------------------------+
-; Flow Status               ; Successful - Sun Apr 11 13:22:41 2021           ;
+; Flow Status               ; Successful - Tue Sep 14 01:35:32 2021           ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
 ; Revision Name             ; GR8RAM                                          ;
 ; Top-level Entity Name     ; GR8RAM                                          ;
 ; Family                    ; MAX II                                          ;
 ; Device                    ; EPM240T100C5                                    ;
 ; Timing Models             ; Final                                           ;
-; Total logic elements      ; 227 / 240 ( 95 % )                              ;
+; Total logic elements      ; 234 / 240 ( 98 % )                              ;
-; Total pins                ; 69 / 80 ( 86 % )                                ;
+; Total pins                ; 80 / 80 ( 100 % )                               ;
 ; Total virtual pins        ; 0                                               ;
 ; UFM blocks                ; 0 / 1 ( 0 % )                                   ;
 +---------------------------+-------------------------------------------------+
@@ -59,42 +59,42 @@ applicable agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 04/11/2021 13:22:17 ;
+; Start date & time ; 09/14/2021 01:35:26 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; GR8RAM              ;
 +-------------------+---------------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                            ;
+; Flow Non-Default Global Settings                                                                                          ;
-+-------------------------------------------------+--------------------------------+---------------+-------------+------------+
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
-; Assignment Name                                 ; Value                          ; Default Value ; Entity Name ; Section Id ;
+; Assignment Name                                 ; Value                        ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------------------+--------------------------------+---------------+-------------+------------+
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
-; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP             ; On                             ; Off           ; --          ; --         ;
+; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP             ; On                           ; Off           ; --          ; --         ;
-; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always                         ; Auto          ; --          ; --         ;
+; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always                       ; Auto          ; --          ; --         ;
-; ALM_REGISTER_PACKING_EFFORT                     ; High                           ; Medium        ; --          ; --         ;
+; ALM_REGISTER_PACKING_EFFORT                     ; High                         ; Medium        ; --          ; --         ;
-; AUTO_PACKED_REGISTERS_MAXII                     ; Minimize Area                  ; Auto          ; --          ; --         ;
+; AUTO_PACKED_REGISTERS_MAXII                     ; Minimize Area                ; Auto          ; --          ; --         ;
-; AUTO_RESOURCE_SHARING                           ; On                             ; Off           ; --          ; --         ;
+; AUTO_RESOURCE_SHARING                           ; On                           ; Off           ; --          ; --         ;
-; COMPILER_SIGNATURE_ID                           ; 44085571633675.161816173700648 ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                           ; 962837114763.163159772501756 ; --            ; --          ; --         ;
-; FINAL_PLACEMENT_OPTIMIZATION                    ; Always                         ; Automatically ; --          ; --         ;
+; FINAL_PLACEMENT_OPTIMIZATION                    ; Always                       ; Automatically ; --          ; --         ;
-; FITTER_EFFORT                                   ; Standard Fit                   ; Auto Fit      ; --          ; --         ;
+; FITTER_EFFORT                                   ; Standard Fit                 ; Auto Fit      ; --          ; --         ;
-; IOBANK_VCCIO                                    ; 3.3V                           ; --            ; --          ; 1          ;
+; IOBANK_VCCIO                                    ; 3.3V                         ; --            ; --          ; 1          ;
-; IOBANK_VCCIO                                    ; 3.3V                           ; --            ; --          ; 2          ;
+; IOBANK_VCCIO                                    ; 3.3V                         ; --            ; --          ; 2          ;
-; MAXII_OPTIMIZATION_TECHNIQUE                    ; Area                           ; Balanced      ; --          ; --         ;
+; MAXII_OPTIMIZATION_TECHNIQUE                    ; Area                         ; Balanced      ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                          ; 85                             ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                          ; 85                           ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                          ; 0                              ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                          ; 0                            ; --            ; --          ; --         ;
-; MUX_RESTRUCTURE                                 ; On                             ; Auto          ; --          ; --         ;
+; MUX_RESTRUCTURE                                 ; On                           ; Auto          ; --          ; --         ;
-; PLACEMENT_EFFORT_MULTIPLIER                     ; 2.0                            ; 1.0           ; --          ; --         ;
+; PLACEMENT_EFFORT_MULTIPLIER                     ; 2.0                          ; 1.0           ; --          ; --         ;
-; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR           ; 3.3V                           ; --            ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR           ; 3.3V                         ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY                        ; output_files                   ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY                        ; output_files                 ; --            ; --          ; --         ;
-; REMOVE_REDUNDANT_LOGIC_CELLS                    ; On                             ; Off           ; --          ; --         ;
+; REMOVE_REDUNDANT_LOGIC_CELLS                    ; On                           ; Off           ; --          ; --         ;
-; ROUTER_EFFORT_MULTIPLIER                        ; 2.0                            ; 1.0           ; --          ; --         ;
+; ROUTER_EFFORT_MULTIPLIER                        ; 2.0                          ; 1.0           ; --          ; --         ;
-; ROUTER_REGISTER_DUPLICATION                     ; Off                            ; Auto          ; --          ; --         ;
+; ROUTER_REGISTER_DUPLICATION                     ; Off                          ; Auto          ; --          ; --         ;
-; SEED                                            ; 235                            ; 1             ; --          ; --         ;
+; SEED                                            ; 235                          ; 1             ; --          ; --         ;
-; STATE_MACHINE_PROCESSING                        ; Minimal Bits                   ; Auto          ; --          ; --         ;
+; STATE_MACHINE_PROCESSING                        ; Minimal Bits                 ; Auto          ; --          ; --         ;
-; SYNTHESIS_SEED                                  ; 123                            ; 1             ; --          ; --         ;
+; SYNTHESIS_SEED                                  ; 123                          ; 1             ; --          ; --         ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS                   ; Off                            ; --            ; --          ; --         ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS                   ; Off                          ; --            ; --          ; --         ;
-+-------------------------------------------------+--------------------------------+---------------+-------------+------------+
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
 
 
 +-------------------------------------------------------------------------------------------------------------------------------+
@@ -102,24 +102,24 @@ applicable agreement for further details.
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:06     ; 1.0                     ; 301 MB              ; 00:00:06                           ;
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 422 MB              ; 00:00:01                           ;
-; Fitter                    ; 00:00:10     ; 1.4                     ; 382 MB              ; 00:00:09                           ;
+; Fitter                    ; 00:00:02     ; 1.0                     ; 544 MB              ; 00:00:02                           ;
-; Assembler                 ; 00:00:03     ; 1.0                     ; 292 MB              ; 00:00:03                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 381 MB              ; 00:00:01                           ;
-; TimeQuest Timing Analyzer ; 00:00:04     ; 1.0                     ; 278 MB              ; 00:00:04                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 374 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:23     ; --                      ; --                  ; 00:00:22                           ;
+; Total                     ; 00:00:07     ; --                      ; --                  ; 00:00:05                           ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
-+-----------------------------------------------------------------------------------------+
++----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                         ;
+; Flow OS Summary                                                                        ;
-+---------------------------+------------------+------------+------------+----------------+
++---------------------------+------------------+-----------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
++---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis      ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
+; Analysis & Synthesis      ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Fitter                    ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
+; Fitter                    ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Assembler                 ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
+; Assembler                 ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; TimeQuest Timing Analyzer ; zane-c8bbf8aef2  ; Windows XP ; 5.1        ; i686           ;
+; TimeQuest Timing Analyzer ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-+---------------------------+------------------+------------+------------+----------------+
++---------------------------+------------------+-----------+------------+----------------+
 
 
 ------------

cpld/output_files/GR8RAM.jdi

@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="a474eff98051f7f4d66b"/>
+    <hash md5_digest_80b="5cae6640443712869b47"/>
   </project>
   <file_info>
     <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>

cpld/output_files/GR8RAM.map.rpt

@@ -1,6 +1,6 @@
 Analysis & Synthesis report for GR8RAM
-Sun Apr 11 13:22:21 2021
+Tue Sep 14 01:35:27 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 
 
 ---------------------
@@ -45,13 +45,13 @@ applicable agreement for further details.
 +-------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                  ;
 +-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sun Apr 11 13:22:21 2021           ;
+; Analysis & Synthesis Status ; Successful - Tue Sep 14 01:35:27 2021           ;
-; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
 ; Revision Name               ; GR8RAM                                          ;
 ; Top-level Entity Name       ; GR8RAM                                          ;
 ; Family                      ; MAX II                                          ;
-; Total logic elements        ; 240                                             ;
+; Total logic elements        ; 257                                             ;
-; Total pins                  ; 69                                              ;
+; Total pins                  ; 80                                              ;
 ; Total virtual pins          ; 0                                               ;
 ; UFM blocks                  ; 0 / 1 ( 0 % )                                   ;
 +-----------------------------+-------------------------------------------------+
@@ -130,30 +130,24 @@ applicable agreement for further details.
 +----------------------------------------------------------------------------+--------------------+--------------------+
 
 
-+------------------------------------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-; Parallel Compilation                     ;
++-------------------------------------+
-+----------------------------+-------------+
+; Parallel Compilation                ;
-; Processors                 ; Number      ;
++----------------------------+--------+
-+----------------------------+-------------+
+; Processors                 ; Number ;
-; Number detected on machine ; 2           ;
++----------------------------+--------+
-; Maximum allowed            ; 2           ;
+; Number detected on machine ; 12     ;
-;                            ;             ;
+; Maximum allowed            ; 1      ;
-; Average used               ; 1.00        ;
++----------------------------+--------+
-; Maximum used               ; 1           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-+----------------------------+-------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                ;
+; Analysis & Synthesis Source Files Read                                                                                                     ;
-+----------------------------------+-----------------+------------------------+-------------------------------+---------+
++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path  ; Library ;
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                       ; Library ;
-+----------------------------------+-----------------+------------------------+-------------------------------+---------+
++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
-; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ;         ;
+; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ;         ;
-+----------------------------------+-----------------+------------------------+-------------------------------+---------+
++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
 
 
 +-----------------------------------------------------+
@@ -161,33 +155,33 @@ applicable agreement for further details.
 +---------------------------------------------+-------+
 ; Resource                                    ; Usage ;
 +---------------------------------------------+-------+
-; Total logic elements                        ; 240   ;
+; Total logic elements                        ; 257   ;
-;     -- Combinational with no register       ; 138   ;
+;     -- Combinational with no register       ; 136   ;
-;     -- Register only                        ; 14    ;
+;     -- Register only                        ; 24    ;
-;     -- Combinational with a register        ; 88    ;
+;     -- Combinational with a register        ; 97    ;
 ;                                             ;       ;
 ; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 130   ;
+;     -- 4 input functions                    ; 126   ;
-;     -- 3 input functions                    ; 30    ;
+;     -- 3 input functions                    ; 41    ;
-;     -- 2 input functions                    ; 66    ;
+;     -- 2 input functions                    ; 65    ;
 ;     -- 1 input functions                    ; 0     ;
-;     -- 0 input functions                    ; 0     ;
+;     -- 0 input functions                    ; 1     ;
 ;                                             ;       ;
 ; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 207   ;
+;     -- normal mode                          ; 224   ;
 ;     -- arithmetic mode                      ; 33    ;
 ;     -- qfbk mode                            ; 0     ;
 ;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 35    ;
+;     -- synchronous clear/load mode          ; 45    ;
-;     -- asynchronous clear/load mode         ; 30    ;
+;     -- asynchronous clear/load mode         ; 29    ;
 ;                                             ;       ;
-; Total registers                             ; 102   ;
+; Total registers                             ; 121   ;
 ; Total logic cells in carry chains           ; 37    ;
-; I/O pins                                    ; 69    ;
+; I/O pins                                    ; 80    ;
 ; Maximum fan-out node                        ; C25M  ;
-; Maximum fan-out                             ; 99    ;
+; Maximum fan-out                             ; 107   ;
-; Total fan-out                               ; 1036  ;
+; Total fan-out                               ; 1095  ;
-; Average fan-out                             ; 3.35  ;
+; Average fan-out                             ; 3.25  ;
 +---------------------------------------------+-------+
 
 
@@ -196,7 +190,7 @@ applicable agreement for further details.
 +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
 ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
 +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
-; |GR8RAM                    ; 240 (240)   ; 102          ; 0          ; 69   ; 0            ; 138 (138)    ; 14 (14)           ; 88 (88)          ; 37 (37)         ; 0 (0)      ; |GR8RAM             ; work         ;
+; |GR8RAM                    ; 257 (257)   ; 121          ; 0          ; 80   ; 0            ; 136 (136)    ; 24 (24)           ; 97 (97)          ; 37 (37)         ; 0 (0)      ; |GR8RAM             ; work         ;
 +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
@@ -231,12 +225,12 @@ Encoding Type:  Minimal Bits
 +----------------------------------------------+-------+
 ; Statistic                                    ; Value ;
 +----------------------------------------------+-------+
-; Total registers                              ; 102   ;
+; Total registers                              ; 121   ;
-; Number of registers using Synchronous Clear  ; 10    ;
+; Number of registers using Synchronous Clear  ; 12    ;
-; Number of registers using Synchronous Load   ; 25    ;
+; Number of registers using Synchronous Load   ; 33    ;
-; Number of registers using Asynchronous Clear ; 30    ;
+; Number of registers using Asynchronous Clear ; 29    ;
 ; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 29    ;
+; Number of registers using Clock Enable       ; 24    ;
 ; Number of registers using Preset             ; 0     ;
 +----------------------------------------------+-------+
 
@@ -262,12 +256,11 @@ Encoding Type:  Minimal Bits
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
 ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|PS[1]              ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|PS[2]              ;
-; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|SA[12]~reg0        ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|SA[11]~reg0        ;
 ; 20:1               ; 6 bits    ; 78 LEs        ; 24 LEs               ; 54 LEs                 ; Yes        ; |GR8RAM|SA[3]~reg0         ;
 ; 20:1               ; 3 bits    ; 39 LEs        ; 18 LEs               ; 21 LEs                 ; Yes        ; |GR8RAM|SA[1]~reg0         ;
-; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |GR8RAM|WRD[0]             ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |GR8RAM|WRD[7]             ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|WRD[7]             ;
 ; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|RDD[1]             ;
 ; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|RDD[4]             ;
 ; 18:1               ; 2 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |GR8RAM|DQMH~reg0          ;
@@ -279,37 +272,45 @@ Encoding Type:  Minimal Bits
 ; Analysis & Synthesis Messages ;
 +-------------------------------+
 Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
+Info: Running Quartus II 64-Bit Analysis & Synthesis
     Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Sun Apr 11 13:22:15 2021
+    Info: Processing started: Tue Sep 14 01:35:25 2021
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Warning (20028): Parallel compilation is not licensed and has been disabled
 Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
     Info (12023): Found entity 1: GR8RAM
 Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)
 Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "nNMIout" is stuck at VCC
+    Warning (13410): Pin "nIRQout" is stuck at VCC
+    Warning (13410): Pin "nRDYout" is stuck at VCC
+    Warning (13410): Pin "nINHout" is stuck at VCC
+    Warning (13410): Pin "RWout" is stuck at VCC
+    Warning (13410): Pin "nDMAout" is stuck at VCC
+    Warning (13410): Pin "RAdir" is stuck at VCC
 Info (17049): 1 registers lost all their fanouts during netlist optimizations.
-Info (21057): Implemented 309 device resources after synthesis - the final resource count might be different
+Info (21057): Implemented 337 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 26 input pins
+    Info (21058): Implemented 28 input pins
-    Info (21059): Implemented 26 output pins
+    Info (21059): Implemented 35 output pins
     Info (21060): Implemented 17 bidirectional pins
-    Info (21061): Implemented 240 logic cells
+    Info (21061): Implemented 257 logic cells
-Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
+Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings
-    Info: Peak virtual memory: 301 megabytes
+    Info: Peak virtual memory: 422 megabytes
-    Info: Processing ended: Sun Apr 11 13:22:21 2021
+    Info: Processing ended: Tue Sep 14 01:35:27 2021
-    Info: Elapsed time: 00:00:06
+    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:06
+    Info: Total CPU time (on all processors): 00:00:01
 
 
 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
+The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
 
 

cpld/output_files/GR8RAM.map.smsg

@@ -1,2 +1,2 @@
-Warning (10273): Verilog HDL warning at GR8RAM.v(79): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z"
-Warning (10273): Verilog HDL warning at GR8RAM.v(256): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z"

cpld/output_files/GR8RAM.map.summary

@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Sun Apr 11 13:22:21 2021
+Analysis & Synthesis Status : Successful - Tue Sep 14 01:35:27 2021
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX II
-Total logic elements : 240
+Total logic elements : 257
-Total pins : 69
+Total pins : 80
 Total virtual pins : 0
 UFM blocks : 0 / 1 ( 0 % )

cpld/output_files/GR8RAM.pin

@@ -57,7 +57,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
 CHIP  "GR8RAM"  ASSIGNED TO AN: EPM240T100C5
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
@@ -78,39 +78,39 @@ VCCINT                       : 13        : power  :                   : 2.5V/3.3
 RA[10]                       : 14        : input  : 3.3-V LVTTL       :         : 1         : Y              
 MOSI                         : 15        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 MISO                         : 16        : input  : 3.3-V LVTTL       :         : 1         : Y              
-RDdir                        : 17        : output : 3.3-V LVTTL       :         : 1         : N              
+RDdir                        : 17        : output : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 18        :        :                   :         : 1         :                
+DMAout                       : 18        : output : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 19        :        :                   :         : 1         :                
+RAdir                        : 19        : output : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 20        :        :                   :         : 1         :                
+INTout                       : 20        : output : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 21        :        :                   :         : 1         :                
+nDMAout                      : 21        : output : 3.3-V LVTTL       :         : 1         : Y              
 TMS                          : 22        : input  :                   :         : 1         :                
 TDI                          : 23        : input  :                   :         : 1         :                
 TCK                          : 24        : input  :                   :         : 1         :                
 TDO                          : 25        : output :                   :         : 1         :                
-GND*                         : 26        :        :                   :         : 1         :                
+nNMIout                      : 26        : output : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 27        :        :                   :         : 1         :                
+nINHout                      : 27        : output : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 28        :        :                   :         : 1         :                
+nRDYout                      : 28        : output : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 29        :        :                   :         : 1         :                
+nIRQout                      : 29        : output : 3.3-V LVTTL       :         : 1         : Y              
 nRESout                      : 30        : output : 3.3-V LVTTL       :         : 1         : Y              
 VCCIO1                       : 31        : power  :                   : 3.3V    : 1         :                
 GNDIO                        : 32        : gnd    :                   :         :           :                
-GND*                         : 33        :        :                   :         : 1         :                
+RWout                        : 33        : output : 3.3-V LVTTL       :         : 1         : Y              
 RA[11]                       : 34        : input  : 3.3-V LVTTL       :         : 1         : Y              
 RA[12]                       : 35        : input  : 3.3-V LVTTL       :         : 1         : Y              
 RA[13]                       : 36        : input  : 3.3-V LVTTL       :         : 1         : Y              
 RA[14]                       : 37        : input  : 3.3-V LVTTL       :         : 1         : Y              
 RA[15]                       : 38        : input  : 3.3-V LVTTL       :         : 1         : Y              
-nIOSEL                       : 39        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nIOSEL                       : 39        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
-nDEVSEL                      : 40        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nDEVSEL                      : 40        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
-PHI0                         : 41        : input  : 3.3-V LVTTL       :         : 1         : Y              
+PHI0                         : 41        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
-nIOSTRB                      : 42        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nIOSTRB                      : 42        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
-nWE                          : 43        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nWE                          : 43        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
-nRES                         : 44        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nRES                         : 44        : input  : 3.3V Schmitt Trigger Input :         : 1         : Y              
 VCCIO1                       : 45        : power  :                   : 3.3V    : 1         :                
 GNDIO                        : 46        : gnd    :                   :         :           :                
 SD[1]                        : 47        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 48        :        :                   :         : 1         :                
+DMAin                        : 48        : input  : 3.3-V LVTTL       :         : 1         : Y              
-GND*                         : 49        :        :                   :         : 1         :                
+INTin                        : 49        : input  : 3.3-V LVTTL       :         : 1         : Y              
 SD[0]                        : 50        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 SD[4]                        : 51        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 SD[5]                        : 52        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
@@ -156,8 +156,8 @@ RD[5]                        : 91        : bidir  : 3.3-V LVTTL       :
 RD[6]                        : 92        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 GNDIO                        : 93        : gnd    :                   :         :           :                
 VCCIO2                       : 94        : power  :                   : 3.3V    : 2         :                
-SetFW[1]                     : 95        : input  : 3.3-V LVTTL       :         : 2         : Y              
+SetFW[1]                     : 95        : input  : 3.3V Schmitt Trigger Input :         : 2         : Y              
-SetFW[0]                     : 96        : input  : 3.3-V LVTTL       :         : 2         : Y              
+SetFW[0]                     : 96        : input  : 3.3V Schmitt Trigger Input :         : 2         : Y              
 RA[2]                        : 97        : input  : 3.3-V LVTTL       :         : 2         : Y              
 RA[1]                        : 98        : input  : 3.3-V LVTTL       :         : 2         : Y              
 RD[7]                        : 99        : bidir  : 3.3-V LVTTL       :         : 2         : Y