B.1.0?

This reverts commit 5db5490f52.

.gitignore

@@ -6,6 +6,7 @@
 *.bak
 *.bck
 *.kicad_pcb-bak
+*.sch-bak
 *~
 _autosave-*
 *.tmp
@@ -21,8 +22,16 @@ fp-info-cache
 *.dsn
 *.ses
 
-# Exported BOM files
-*.xml
-*.csv
-
 *.DS_Store
+*.kicad_prl
+
+CPLD/MAXII/db/*
+CPLD/MAXII/incremental_db/*
+CPLD/MAXII/GR8RAM.qws
+CPLD/MAXV/db/*
+CPLD/MAXV/incremental_db/*
+CPLD/MAXV/GR8RAM.qws
+
+/Hardware/MAX/GR8RAM-backups/*
+/Hardware/LCMXO2/GR8RAM-backups/*
+*.lck

CPLD/GR8RAM-old.v

@@ -0,0 +1,568 @@
+module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
+			  INTin, INTout, DMAin, DMAout, 
+			  nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
+			  RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
+			  SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
+			  nFCS, FCK, MISO, MOSI);
+
+	/* Clock signals */
+	input C25M, PHI0;
+	reg PHI0r1, PHI0r2;
+	always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
+	
+	/* Reset filter */
+	input nRES;
+	reg [3:0] nRESf = 0;
+	reg nRESr = 0;
+	always @(posedge C25M) begin 
+		nRESf[3:0] <= { nRESf[2:0], nRES };
+		nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
+	end
+
+	/* Firmware select */
+	input [1:0] SetFW;
+	reg [1:0] SetFWr;
+	reg SetFWLoaded = 0;
+	always @(posedge C25M) begin
+		if (!SetFWLoaded) begin
+			SetFWLoaded <= 1;
+			SetFWr[1:0] <= SetFW[1:0];
+		end
+	end
+	wire [1:0] SetROM = ~SetFWr[1:0];
+	wire SetEN16MB = SetROM[1:0]==2'b11;
+	wire SetEN24bit = SetROM[1];
+
+	/* State counter from PHI0 rising edge */
+	reg [3:0] PS = 0;
+	wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
+	always @(posedge C25M) begin
+		if (PSStart) PS <= 1;
+		else if (PS==0) PS <= 0;
+		else PS <= PS+1;
+	end
+
+	/* Long state counter: counts from 0 to $3FFF */
+	reg [13:0] LS = 0;
+	always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
+
+	/* Init state */
+	output reg nRESout = 0;
+	reg [2:0] IS = 0;
+	always @(posedge C25M) begin
+		if (IS==7) nRESout <= 1;
+		else if (PS==15) begin
+			if (LS==14'h1FCE) IS <= 1; // PC all + load mode
+			else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
+			else if (LS==14'h1FFA) IS <= 5; // SPI flash command
+			else if (LS==14'h1FFF) IS <= 6; // Flash load driver
+			else if (LS==14'h3FFF) IS <= 7; // Operating mode
+		end
+	end
+
+	/* Apple IO area select signals */
+	input nIOSEL, nDEVSEL, nIOSTRB;
+
+	/* Apple address bus */
+	input [15:0] RA; input nWE;
+	reg   [11:0] RAr; reg nWEr;
+	reg CXXXr;
+	always @(posedge PHI0) begin
+		CXXXr <= RA[15:12]==4'hC;
+		RAr[11:0] <= RA[11:0];
+		nWEr <= nWE;
+	end
+
+	/* Apple select signals */
+	wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11]));
+	wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
+	wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
+	wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
+	wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]);
+	wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
+	wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
+	wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
+	wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL;
+	wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL;
+	wire RAMSEL = !nDEVSEL && RAMSpecSEL;
+	wire RAMWR = RAMSEL && !nWEr;
+	wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL;
+	wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL;
+	wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL;
+	
+	/* IOROMEN and REGEN control */
+	reg IOROMEN = 0;
+	reg REGEN = 0;
+	reg nIOSTRBr;
+	wire IOROMRES = RAr[10:0]==11'h7FF && !nIOSTRB && !nIOSTRBr;
+	always @(posedge C25M, negedge nRESr) begin
+		if (!nRESr) REGEN <= 0;
+		else if (PS==8 && !nIOSEL) REGEN <= 1;
+	end
+	always @(posedge C25M) begin
+		nIOSTRBr <= nIOSTRB;
+		if (!nRESr) IOROMEN <= 0;
+		else if (PS==8 && IOROMRES) IOROMEN <= 0;
+		else if (PS==8 && !nIOSEL) IOROMEN <= 1;
+	end
+
+	/* Apple data bus */
+	inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
+	reg [7:0] RDD;
+	output RDdir = !(PHI0r2 && nWE && PHI0 &&
+		(!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
+
+	/* Slinky address registers */
+	reg [23:0] Addr = 0;
+	reg AddrIncL = 0;
+	reg AddrIncM = 0;
+	reg AddrIncH = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (!nRESr) begin
+			Addr[23:0] <= 24'h000000;
+			AddrIncL <= 0;
+			AddrIncM <= 0;
+			AddrIncH <= 0;
+		end else begin
+			if (PS==8 && RAMRegSEL) AddrIncL <= 1;
+			else AddrIncL <= 0;
+
+			if (PS==8 && AddrLSEL && !nWEr) begin
+				Addr[7:0] <= RD[7:0];
+				AddrIncM <= Addr[7] && !RD[7];
+			end else if (AddrIncL) begin
+				Addr[7:0] <= Addr[7:0]+1;
+				AddrIncM <= Addr[7:0]==8'hFF;
+			end else AddrIncM <= 0;
+
+			if (PS==8 && AddrMSEL && !nWEr) begin
+				Addr[15:8] <= RD[7:0];
+				AddrIncH <= Addr[15] && !RD[7];
+			end else if (AddrIncM) begin
+				Addr[15:8] <= Addr[15:8]+1;
+				AddrIncH <= Addr[15:8]==8'hFF;
+			end else AddrIncH <= 0;
+
+			if (PS==8 && AddrHSEL && !nWEr) begin
+				Addr[23:16] <= RD[7:0];
+			end else if (AddrIncH) begin
+				Addr[23:16] <= Addr[23:16]+1;
+			end
+		end
+	end
+
+	/* ROM bank register */
+	reg Bank = 0;
+	always @(posedge C25M, negedge nRESr) begin
+		if (!nRESr) Bank <= 0;
+		else if (PS==8 && BankSEL && !nWEr) begin
+			Bank <= RD[0];
+		end
+	end
+
+	/* SPI flash control signals */
+	output nFCS = FCKOE ? !FCS : 1'bZ;
+	reg FCS = 0;
+	output FCK = FCKOE ? FCKout : 1'bZ;
+	reg FCKOE = 0;
+	reg FCKout = 0;
+	inout MOSI = MOSIOE ? MOSIout : 1'bZ;
+	reg MOSIOE = 0;
+	input MISO;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 1: begin // ACT
+				FCKout <= !(IS==5 || IS==6);
+			end 2: begin // RD
+				FCKout <= 1'b1;
+			end 3: begin // NOP CKE
+				FCKout <= !(IS==5 || IS==6);
+			end 4: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 5: begin // NOP CKE
+				FCKout <= !(IS==5 || IS==6);
+			end 6: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 7: begin // NOP CKE
+				FCKout <= !(IS==5 || IS==6);
+			end 8: begin // WR AP
+				FCKout <= 1'b1;
+			end 9: begin // NOP CKE
+				FCKout <= !(IS==5);
+			end 10: begin // PC all
+				FCKout <= 1'b1;
+			end 11: begin // AREF
+				FCKout <= !(IS==5);
+			end 12: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 13: begin // NOP CKE
+				FCKout <= !(IS==5);
+			end 14: begin // NOP CKE
+				FCKout <= 1'b1;
+			end 15: begin // NOP CKE
+				FCKout <= !(IS==5);
+			end
+		endcase
+		FCS <= IS==4 || IS==5 || IS==6;
+		MOSIOE <= IS==5;
+		FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
+	end
+
+	/* SPI flash MOSI control */
+	reg MOSIout = 0;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			1: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 7
+					3'h4: MOSIout <= 1'b0; // Address bit 23
+					3'h5: MOSIout <= 1'b0; // Address bit 15
+					3'h6: MOSIout <= 1'b0; // Address bit 7
+					default MOSIout <= 1'b0;
+				endcase
+			end 3: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 6
+					3'h4: MOSIout <= 1'b0; // Address bit 22
+					3'h5: MOSIout <= SetROM[1]; // Address bit 14
+					3'h6: MOSIout <= 1'b0; // Address bit 6
+					default MOSIout <= 1'b0;
+				endcase
+			end 5: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 5
+					3'h4: MOSIout <= 1'b0; // Address bit 21
+					3'h5: MOSIout <= SetROM[0]; // Address bit 13
+					3'h6: MOSIout <= 1'b0; // Address bit 5
+					default MOSIout <= 1'b0;
+				endcase
+			end 7: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 4
+					3'h4: MOSIout <= 1'b0; // Address bit 20
+					3'h5: MOSIout <= 1'b0; // Address bit 12
+					3'h6: MOSIout <= 1'b0; // Address bit 4
+					default MOSIout <= 1'b0;
+				endcase
+			end 9: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 3
+					3'h4: MOSIout <= 1'b0; // Address bit 19
+					3'h5: MOSIout <= 1'b0; // Address bit 11
+					3'h6: MOSIout <= 1'b0; // Address bit 3
+					default MOSIout <= 1'b0;
+				endcase
+			end 11: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b0; // Command bit 2
+					3'h4: MOSIout <= 1'b0; // Address bit 18
+					3'h5: MOSIout <= 1'b0; // Address bit 10
+					3'h6: MOSIout <= 1'b0; // Address bit 2
+					default MOSIout <= 1'b0;
+				endcase
+			end 13: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 1
+					3'h4: MOSIout <= 1'b0; // Address bit 16
+					3'h5: MOSIout <= 1'b0; // Address bit 9
+					3'h6: MOSIout <= 1'b0; // Address bit 1
+					default MOSIout <= 1'b0;
+				endcase
+			end 15: begin
+				case (LS[2:0])
+					3'h3: MOSIout <= 1'b1; // Command bit 0
+					3'h4: MOSIout <= 1'b0; // Address bit 15
+					3'h5: MOSIout <= 1'b0; // Address bit 7
+					3'h6: MOSIout <= 1'b0; // Address bit 0
+					default MOSIout <= 1'b0;
+				endcase
+			end 
+		endcase
+	end
+
+	/* SDRAM data bus */
+	inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
+	reg [7:0] WRD;
+	reg SDOE = 0;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 1: begin // ACT
+			end 2: begin // RD
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 3: begin // NOP CKE
+			end 4: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 5: begin // NOP CKE
+			end 6: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 7: begin // NOP CKE
+			end 8: begin // WR AP
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 9: begin // NOP CKE
+			end 10: begin // PC all
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 11: begin // AREF
+			end 12: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 13: begin // NOP CKE
+			end 14: begin // NOP CKE
+				if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
+				else WRD[7:0] <= RD[7:0];
+			end 15: begin // NOP CKE
+			end
+		endcase
+	end
+
+	/* Apple data bus from SDRAM */
+	always @(negedge C25M) begin
+		if (PS==5) begin
+			if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
+			else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
+			else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
+			else RDD[7:0] <= SD[7:0];
+		end
+	end
+
+	/* SDRAM command */
+	output reg RCKE = 1;
+	output reg nRCS = 1;
+	output reg nRAS = 1;
+	output reg nCAS = 1;
+	output reg nSWE = 1;
+	wire RefReqd = LS[1:0] == 2'b11;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE / NOP CKD
+				RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 1: begin // ACT CKE / NOP CKD (ACT)
+				RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
+				nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
+				nRAS <= 0;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 2: begin // RD CKE / NOP CKD (RD)
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
+				nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
+				nRAS <= 1;
+				nCAS <= 0;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 3: begin // NOP CKE / CKD
+				RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 4: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 5: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 6: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 7: begin // NOP CKE / CKD
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 8: begin // WR AP CKE / NOP CKD (WR AP)
+				RCKE <= IS==6 || (RAMWR && IS==7);
+				nRCS <= !(IS==6 || (RAMWR && IS==7));
+				nRAS <= 1;
+				nCAS <= 0;
+				nSWE <= 0;
+				SDOE <= IS==6 || (RAMWR && IS==7);
+			end 9: begin // NOP CKE / NOP CKD
+				RCKE <= 1;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end 10: begin // PC all CKE / PC all CKD
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
+				nRCS <= 0;
+				nRAS <= 0;
+				nCAS <= 1;
+				nSWE <= 0;
+				SDOE <= 0;
+			end 11: begin // LDM CKE / AREF CKE / NOP CKD
+				RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
+				nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
+				nRAS <= 0;
+				nCAS <= 0;
+				nSWE <= !(IS==1);
+				SDOE <= 0;
+			end default: begin // NOP CKD
+				RCKE <= 0;
+				nRCS <= 1;
+				nRAS <= 1;
+				nCAS <= 1;
+				nSWE <= 1;
+				SDOE <= 0;
+			end
+		endcase
+	end
+
+	/* SDRAM address */
+	output reg DQML = 1;
+	output reg DQMH = 1;
+	output reg [1:0] SBA;
+	output reg [12:0] SA;
+	always @(posedge C25M) begin
+		case (PS[3:0])
+			0: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 1: begin // ACT
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				if (IS==6) begin
+					SBA[1:0] <= { 2'b10 };
+					SA[12:0] <= { 10'b0011000100, LS[12:10] };
+				end else if (RAMSpecSEL) begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
+					SA[9:0] <= Addr[19:10];
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
+				end
+			end 2: begin // RD
+				if (RAMSpecSEL) begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= !Addr[0];
+				end else begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, RAr[9:1]};
+					DQML <= RAr[0];
+					DQMH <= !RAr[0];
+				end
+			end 3: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 4: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 5: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 6: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 7: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 8: begin // WR AP
+				if (IS==6) begin
+					SBA[1:0] <= 2'b10;
+					SA[12:0] <= { 4'b0011, LS[9:1] };
+					DQML <= LS[0];
+					DQMH <= !LS[0];
+				end else begin
+					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SA[12:0] <= { 4'b0011, Addr[9:1] };
+					DQML <= Addr[0];
+					DQMH <= !Addr[0];
+				end
+			end 9: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 10: begin // PC all
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 11: begin // AREF / load mode
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0001000100000;
+			end 12: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 13: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 14: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end 15: begin // NOP CKE
+				DQML <= 1'b1;
+				DQMH <= 1'b1;
+				SBA[1:0] <= 2'b00;
+				SA[12:0] <= 13'b0011000100000;
+			end
+		endcase
+	end
+
+	/* DMA/INT in/out */
+	input INTin, DMAin;
+	output INTout = INTin;
+	output DMAout = DMAin;
+
+	/* Unused Pins */
+	output RAdir = 1;
+	output nDMAout = 1;
+	output nNMIout = 1;
+	output nINHout = 1;
+	output nRDYout = 1;
+	output nIRQout = 1;
+	output RWout = 1;
+endmodule

Documentation/Flash Map

@@ -0,0 +1,38 @@
+GR8RAM flash memory map
+
+....		-----------------------------
+7FFF		|							|
+....		|     firmware 3 (8 kB)     |
+6000		|							|
+			-----------------------------
+5FFF		|							|
+....		|     firmware 2 (8 kB)     |
+4000		|							|
+			-----------------------------
+3FFF		|							|
+....		|     firmware 1 (8 kB)     |
+2000		|							|
+			-----------------------------
+1FFF		|							|
+....		|     firmware 0 (8 kB)     |
+0000		|							|
+			-----------------------------
+
+Firmware area map (N=$0000, $2000, $4000, $6000)
+			-----------------------------
+N+1FFF		|							|
+....		|    IOSTRB bank 1 (2 kB)   |
+N+1800		|							|
+			-----------------------------
+N+17FF		|							|
+....		|    IOSEL bank 1 (2 kB)    |
+N+1000		|							|
+			-----------------------------
+N+0FFF		|							|
+....		|    IOSTRB bank 0 (2 kB)   |
+N+0800		|							|
+			-----------------------------
+N+07FF		|							|
+....		|    IOSEL bank 0 (2 kB)    |
+N+0000		|							|
+			-----------------------------

Documentation/RAM Map

@@ -0,0 +1,32 @@
+GR8RAM/LibraryCard Slinky RAM memory map
+			-----------------------------
+1 FF FFFF	|							|
+. .. ....	|    reserved (16,376 kB)   |
+1 00 2000	|							|
+			-----------------------------
+1 00 1FFF	|							|
+. .. ....	|      firmware (8 kB)      |
+1 00 0000	|							|
+			-----------------------------
+0 FF FFFF	|							|
+. .. ....	|     Slinky RAM (16 MB)    |
+0 00 0000	|							|
+			-----------------------------
+
+			-----------------------------
+1 00 1FFF	|							|
+....		|    IOSTRB bank 1 (2 kB)   |
+1 00 1800	|							|
+			-----------------------------
+1 00 17FF	|							|
+....		|    IOSEL bank 1 (2 kB)    |
+1 00 1000	|							|
+			-----------------------------
+1 00 0FFF	|							|
+....		|    IOSTRB bank 0 (2 kB)   |
+1 00 0800	|							|
+			-----------------------------
+1 00 07FF	|							|
+....		|    IOSEL bank 0 (2 kB)    |
+1 00 0000	|							|
+			-----------------------------

GR8RAM-cache.lib

@@ -1,482 +0,0 @@
-EESchema-LIBRARY Version 2.4
-#encoding utf-8
-#
-# Connector_AVR-JTAG-10
-#
-DEF Connector_AVR-JTAG-10 J 0 40 Y Y 1 F N
-F0 "J" 175 500 50 H V L CNN
-F1 "Connector_AVR-JTAG-10" 100 -500 50 H V L CNN
-F2 "" -150 150 50 V I C CNN
-F3 "" -1275 -550 50 H I C CNN
-$FPLIST
- IDC?Header*2x05*
- Pin?Header*2x05*
-$ENDFPLIST
-DRAW
-S -105 450 -95 420 0 1 0 N
-S -5 -420 5 -450 0 1 0 N
-S -5 450 5 420 0 1 0 N
-S 350 -195 320 -205 0 1 0 N
-S 350 -95 320 -105 0 1 0 N
-S 350 5 320 -5 0 1 0 N
-S 350 105 320 95 0 1 0 N
-S 350 205 320 195 0 1 0 N
-S 350 305 320 295 0 1 0 N
-S 350 450 -350 -450 0 1 10 f
-X TCK 1 500 100 150 L 50 50 1 1 P
-X GND 10 0 -600 150 U 50 50 1 1 W
-X GND 2 0 -600 150 U 50 50 1 1 P N
-X TDO 3 500 -100 150 L 50 50 1 1 P
-X VREF 4 -100 600 150 D 50 50 1 1 P
-X TMS 5 500 0 150 L 50 50 1 1 P
-X ~SRST 6 500 300 150 L 50 50 1 1 P
-X VCC 7 0 600 150 D 50 50 1 1 W
-X ~TRST 8 500 200 150 L 50 50 1 1 P
-X TDI 9 500 -200 150 L 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# Connector_Generic_Conn_02x25_Counter_Clockwise
-#
-DEF Connector_Generic_Conn_02x25_Counter_Clockwise J 0 40 Y N 1 F N
-F0 "J" 50 1300 50 H V C CNN
-F1 "Connector_Generic_Conn_02x25_Counter_Clockwise" 50 -1300 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- Connector*:*_2x??_*
-$ENDFPLIST
-DRAW
-S -50 -1195 0 -1205 1 1 6 N
-S -50 -1095 0 -1105 1 1 6 N
-S -50 -995 0 -1005 1 1 6 N
-S -50 -895 0 -905 1 1 6 N
-S -50 -795 0 -805 1 1 6 N
-S -50 -695 0 -705 1 1 6 N
-S -50 -595 0 -605 1 1 6 N
-S -50 -495 0 -505 1 1 6 N
-S -50 -395 0 -405 1 1 6 N
-S -50 -295 0 -305 1 1 6 N
-S -50 -195 0 -205 1 1 6 N
-S -50 -95 0 -105 1 1 6 N
-S -50 5 0 -5 1 1 6 N
-S -50 105 0 95 1 1 6 N
-S -50 205 0 195 1 1 6 N
-S -50 305 0 295 1 1 6 N
-S -50 405 0 395 1 1 6 N
-S -50 505 0 495 1 1 6 N
-S -50 605 0 595 1 1 6 N
-S -50 705 0 695 1 1 6 N
-S -50 805 0 795 1 1 6 N
-S -50 905 0 895 1 1 6 N
-S -50 1005 0 995 1 1 6 N
-S -50 1105 0 1095 1 1 6 N
-S -50 1205 0 1195 1 1 6 N
-S -50 1250 150 -1250 1 1 10 f
-S 150 -1195 100 -1205 1 1 6 N
-S 150 -1095 100 -1105 1 1 6 N
-S 150 -995 100 -1005 1 1 6 N
-S 150 -895 100 -905 1 1 6 N
-S 150 -795 100 -805 1 1 6 N
-S 150 -695 100 -705 1 1 6 N
-S 150 -595 100 -605 1 1 6 N
-S 150 -495 100 -505 1 1 6 N
-S 150 -395 100 -405 1 1 6 N
-S 150 -295 100 -305 1 1 6 N
-S 150 -195 100 -205 1 1 6 N
-S 150 -95 100 -105 1 1 6 N
-S 150 5 100 -5 1 1 6 N
-S 150 105 100 95 1 1 6 N
-S 150 205 100 195 1 1 6 N
-S 150 305 100 295 1 1 6 N
-S 150 405 100 395 1 1 6 N
-S 150 505 100 495 1 1 6 N
-S 150 605 100 595 1 1 6 N
-S 150 705 100 695 1 1 6 N
-S 150 805 100 795 1 1 6 N
-S 150 905 100 895 1 1 6 N
-S 150 1005 100 995 1 1 6 N
-S 150 1105 100 1095 1 1 6 N
-S 150 1205 100 1195 1 1 6 N
-X Pin_1 1 -200 1200 150 R 50 50 1 1 P
-X Pin_10 10 -200 300 150 R 50 50 1 1 P
-X Pin_11 11 -200 200 150 R 50 50 1 1 P
-X Pin_12 12 -200 100 150 R 50 50 1 1 P
-X Pin_13 13 -200 0 150 R 50 50 1 1 P
-X Pin_14 14 -200 -100 150 R 50 50 1 1 P
-X Pin_15 15 -200 -200 150 R 50 50 1 1 P
-X Pin_16 16 -200 -300 150 R 50 50 1 1 P
-X Pin_17 17 -200 -400 150 R 50 50 1 1 P
-X Pin_18 18 -200 -500 150 R 50 50 1 1 P
-X Pin_19 19 -200 -600 150 R 50 50 1 1 P
-X Pin_2 2 -200 1100 150 R 50 50 1 1 P
-X Pin_20 20 -200 -700 150 R 50 50 1 1 P
-X Pin_21 21 -200 -800 150 R 50 50 1 1 P
-X Pin_22 22 -200 -900 150 R 50 50 1 1 P
-X Pin_23 23 -200 -1000 150 R 50 50 1 1 P
-X Pin_24 24 -200 -1100 150 R 50 50 1 1 P
-X Pin_25 25 -200 -1200 150 R 50 50 1 1 P
-X Pin_26 26 300 -1200 150 L 50 50 1 1 P
-X Pin_27 27 300 -1100 150 L 50 50 1 1 P
-X Pin_28 28 300 -1000 150 L 50 50 1 1 P
-X Pin_29 29 300 -900 150 L 50 50 1 1 P
-X Pin_3 3 -200 1000 150 R 50 50 1 1 P
-X Pin_30 30 300 -800 150 L 50 50 1 1 P
-X Pin_31 31 300 -700 150 L 50 50 1 1 P
-X Pin_32 32 300 -600 150 L 50 50 1 1 P
-X Pin_33 33 300 -500 150 L 50 50 1 1 P
-X Pin_34 34 300 -400 150 L 50 50 1 1 P
-X Pin_35 35 300 -300 150 L 50 50 1 1 P
-X Pin_36 36 300 -200 150 L 50 50 1 1 P
-X Pin_37 37 300 -100 150 L 50 50 1 1 P
-X Pin_38 38 300 0 150 L 50 50 1 1 P
-X Pin_39 39 300 100 150 L 50 50 1 1 P
-X Pin_4 4 -200 900 150 R 50 50 1 1 P
-X Pin_40 40 300 200 150 L 50 50 1 1 P
-X Pin_41 41 300 300 150 L 50 50 1 1 P
-X Pin_42 42 300 400 150 L 50 50 1 1 P
-X Pin_43 43 300 500 150 L 50 50 1 1 P
-X Pin_44 44 300 600 150 L 50 50 1 1 P
-X Pin_45 45 300 700 150 L 50 50 1 1 P
-X Pin_46 46 300 800 150 L 50 50 1 1 P
-X Pin_47 47 300 900 150 L 50 50 1 1 P
-X Pin_48 48 300 1000 150 L 50 50 1 1 P
-X Pin_49 49 300 1100 150 L 50 50 1 1 P
-X Pin_5 5 -200 800 150 R 50 50 1 1 P
-X Pin_50 50 300 1200 150 L 50 50 1 1 P
-X Pin_6 6 -200 700 150 R 50 50 1 1 P
-X Pin_7 7 -200 600 150 R 50 50 1 1 P
-X Pin_8 8 -200 500 150 R 50 50 1 1 P
-X Pin_9 9 -200 400 150 R 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# Device_CP_Small
-#
-DEF Device_CP_Small C 0 10 N N 1 F N
-F0 "C" 10 70 50 H V L CNN
-F1 "Device_CP_Small" 10 -80 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- CP_*
-$ENDFPLIST
-DRAW
-S -60 -12 60 -27 0 1 0 F
-S -60 27 60 12 0 1 0 N
-P 2 0 1 0 -50 60 -30 60 N
-P 2 0 1 0 -40 50 -40 70 N
-X ~ 1 0 100 73 D 50 50 1 1 P
-X ~ 2 0 -100 73 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# Device_C_Small
-#
-DEF Device_C_Small C 0 10 N N 1 F N
-F0 "C" 10 70 50 H V L CNN
-F1 "Device_C_Small" 10 -80 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 13 -60 -20 60 -20 N
-P 2 0 1 12 -60 20 60 20 N
-X ~ 1 0 100 80 D 50 50 1 1 P
-X ~ 2 0 -100 80 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# Mechanical_MountingHole
-#
-DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
-F0 "H" 0 200 50 H V C CNN
-F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- MountingHole*
-$ENDFPLIST
-DRAW
-C 0 0 50 0 1 50 N
-ENDDRAW
-ENDDEF
-#
-# Mechanical_MountingHole_Pad
-#
-DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
-F0 "H" 0 250 50 H V C CNN
-F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- MountingHole*Pad*
-$ENDFPLIST
-DRAW
-C 0 50 50 0 1 50 N
-X 1 1 0 -100 100 U 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# power_+12V
-#
-DEF power_+12V #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -150 50 H I C CNN
-F1 "power_+12V" 0 140 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 2 0 1 0 -30 50 0 100 N
-P 2 0 1 0 0 0 0 100 N
-P 2 0 1 0 0 100 30 50 N
-X +12V 1 0 0 0 U 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# power_+5V
-#
-DEF power_+5V #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -150 50 H I C CNN
-F1 "power_+5V" 0 140 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 2 0 1 0 -30 50 0 100 N
-P 2 0 1 0 0 0 0 100 N
-P 2 0 1 0 0 100 30 50 N
-X +5V 1 0 0 0 U 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# power_-12V
-#
-DEF power_-12V #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 100 50 H I C CNN
-F1 "power_-12V" 0 150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
-X -12V 1 0 0 0 U 50 50 0 0 W N
-ENDDRAW
-ENDDEF
-#
-# power_-5V
-#
-DEF power_-5V #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 100 50 H I C CNN
-F1 "power_-5V" 0 150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
-X -5V 1 0 0 0 U 50 50 0 0 W N
-ENDDRAW
-ENDDEF
-#
-# power_GND
-#
-DEF power_GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "power_GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# stdparts_39F040
-#
-DEF stdparts_39F040 U 0 20 Y Y 1 F N
-F0 "U" 0 1050 50 H V C CNN
-F1 "stdparts_39F040" 0 0 50 V V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-S -300 1000 300 -1000 0 1 10 f
-X GND 16 500 -900 200 L 50 50 0 0 W
-X VCC 32 500 900 200 L 50 50 0 0 W
-X A18 1 -500 -900 200 R 50 50 1 1 I
-X A2 10 -500 700 200 R 50 50 1 1 I
-X A1 11 -500 800 200 R 50 50 1 1 I
-X A0 12 -500 900 200 R 50 50 1 1 I
-X D0 13 500 700 200 L 50 50 1 1 T
-X D1 14 500 600 200 L 50 50 1 1 T
-X D2 15 500 500 200 L 50 50 1 1 T
-X D3 17 500 400 200 L 50 50 1 1 T
-X D4 18 500 300 200 L 50 50 1 1 T
-X D5 19 500 200 200 L 50 50 1 1 T
-X A16 2 -500 -700 200 R 50 50 1 1 I
-X D6 20 500 100 200 L 50 50 1 1 T
-X D7 21 500 0 200 L 50 50 1 1 T
-X ~CS~ 22 500 -400 200 L 50 50 1 1 I L
-X A10 23 -500 -100 200 R 50 50 1 1 I
-X ~OE~ 24 500 -600 200 L 50 50 1 1 I L
-X A11 25 -500 -200 200 R 50 50 1 1 I
-X A9 26 -500 0 200 R 50 50 1 1 I
-X A8 27 -500 100 200 R 50 50 1 1 I
-X A13 28 -500 -400 200 R 50 50 1 1 I
-X A14 29 -500 -500 200 R 50 50 1 1 I
-X A15 3 -500 -600 200 R 50 50 1 1 I
-X A17 30 -500 -800 200 R 50 50 1 1 I
-X ~WE~ 31 500 -500 200 L 50 50 1 1 I L
-X A12 4 -500 -300 200 R 50 50 1 1 I
-X A7 5 -500 200 200 R 50 50 1 1 I
-X A6 6 -500 300 200 R 50 50 1 1 I
-X A5 7 -500 400 200 R 50 50 1 1 I
-X A4 8 -500 500 200 R 50 50 1 1 I
-X A3 9 -500 600 200 R 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# stdparts_AS4C4M4
-#
-DEF stdparts_AS4C4M4 U 0 20 Y Y 1 F N
-F0 "U" 0 800 50 H V C CNN
-F1 "stdparts_AS4C4M4" 0 0 50 V V C CNN
-F2 "Package_SO:TSOP-II-44_10.16x18.41mm_P0.8mm" 0 -900 50 H I C CNN
-F3 "" 0 -450 50 H I C CNN
-$FPLIST
- SOJ*10.16x23.49mm*P1.27mm*
-$ENDFPLIST
-DRAW
-S -300 750 300 -850 0 1 10 f
-X A4 1 -400 250 100 R 50 50 1 1 I
-X I/O2 11 400 250 100 L 50 50 1 1 B
-X VDD 11 400 650 100 L 50 50 1 1 W
-X GND 12 -400 -750 100 R 50 50 1 1 P N
-X I/O3 12 400 150 100 L 50 50 1 1 B
-X NC 15 -400 -550 100 R 50 50 1 1 N N
-X NC 16 -400 -550 100 R 50 50 1 1 N N
-X ~WE~ 17 400 -650 100 L 50 50 1 1 I
-X A3 2 -400 350 100 R 50 50 1 1 I
-X I/O4 25 400 50 100 L 50 50 1 1 B
-X I/O5 26 400 -50 100 L 50 50 1 1 B
-X A10 27 -400 -350 100 R 50 50 1 1 I
-X A9 28 -400 -250 100 R 50 50 1 1 I
-X I/O6 29 400 -150 100 L 50 50 1 1 B
-X NC 29 -400 -550 100 R 50 50 1 1 N N
-X A2 3 -400 450 100 R 50 50 1 1 I
-X I/O7 30 400 -250 100 L 50 50 1 1 B
-X NC 30 -400 -550 100 R 50 50 1 1 N N
-X VDD 33 400 650 100 L 50 50 1 1 W N
-X GND 34 -400 -750 100 R 50 50 1 1 W
-X NC 37 -400 -550 100 R 50 50 1 1 N N
-X NC 38 -400 -550 100 R 50 50 1 1 N N
-X A8 39 -400 -150 100 R 50 50 1 1 I
-X A1 4 -400 550 100 R 50 50 1 1 I
-X ~RAS~ 40 400 -550 100 L 50 50 1 1 I
-X ~OE~ 41 400 -750 100 L 50 50 1 1 I
-X A7 42 -400 -50 100 R 50 50 1 1 I
-X A6 43 -400 50 100 R 50 50 1 1 I
-X A5 44 -400 150 100 R 50 50 1 1 I
-X A0 5 -400 650 100 R 50 50 1 1 I
-X ~CAS~ 6 400 -450 100 L 50 50 1 1 I
-X I/O0 7 400 450 100 L 50 50 1 1 B
-X NC 7 -400 -550 100 R 50 50 1 1 N N
-X I/O1 8 400 350 100 L 50 50 1 1 B
-X NC 8 -400 -550 100 R 50 50 1 1 N N
-ENDDRAW
-ENDDEF
-#
-# stdparts_EPM7128SL84
-#
-DEF stdparts_EPM7128SL84 U 0 40 Y Y 1 F N
-F0 "U" 0 50 50 H V C CNN
-F1 "stdparts_EPM7128SL84" 0 -50 50 H V C CNN
-F2 "" -150 200 50 H I C CNN
-F3 "" -150 200 50 H I C CNN
-DRAW
-S -600 -1950 600 1850 0 1 10 f
-X ~GClr~ 1 750 900 150 L 50 50 1 1 I
-X I/O 10 750 1600 150 L 50 50 1 1 B
-X I/O 11 750 1700 150 L 50 50 1 1 B
-X I/O 12 -750 1700 150 R 50 50 1 1 B
-X VccIO 13 -350 2000 150 D 50 50 1 1 W
-X TDI 14 -750 1600 150 R 50 50 1 1 B
-X I/O 15 -750 1500 150 R 50 50 1 1 B
-X I/O 16 -750 1400 150 R 50 50 1 1 B
-X I/O 17 -750 1300 150 R 50 50 1 1 B
-X I/O 18 -750 1200 150 R 50 50 1 1 B
-X GND 19 -350 -2100 150 U 50 50 1 1 W
-X OE2/GClk2 2 750 1000 150 L 50 50 1 1 I
-X I/O 20 -750 1100 150 R 50 50 1 1 B
-X I/O 21 -750 1000 150 R 50 50 1 1 B
-X I/O 22 -750 900 150 R 50 50 1 1 B
-X TMS 23 -750 800 150 R 50 50 1 1 B
-X I/O 24 -750 700 150 R 50 50 1 1 B
-X I/O 25 -750 600 150 R 50 50 1 1 B
-X VccIO 26 -250 2000 150 D 50 50 1 1 W
-X I/O 27 -750 500 150 R 50 50 1 1 W
-X I/O 28 -750 400 150 R 50 50 1 1 B
-X I/O 29 -750 300 150 R 50 50 1 1 B
-X VccINT 3 350 2000 150 D 50 50 1 1 W
-X I/O 30 -750 200 150 R 50 50 1 1 B
-X I/O 31 -750 100 150 R 50 50 1 1 B
-X GND 32 -250 -2100 150 U 50 50 1 1 W
-X I/O 33 -750 -100 150 R 50 50 1 1 B
-X I/O 34 -750 -200 150 R 50 50 1 1 B
-X I/O 35 -750 -300 150 R 50 50 1 1 B
-X I/O 36 -750 -400 150 R 50 50 1 1 B
-X I/O 37 -750 -500 150 R 50 50 1 1 B
-X VccIO 38 -150 2000 150 D 50 50 1 1 W
-X I/O/NC 39 -750 -600 150 R 50 50 1 1 B
-X I/O 4 750 1100 150 L 50 50 1 1 B
-X I/O 40 -750 -700 150 R 50 50 1 1 B
-X I/O 41 -750 -800 150 R 50 50 1 1 B
-X GND 42 -150 -2100 150 U 50 50 1 1 W
-X VccINT 43 250 2000 150 D 50 50 1 1 W
-X I/O 44 -750 -900 150 R 50 50 1 1 B
-X I/O 45 -750 -1000 150 R 50 50 1 1 B
-X I/O/NC 46 -750 -1100 150 R 50 50 1 1 B
-X GND 47 -50 -2100 150 U 50 50 1 1 W
-X I/O 48 -750 -1200 150 R 50 50 1 1 B
-X I/O 49 -750 -1300 150 R 50 50 1 1 B
-X I/O 5 750 1200 150 L 50 50 1 1 B
-X I/O 50 -750 -1400 150 R 50 50 1 1 B
-X I/O 51 -750 -1500 150 R 50 50 1 1 B
-X I/O 52 -750 -1600 150 R 50 50 1 1 B
-X VccIO 53 -50 2000 150 D 50 50 1 1 W
-X I/O 54 750 -1800 150 L 50 50 1 1 B
-X I/O 55 750 -1700 150 L 50 50 1 1 B
-X I/O 56 750 -1600 150 L 50 50 1 1 B
-X I/O 57 750 -1500 150 L 50 50 1 1 B
-X I/O 58 750 -1400 150 L 50 50 1 1 B
-X GND 59 50 -2100 150 U 50 50 1 1 W
-X I/O/NC 6 750 1300 150 L 50 50 1 1 B
-X I/O 60 750 -1300 150 L 50 50 1 1 B
-X I/O 61 750 -1200 150 L 50 50 1 1 B
-X TCK 62 750 -1100 150 L 50 50 1 1 B
-X I/O 63 750 -1000 150 L 50 50 1 1 B
-X I/O 64 750 -900 150 L 50 50 1 1 B
-X I/O 65 750 -800 150 L 50 50 1 1 B
-X VccIO 66 50 2000 150 D 50 50 1 1 W
-X I/O 67 750 -700 150 L 50 50 1 1 B
-X I/O 68 750 -600 150 L 50 50 1 1 B
-X I/O 69 750 -500 150 L 50 50 1 1 B
-X GND 7 350 -2100 150 U 50 50 1 1 W
-X I/O 70 750 -400 150 L 50 50 1 1 B
-X TDO 71 750 -300 150 L 50 50 1 1 B
-X GND 72 150 -2100 150 U 50 50 1 1 W
-X I/O 73 750 -200 150 L 50 50 1 1 B
-X I/O 74 750 -100 150 L 50 50 1 1 B
-X I/O 75 750 100 150 L 50 50 1 1 B
-X I/O 76 750 200 150 L 50 50 1 1 B
-X I/O 77 750 300 150 L 50 50 1 1 B
-X VccIO 78 150 2000 150 D 50 50 1 1 W
-X I/O/NC 79 750 400 150 L 50 50 1 1 B
-X I/O 8 750 1400 150 L 50 50 1 1 B
-X I/O 80 750 500 150 L 50 50 1 1 B
-X I/O 81 750 600 150 L 50 50 1 1 B
-X GND 82 250 -2100 150 U 50 50 1 1 W
-X GClk1 83 750 700 150 L 50 50 1 1 I
-X OE1 84 750 800 150 L 50 50 1 1 I
-X I/O 9 750 1500 150 L 50 50 1 1 B
-ENDDRAW
-ENDDEF
-#
-#End Library

GR8RAM.pro

@@ -1,256 +0,0 @@
-update=Monday, June 10, 2019 at 02:27:25 PM
-version=1
-last_client=kicad
-[general]
-version=1
-RootSch=
-BoardNm=
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
-[pcbnew]
-version=1
-PageLayoutDescrFile=
-LastNetListRead=GR8RAM.net
-CopperLayerCount=4
-BoardThickness=1.6
-AllowMicroVias=0
-AllowBlindVias=0
-RequireCourtyardDefinitions=0
-ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.1524
-MinViaDiameter=0.4
-MinViaDrill=0.3
-MinMicroViaDiameter=0.2
-MinMicroViaDrill=0.09999999999999999
-MinHoleToHole=0.25
-TrackWidth1=0.1524
-TrackWidth2=0.2
-TrackWidth3=0.254
-TrackWidth4=0.508
-TrackWidth5=0.762
-TrackWidth6=1.27
-TrackWidth7=1.524
-ViaDiameter1=0.8
-ViaDrill1=0.4
-ViaDiameter2=1.524
-ViaDrill2=0.762
-dPairWidth1=0.2
-dPairGap1=0.25
-dPairViaGap1=0.25
-SilkLineWidth=0.15
-SilkTextSizeV=1
-SilkTextSizeH=1
-SilkTextSizeThickness=0.15
-SilkTextItalic=0
-SilkTextUpright=1
-CopperLineWidth=0.1524
-CopperTextSizeV=1.5
-CopperTextSizeH=1.5
-CopperTextThickness=0.3
-CopperTextItalic=0
-CopperTextUpright=1
-EdgeCutLineWidth=0.15
-CourtyardLineWidth=0.05
-OthersLineWidth=0.15
-OthersTextSizeV=1
-OthersTextSizeH=1
-OthersTextSizeThickness=0.15
-OthersTextItalic=0
-OthersTextUpright=1
-SolderMaskClearance=0.07619999999999999
-SolderMaskMinWidth=0.1524
-SolderPasteClearance=-0.05
-SolderPasteRatio=0
-[pcbnew/Layer.F.Cu]
-Name=F.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.In1.Cu]
-Name=In1.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.In2.Cu]
-Name=In2.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.In3.Cu]
-Name=In3.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In4.Cu]
-Name=In4.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In5.Cu]
-Name=In5.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In6.Cu]
-Name=In6.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In7.Cu]
-Name=In7.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In8.Cu]
-Name=In8.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In9.Cu]
-Name=In9.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In10.Cu]
-Name=In10.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In11.Cu]
-Name=In11.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In12.Cu]
-Name=In12.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In13.Cu]
-Name=In13.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In14.Cu]
-Name=In14.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In15.Cu]
-Name=In15.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In16.Cu]
-Name=In16.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In17.Cu]
-Name=In17.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In18.Cu]
-Name=In18.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In19.Cu]
-Name=In19.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In20.Cu]
-Name=In20.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In21.Cu]
-Name=In21.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In22.Cu]
-Name=In22.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In23.Cu]
-Name=In23.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In24.Cu]
-Name=In24.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In25.Cu]
-Name=In25.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In26.Cu]
-Name=In26.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In27.Cu]
-Name=In27.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In28.Cu]
-Name=In28.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In29.Cu]
-Name=In29.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In30.Cu]
-Name=In30.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.B.Cu]
-Name=B.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.B.Adhes]
-Enabled=1
-[pcbnew/Layer.F.Adhes]
-Enabled=1
-[pcbnew/Layer.B.Paste]
-Enabled=1
-[pcbnew/Layer.F.Paste]
-Enabled=1
-[pcbnew/Layer.B.SilkS]
-Enabled=1
-[pcbnew/Layer.F.SilkS]
-Enabled=1
-[pcbnew/Layer.B.Mask]
-Enabled=1
-[pcbnew/Layer.F.Mask]
-Enabled=1
-[pcbnew/Layer.Dwgs.User]
-Enabled=1
-[pcbnew/Layer.Cmts.User]
-Enabled=1
-[pcbnew/Layer.Eco1.User]
-Enabled=1
-[pcbnew/Layer.Eco2.User]
-Enabled=1
-[pcbnew/Layer.Edge.Cuts]
-Enabled=1
-[pcbnew/Layer.Margin]
-Enabled=1
-[pcbnew/Layer.B.CrtYd]
-Enabled=1
-[pcbnew/Layer.F.CrtYd]
-Enabled=1
-[pcbnew/Layer.B.Fab]
-Enabled=1
-[pcbnew/Layer.F.Fab]
-Enabled=1
-[pcbnew/Layer.Rescue]
-Enabled=0
-[pcbnew/Netclasses]
-[pcbnew/Netclasses/Default]
-Name=Default
-Clearance=0.1524
-TrackWidth=0.1524
-ViaDiameter=0.8
-ViaDrill=0.4
-uViaDiameter=0.3
-uViaDrill=0.1
-dPairWidth=0.2
-dPairGap=0.25
-dPairViaGap=0.25

Hardware/LCMXO2/GR8RAM

@@ -0,0 +1,21 @@
+Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
+C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
+C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
+FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
+H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
+H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
+J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
+J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
+J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
+R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
+R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
+RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
+RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
+SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
+U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
+U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
+U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
+U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
+U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
+U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
+U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"

Hardware/LCMXO2/GR8RAM.kicad_pro

@@ -0,0 +1,701 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "apply_defaults_to_fp_fields": false,
+        "apply_defaults_to_fp_shapes": false,
+        "apply_defaults_to_fp_text": false,
+        "board_outline_line_width": 0.15,
+        "copper_line_width": 0.1524,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.05,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.1,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.1,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.0,
+          "height": 0.4,
+          "width": 0.65
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.15
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "error",
+        "courtyards_overlap": "warning",
+        "creepage": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "error",
+        "extra_footprint": "error",
+        "footprint": "error",
+        "footprint_filters_mismatch": "ignore",
+        "footprint_symbol_mismatch": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "hole_to_hole": "error",
+        "holes_co_located": "warning",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "ignore",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "mirrored_text_on_front_layer": "warning",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "error",
+        "net_conflict": "error",
+        "nonmirrored_text_on_back_layer": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "ignore",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_on_edge_cuts": "error",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_angle": "error",
+        "track_dangling": "warning",
+        "track_segment_length": "error",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.15,
+        "min_connection": 0.12,
+        "min_copper_edge_clearance": 0.4064,
+        "min_groove_width": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.5,
+        "min_microvia_diameter": 0.2,
+        "min_microvia_drill": 0.1,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
+        "min_text_height": 0.8,
+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.15,
+        "min_via_annular_width": 0.1,
+        "min_via_diameter": 0.5,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_onpthpad": true,
+          "td_onroundshapesonly": false,
+          "td_onsmdpad": true,
+          "td_ontrackend": false,
+          "td_onvia": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [
+        0.0,
+        0.15,
+        0.2,
+        0.25,
+        0.3,
+        0.35,
+        0.4,
+        0.45,
+        0.5,
+        0.6,
+        0.8,
+        1.0,
+        1.27,
+        1.524
+      ],
+      "tuning_pattern_settings": {
+        "diff_pair_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 1.0
+        },
+        "diff_pair_skew_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        },
+        "single_track_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        }
+      },
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        },
+        {
+          "diameter": 0.5,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.6,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.4
+        },
+        {
+          "diameter": 1.0,
+          "drill": 0.5
+        },
+        {
+          "diameter": 1.524,
+          "drill": 0.762
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "ipc2581": {
+      "dist": "",
+      "distpn": "",
+      "internal_id": "",
+      "mfg": "",
+      "mpn": ""
+    },
+    "layer_pairs": [],
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "footprint_filter": "ignore",
+      "footprint_link_issues": "warning",
+      "four_way_junction": "ignore",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "label_multiple_wires": "warning",
+      "lib_symbol_issues": "warning",
+      "lib_symbol_mismatch": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "same_local_global_label": "warning",
+      "similar_label_and_power": "warning",
+      "similar_labels": "warning",
+      "similar_power": "warning",
+      "simulation_model_issue": "ignore",
+      "single_global_label": "ignore",
+      "unannotated": "error",
+      "unconnected_wire_endpoint": "warning",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "GR8RAM.kicad_pro",
+    "version": 3
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 2147483647,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.15,
+        "via_diameter": 0.5,
+        "via_drill": 0.3,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 4
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "GR8RAM.net",
+      "plot": "",
+      "pos_files": "",
+      "specctra_dsn": "",
+      "step": "",
+      "svg": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "bom_export_filename": "${PROJECTNAME}.csv",
+    "bom_fmt_presets": [],
+    "bom_fmt_settings": {
+      "field_delimiter": ",",
+      "keep_line_breaks": false,
+      "keep_tabs": false,
+      "name": "CSV",
+      "ref_delimiter": ",",
+      "ref_range_delimiter": "",
+      "string_delimiter": "\""
+    },
+    "bom_presets": [],
+    "bom_settings": {
+      "exclude_dnp": false,
+      "fields_ordered": [
+        {
+          "group_by": false,
+          "label": "Reference",
+          "name": "Reference",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Value",
+          "name": "Value",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Footprint",
+          "name": "Footprint",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Datasheet",
+          "name": "Datasheet",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Description",
+          "name": "Description",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "Qty",
+          "name": "${QUANTITY}",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "#",
+          "name": "${ITEM_NUMBER}",
+          "show": false
+        },
+        {
+          "group_by": false,
+          "label": "LCSC Part",
+          "name": "LCSC Part",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "DNP",
+          "name": "${DNP}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Exclude from BOM",
+          "name": "${EXCLUDE_FROM_BOM}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Exclude from Board",
+          "name": "${EXCLUDE_FROM_BOARD}",
+          "show": true
+        }
+      ],
+      "filter_string": "",
+      "group_symbols": true,
+      "include_excluded_from_bom": true,
+      "name": "",
+      "sort_asc": true,
+      "sort_field": "Reference"
+    },
+    "connection_grid_size": 50.0,
+    "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "operating_point_overlay_i_precision": 3,
+      "operating_point_overlay_i_range": "~A",
+      "operating_point_overlay_v_precision": 3,
+      "operating_point_overlay_v_range": "~V",
+      "overbar_offset_ratio": 1.23,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Pcbnew",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "space_save_all_events": true,
+    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_dissipations": false,
+    "spice_save_all_voltages": false,
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "a29f8df0-3fae-4edf-8d9c-bd5a875b13e3",
+      "Root"
+    ]
+  ],
+  "text_variables": {}
+}

Hardware/LCMXO2/fp-lib-table

@@ -0,0 +1,4 @@
+(fp_lib_table
+  (version 7)
+  (lib (name "stdpads")(type "KiCad")(uri "$(KIPRJMOD)/../../../stdpads.pretty")(options "")(descr ""))
+)

Hardware/LCMXO2/gerber/GR8RAM-BOM.csv

@@ -0,0 +1,30 @@
+"Reference","Quantity","Value","Footprint","LCSC Part","DNP"
+"C1, C2, C3, C4, C7, C10, C11, C36, C37, C38","10","10u","stdpads:C_0805","C15850",""
+"C5, C6, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C39, C40, C42, C43, C44, C45","32","2u2","stdpads:C_0603","C23630",""
+"C8, C9, C41","3","22p","stdpads:C_0603","C1653",""
+"D1","1","Amber","stdpads:LED_0805","C284932",""
+"FID1, FID2, FID3, FID4, FID5","5","Fiducial","stdpads:Fiducial","",""
+"H1","1","~","stdpads:PasteHole_1.1mm_PTH","",""
+"H2, H3, H4, H5","4","~","stdpads:PasteHole_1.152mm_NPTH","",""
+"J1","1","AppleIIBus","stdpads:AppleIIBus_Edge","",""
+"J2","1","microUSB","stdpads:USB_Micro-B_Amphenol_10118192-0001","C132564",""
+"J3","1","Flash","stdpads:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","",""
+"J4","1","JTAG","stdpads:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","",""
+"R1","1","0","stdpads:R_0805","C17477",""
+"R2, R5, R9, R10, R11, R13, R21, R22","8","47","stdpads:R_0603","C23182",""
+"R3, R7, R8, R12, R18, R19","6","DNP","stdpads:R_0603","",""
+"R4, R6, R17, R25, R26, R27","6","10k","stdpads:R_0603","C25804",""
+"R14, R15, R16, R23, R24","5","3k3","stdpads:R_0603","C22978",""
+"R20","1","220","stdpads:R_0805","C17557",""
+"SW1","1","FW","stdpads:SW_DIP_SPSTx03_Slide_DSHP03TS_P1.27mm","C319051",""
+"U1","1","LCMXO2-640HC-4TG100C","stdpads:TQFP-100_14x14mm_P0.5mm","C1519051",""
+"U2","1","W9825G6KH-6","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","C62246",""
+"U3","1","W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","C97521",""
+"U4, U5, U6, U9","4","74LVC245APW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","C6082",""
+"U7","1","CH340G","stdpads:SOIC-16_3.9mm","C14267",""
+"U8","1","XC6206P332MR","stdpads:SOT-23","C5446",""
+"U10","1","DNP","stdpads:SOT-23-5","",""
+"U11, U14","2","74AHCT1G125GW","stdpads:SOT-353","C12495",""
+"U12","1","74AHCT245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","C173388",""
+"U13","1","DNP","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","",""
+"Y1","1","12M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","C9002",""

Hardware/LCMXO2/gerber/GR8RAM-Edge_Cuts.gm1

@@ -0,0 +1,71 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,9.0.1*
+G04 #@! TF.CreationDate,2025-04-12T23:39:18-04:00*
+G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,1.0*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Profile,NP*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 9.0.1) date 2025-04-12 23:39:18*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 #@! TA.AperFunction,Profile*
+%ADD10C,0.150000*%
+G04 #@! TD*
+G04 APERTURE END LIST*
+D10*
+X57785000Y-80391000D02*
+X46101001Y-92074999D01*
+X143002000Y-132080000D02*
+X139446000Y-132080000D01*
+X45593000Y-129540000D02*
+X45593000Y-93599000D01*
+X48133000Y-132080000D02*
+G75*
+G02*
+X45593000Y-129540000I0J2540000D01*
+G01*
+X138938000Y-139700000D02*
+X74422000Y-139700000D01*
+X145542000Y-129540000D02*
+G75*
+G02*
+X143002000Y-132080000I-2540000J0D01*
+G01*
+X139446000Y-139192000D02*
+G75*
+G02*
+X138938000Y-139700000I-508000J0D01*
+G01*
+X57785000Y-80391000D02*
+G75*
+G02*
+X59309000Y-79883000I1524000J-2032000D01*
+G01*
+X74422000Y-139700000D02*
+G75*
+G02*
+X73914000Y-139192000I0J508000D01*
+G01*
+X48133000Y-132080000D02*
+X73914000Y-132080000D01*
+X143002000Y-79883000D02*
+G75*
+G02*
+X145542000Y-82423000I0J-2540000D01*
+G01*
+X145542000Y-82423000D02*
+X145542000Y-129540000D01*
+X139446000Y-132080000D02*
+X139446000Y-139192000D01*
+X59309000Y-79883000D02*
+X143002000Y-79883000D01*
+X73914000Y-132080000D02*
+X73914000Y-139192000D01*
+X45593000Y-93599000D02*
+G75*
+G02*
+X46101001Y-92074999I2540000J0D01*
+G01*
+M02*

Hardware/LCMXO2/gerber/GR8RAM-F_Paste.gtp

@@ -0,0 +1,622 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,9.0.1*
+G04 #@! TF.CreationDate,2025-04-12T23:39:18-04:00*
+G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,1.0*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Paste,Top*
+G04 #@! TF.FilePolarity,Positive*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 9.0.1) date 2025-04-12 23:39:18*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 Aperture macros list*
+%AMRoundRect*
+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
+20,1,$1+$1,$2,$3,$4,$5,0*
+20,1,$1+$1,$4,$5,$6,$7,0*
+20,1,$1+$1,$6,$7,$8,$9,0*
+20,1,$1+$1,$8,$9,$2,$3,0*%
+G04 Aperture macros list end*
+%ADD10RoundRect,0.080000X-0.555000X0.080000X-0.555000X-0.080000X0.555000X-0.080000X0.555000X0.080000X0*%
+%ADD11RoundRect,0.075000X-0.550000X0.075000X-0.550000X-0.075000X0.550000X-0.075000X0.550000X0.075000X0*%
+%ADD12RoundRect,0.437500X-0.487500X0.437500X-0.487500X-0.437500X0.487500X-0.437500X0.487500X0.437500X0*%
+%ADD13RoundRect,0.387500X-0.387500X0.637500X-0.387500X-0.637500X0.387500X-0.637500X0.387500X0.637500X0*%
+%ADD14RoundRect,0.462500X-0.462500X0.462500X-0.462500X-0.462500X0.462500X-0.462500X0.462500X0.462500X0*%
+%ADD15RoundRect,0.192500X-0.242500X0.192500X-0.242500X-0.192500X0.242500X-0.192500X0.242500X0.192500X0*%
+%ADD16RoundRect,0.177500X0.177500X-0.559500X0.177500X0.559500X-0.177500X0.559500X-0.177500X-0.559500X0*%
+%ADD17RoundRect,0.150000X-0.150000X-0.275000X0.150000X-0.275000X0.150000X0.275000X-0.150000X0.275000X0*%
+%ADD18RoundRect,0.250000X0.250000X0.425000X-0.250000X0.425000X-0.250000X-0.425000X0.250000X-0.425000X0*%
+%ADD19RoundRect,0.200000X-0.475000X0.200000X-0.475000X-0.200000X0.475000X-0.200000X0.475000X0.200000X0*%
+%ADD20RoundRect,0.192500X0.242500X-0.192500X0.242500X0.192500X-0.242500X0.192500X-0.242500X-0.192500X0*%
+%ADD21RoundRect,0.092500X0.092500X-0.592500X0.092500X0.592500X-0.092500X0.592500X-0.092500X-0.592500X0*%
+%ADD22RoundRect,0.150000X-0.275000X0.150000X-0.275000X-0.150000X0.275000X-0.150000X0.275000X0.150000X0*%
+%ADD23RoundRect,0.150000X0.150000X0.275000X-0.150000X0.275000X-0.150000X-0.275000X0.150000X-0.275000X0*%
+%ADD24RoundRect,0.080000X-0.080000X0.380000X-0.080000X-0.380000X0.080000X-0.380000X0.080000X0.380000X0*%
+%ADD25RoundRect,0.250000X0.425000X-0.250000X0.425000X0.250000X-0.425000X0.250000X-0.425000X-0.250000X0*%
+%ADD26RoundRect,0.150000X0.275000X-0.150000X0.275000X0.150000X-0.275000X0.150000X-0.275000X-0.150000X0*%
+%ADD27RoundRect,0.137500X0.487500X0.137500X-0.487500X0.137500X-0.487500X-0.137500X0.487500X-0.137500X0*%
+%ADD28RoundRect,0.057500X0.057500X-0.645000X0.057500X0.645000X-0.057500X0.645000X-0.057500X-0.645000X0*%
+%ADD29RoundRect,0.057500X0.645000X-0.057500X0.645000X0.057500X-0.645000X0.057500X-0.645000X-0.057500X0*%
+%ADD30RoundRect,0.192500X0.192500X0.242500X-0.192500X0.242500X-0.192500X-0.242500X0.192500X-0.242500X0*%
+%ADD31RoundRect,0.224700X-0.224700X-0.437200X0.224700X-0.437200X0.224700X0.437200X-0.224700X0.437200X0*%
+%ADD32RoundRect,0.175000X-0.450000X-0.175000X0.450000X-0.175000X0.450000X0.175000X-0.450000X0.175000X0*%
+%ADD33RoundRect,0.275000X0.375000X0.275000X-0.375000X0.275000X-0.375000X-0.275000X0.375000X-0.275000X0*%
+%ADD34RoundRect,0.137500X-0.137500X0.812500X-0.137500X-0.812500X0.137500X-0.812500X0.137500X0.812500X0*%
+%ADD35RoundRect,0.192500X-0.192500X-0.242500X0.192500X-0.242500X0.192500X0.242500X-0.192500X0.242500X0*%
+%ADD36RoundRect,0.099500X0.625500X0.099500X-0.625500X0.099500X-0.625500X-0.099500X0.625500X-0.099500X0*%
+%ADD37RoundRect,0.275000X-0.375000X-0.275000X0.375000X-0.275000X0.375000X0.275000X-0.375000X0.275000X0*%
+%ADD38RoundRect,0.162500X-0.162500X0.662500X-0.162500X-0.662500X0.162500X-0.662500X0.162500X0.662500X0*%
+%ADD39RoundRect,0.200000X0.200000X0.475000X-0.200000X0.475000X-0.200000X-0.475000X0.200000X-0.475000X0*%
+%ADD40RoundRect,0.250000X-0.250000X-0.425000X0.250000X-0.425000X0.250000X0.425000X-0.250000X0.425000X0*%
+G04 APERTURE END LIST*
+D10*
+X49675000Y-98500000D03*
+X49675000Y-99150000D03*
+X49675000Y-99800000D03*
+X49675000Y-100450000D03*
+D11*
+X49675000Y-101100000D03*
+D12*
+X47000000Y-96000000D03*
+D13*
+X49550000Y-96700000D03*
+D14*
+X47000000Y-98600000D03*
+X47000000Y-101000000D03*
+D13*
+X49550000Y-102900000D03*
+D12*
+X47000000Y-103600000D03*
+D15*
+X104200000Y-119050000D03*
+X104200000Y-120550000D03*
+D16*
+X134493000Y-94615000D03*
+X135763000Y-94615000D03*
+X137033000Y-94615000D03*
+X137033000Y-86995000D03*
+X135763000Y-86995000D03*
+X134493000Y-86995000D03*
+D17*
+X67650000Y-95950000D03*
+X69250000Y-95950000D03*
+D18*
+X76200000Y-128270000D03*
+X74500000Y-128270000D03*
+D17*
+X67650000Y-97450000D03*
+X69250000Y-97450000D03*
+D19*
+X127850000Y-118600000D03*
+X127850000Y-120500000D03*
+D15*
+X126450000Y-107050000D03*
+X126450000Y-108550000D03*
+X103800000Y-106900000D03*
+X103800000Y-108400000D03*
+D20*
+X110800000Y-104800000D03*
+X110800000Y-103300000D03*
+X84300000Y-97900000D03*
+X84300000Y-96400000D03*
+D21*
+X96500000Y-124950000D03*
+X97150000Y-124950000D03*
+X97800000Y-124950000D03*
+X98450000Y-124950000D03*
+X99100000Y-124950000D03*
+X99750000Y-124950000D03*
+X100400000Y-124950000D03*
+X101050000Y-124950000D03*
+X101700000Y-124950000D03*
+X102350000Y-124950000D03*
+X102350000Y-119050000D03*
+X101700000Y-119050000D03*
+X101050000Y-119050000D03*
+X100400000Y-119050000D03*
+X99750000Y-119050000D03*
+X99100000Y-119050000D03*
+X98450000Y-119050000D03*
+X97800000Y-119050000D03*
+X97150000Y-119050000D03*
+X96500000Y-119050000D03*
+D22*
+X105950000Y-114800000D03*
+X105950000Y-116400000D03*
+D18*
+X120826000Y-128270000D03*
+X119126000Y-128270000D03*
+D23*
+X108200000Y-98550000D03*
+X106600000Y-98550000D03*
+D22*
+X108950000Y-114800000D03*
+X108950000Y-116400000D03*
+D20*
+X121200000Y-122350000D03*
+X121200000Y-120850000D03*
+D24*
+X119650000Y-120500000D03*
+X119000000Y-120500000D03*
+X118350000Y-120500000D03*
+X118350000Y-122200000D03*
+X119650000Y-122200000D03*
+D25*
+X132750000Y-125050000D03*
+X132750000Y-123350000D03*
+D26*
+X50736500Y-125158500D03*
+X50736500Y-123558500D03*
+D21*
+X87300000Y-124950000D03*
+X87950000Y-124950000D03*
+X88600000Y-124950000D03*
+X89250000Y-124950000D03*
+X89900000Y-124950000D03*
+X90550000Y-124950000D03*
+X91200000Y-124950000D03*
+X91850000Y-124950000D03*
+X92500000Y-124950000D03*
+X93150000Y-124950000D03*
+X93150000Y-119050000D03*
+X92500000Y-119050000D03*
+X91850000Y-119050000D03*
+X91200000Y-119050000D03*
+X90550000Y-119050000D03*
+X89900000Y-119050000D03*
+X89250000Y-119050000D03*
+X88600000Y-119050000D03*
+X87950000Y-119050000D03*
+X87300000Y-119050000D03*
+D27*
+X137300000Y-120400000D03*
+X137300000Y-119450000D03*
+X137300000Y-118500000D03*
+X135200000Y-118500000D03*
+X135200000Y-120400000D03*
+D28*
+X88050000Y-109062500D03*
+X88550000Y-109062500D03*
+X89050000Y-109062500D03*
+X89550000Y-109062500D03*
+X90050000Y-109062500D03*
+X90550000Y-109062500D03*
+X91050000Y-109062500D03*
+X91550000Y-109062500D03*
+X92050000Y-109062500D03*
+X92550000Y-109062500D03*
+X93050000Y-109062500D03*
+X93550000Y-109062500D03*
+X94050000Y-109062500D03*
+X94550000Y-109062500D03*
+X95050000Y-109062500D03*
+X95550000Y-109062500D03*
+X96050000Y-109062500D03*
+X96550000Y-109062500D03*
+X97050000Y-109062500D03*
+X97550000Y-109062500D03*
+X98050000Y-109062500D03*
+X98550000Y-109062500D03*
+X99050000Y-109062500D03*
+X99550000Y-109062500D03*
+X100050000Y-109062500D03*
+D29*
+X101712500Y-107400000D03*
+X101712500Y-106900000D03*
+X101712500Y-106400000D03*
+X101712500Y-105900000D03*
+X101712500Y-105400000D03*
+X101712500Y-104900000D03*
+X101712500Y-104400000D03*
+X101712500Y-103900000D03*
+X101712500Y-103400000D03*
+X101712500Y-102900000D03*
+X101712500Y-102400000D03*
+X101712500Y-101900000D03*
+X101712500Y-101400000D03*
+X101712500Y-100900000D03*
+X101712500Y-100400000D03*
+X101712500Y-99900000D03*
+X101712500Y-99400000D03*
+X101712500Y-98900000D03*
+X101712500Y-98400000D03*
+X101712500Y-97900000D03*
+X101712500Y-97400000D03*
+X101712500Y-96900000D03*
+X101712500Y-96400000D03*
+X101712500Y-95900000D03*
+X101712500Y-95400000D03*
+D28*
+X100050000Y-93737500D03*
+X99550000Y-93737500D03*
+X99050000Y-93737500D03*
+X98550000Y-93737500D03*
+X98050000Y-93737500D03*
+X97550000Y-93737500D03*
+X97050000Y-93737500D03*
+X96550000Y-93737500D03*
+X96050000Y-93737500D03*
+X95550000Y-93737500D03*
+X95050000Y-93737500D03*
+X94550000Y-93737500D03*
+X94050000Y-93737500D03*
+X93550000Y-93737500D03*
+X93050000Y-93737500D03*
+X92550000Y-93737500D03*
+X92050000Y-93737500D03*
+X91550000Y-93737500D03*
+X91050000Y-93737500D03*
+X90550000Y-93737500D03*
+X90050000Y-93737500D03*
+X89550000Y-93737500D03*
+X89050000Y-93737500D03*
+X88550000Y-93737500D03*
+X88050000Y-93737500D03*
+D29*
+X86387500Y-95400000D03*
+X86387500Y-95900000D03*
+X86387500Y-96400000D03*
+X86387500Y-96900000D03*
+X86387500Y-97400000D03*
+X86387500Y-97900000D03*
+X86387500Y-98400000D03*
+X86387500Y-98900000D03*
+X86387500Y-99400000D03*
+X86387500Y-99900000D03*
+X86387500Y-100400000D03*
+X86387500Y-100900000D03*
+X86387500Y-101400000D03*
+X86387500Y-101900000D03*
+X86387500Y-102400000D03*
+X86387500Y-102900000D03*
+X86387500Y-103400000D03*
+X86387500Y-103900000D03*
+X86387500Y-104400000D03*
+X86387500Y-104900000D03*
+X86387500Y-105400000D03*
+X86387500Y-105900000D03*
+X86387500Y-106400000D03*
+X86387500Y-106900000D03*
+X86387500Y-107400000D03*
+D22*
+X107450000Y-114800000D03*
+X107450000Y-116400000D03*
+D20*
+X110850000Y-109450000D03*
+X110850000Y-107950000D03*
+D25*
+X140100000Y-120400000D03*
+X140100000Y-118700000D03*
+D15*
+X126450000Y-103050000D03*
+X126450000Y-104550000D03*
+D25*
+X130350000Y-120400000D03*
+X130350000Y-118700000D03*
+D30*
+X124400000Y-115350000D03*
+X122900000Y-115350000D03*
+X114400000Y-115350000D03*
+X112900000Y-115350000D03*
+D22*
+X50736500Y-120459500D03*
+X50736500Y-122059500D03*
+D20*
+X58293000Y-94234000D03*
+X58293000Y-92734000D03*
+D22*
+X103400000Y-90700000D03*
+X103400000Y-92300000D03*
+D17*
+X86000000Y-111150000D03*
+X87600000Y-111150000D03*
+D15*
+X67400000Y-119050000D03*
+X67400000Y-120550000D03*
+D21*
+X78100000Y-124950000D03*
+X78750000Y-124950000D03*
+X79400000Y-124950000D03*
+X80050000Y-124950000D03*
+X80700000Y-124950000D03*
+X81350000Y-124950000D03*
+X82000000Y-124950000D03*
+X82650000Y-124950000D03*
+X83300000Y-124950000D03*
+X83950000Y-124950000D03*
+X83950000Y-119050000D03*
+X83300000Y-119050000D03*
+X82650000Y-119050000D03*
+X82000000Y-119050000D03*
+X81350000Y-119050000D03*
+X80700000Y-119050000D03*
+X80050000Y-119050000D03*
+X79400000Y-119050000D03*
+X78750000Y-119050000D03*
+X78100000Y-119050000D03*
+D20*
+X116500000Y-122350000D03*
+X116500000Y-120850000D03*
+D15*
+X95000000Y-119050000D03*
+X95000000Y-120550000D03*
+D26*
+X80950000Y-109300000D03*
+X80950000Y-107700000D03*
+D20*
+X51650000Y-98500000D03*
+X51650000Y-97000000D03*
+D23*
+X95699999Y-91656072D03*
+X94099999Y-91656072D03*
+D30*
+X60833000Y-91376500D03*
+X59333000Y-91376500D03*
+D31*
+X106478750Y-93196250D03*
+X108353750Y-93196250D03*
+D32*
+X135200000Y-123250000D03*
+X135200000Y-125150000D03*
+X137300000Y-124200000D03*
+D33*
+X55399400Y-91650600D03*
+X53199400Y-91650600D03*
+X53199400Y-93350600D03*
+X55399400Y-93350600D03*
+D22*
+X104450000Y-114800000D03*
+X104450000Y-116400000D03*
+D30*
+X124400000Y-90750000D03*
+X122900000Y-90750000D03*
+D34*
+X62103000Y-96458000D03*
+X60833000Y-96458000D03*
+X59563000Y-96458000D03*
+X58293000Y-96458000D03*
+X57023000Y-96458000D03*
+X55753000Y-96458000D03*
+X54483000Y-96458000D03*
+X53213000Y-96458000D03*
+X53213000Y-101408000D03*
+X54483000Y-101408000D03*
+X55753000Y-101408000D03*
+X57023000Y-101408000D03*
+X58293000Y-101408000D03*
+X59563000Y-101408000D03*
+X60833000Y-101408000D03*
+X62103000Y-101408000D03*
+D26*
+X60833000Y-94627500D03*
+X60833000Y-93027500D03*
+D20*
+X63817500Y-101409500D03*
+X63817500Y-99909500D03*
+D17*
+X62166500Y-93027500D03*
+X63766500Y-93027500D03*
+D20*
+X51199400Y-93350600D03*
+X51199400Y-91850600D03*
+D35*
+X88550000Y-91650000D03*
+X90050000Y-91650000D03*
+D15*
+X85800000Y-119050000D03*
+X85800000Y-120550000D03*
+D20*
+X82800000Y-104400000D03*
+X82800000Y-102900000D03*
+D36*
+X124400000Y-113450000D03*
+X124400000Y-112650000D03*
+X124400000Y-111850000D03*
+X124400000Y-111050000D03*
+X124400000Y-110250000D03*
+X124400000Y-109450000D03*
+X124400000Y-108650000D03*
+X124400000Y-107850000D03*
+X124400000Y-107050000D03*
+X124400000Y-106250000D03*
+X124400000Y-105450000D03*
+X124400000Y-104650000D03*
+X124400000Y-103850000D03*
+X124400000Y-103050000D03*
+X124400000Y-102250000D03*
+X124400000Y-101450000D03*
+X124400000Y-100650000D03*
+X124400000Y-99850000D03*
+X124400000Y-99050000D03*
+X124400000Y-98250000D03*
+X124400000Y-97450000D03*
+X124400000Y-96650000D03*
+X124400000Y-95850000D03*
+X124400000Y-95050000D03*
+X124400000Y-94250000D03*
+X124400000Y-93450000D03*
+X124400000Y-92650000D03*
+X112900000Y-92650000D03*
+X112900000Y-93450000D03*
+X112900000Y-94250000D03*
+X112900000Y-95050000D03*
+X112900000Y-95850000D03*
+X112900000Y-96650000D03*
+X112900000Y-97450000D03*
+X112900000Y-98250000D03*
+X112900000Y-99050000D03*
+X112900000Y-99850000D03*
+X112900000Y-100650000D03*
+X112900000Y-101450000D03*
+X112900000Y-102250000D03*
+X112900000Y-103050000D03*
+X112900000Y-103850000D03*
+X112900000Y-104650000D03*
+X112900000Y-105450000D03*
+X112900000Y-106250000D03*
+X112900000Y-107050000D03*
+X112900000Y-107850000D03*
+X112900000Y-108650000D03*
+X112900000Y-109450000D03*
+X112900000Y-110250000D03*
+X112900000Y-111050000D03*
+X112900000Y-111850000D03*
+X112900000Y-112650000D03*
+X112900000Y-113450000D03*
+D17*
+X67650000Y-98950000D03*
+X69250000Y-98950000D03*
+D24*
+X115000000Y-120500000D03*
+X114350000Y-120500000D03*
+X113700000Y-120500000D03*
+X113700000Y-122200000D03*
+X115000000Y-122200000D03*
+D15*
+X103800000Y-96900000D03*
+X103800000Y-98400000D03*
+D37*
+X106000000Y-103350000D03*
+X108200000Y-103350000D03*
+X108200000Y-101650000D03*
+X106000000Y-101650000D03*
+D21*
+X68900000Y-124950000D03*
+X69550000Y-124950000D03*
+X70200000Y-124950000D03*
+X70850000Y-124950000D03*
+X71500000Y-124950000D03*
+X72150000Y-124950000D03*
+X72800000Y-124950000D03*
+X73450000Y-124950000D03*
+X74100000Y-124950000D03*
+X74750000Y-124950000D03*
+X74750000Y-119050000D03*
+X74100000Y-119050000D03*
+X73450000Y-119050000D03*
+X72800000Y-119050000D03*
+X72150000Y-119050000D03*
+X71500000Y-119050000D03*
+X70850000Y-119050000D03*
+X70200000Y-119050000D03*
+X69550000Y-119050000D03*
+X68900000Y-119050000D03*
+D17*
+X86000000Y-113150000D03*
+X87600000Y-113150000D03*
+D20*
+X84300000Y-104400000D03*
+X84300000Y-102900000D03*
+D15*
+X104050000Y-101650000D03*
+X104050000Y-103150000D03*
+D30*
+X114400000Y-90750000D03*
+X112900000Y-90750000D03*
+D18*
+X137160000Y-128270000D03*
+X135460000Y-128270000D03*
+D38*
+X81026000Y-97061000D03*
+X79756000Y-97061000D03*
+X78486000Y-97061000D03*
+X77216000Y-97061000D03*
+X77216000Y-104361000D03*
+X78486000Y-104361000D03*
+X79756000Y-104361000D03*
+X81026000Y-104361000D03*
+D39*
+X108346250Y-95296250D03*
+X106446250Y-95296250D03*
+D17*
+X106600000Y-100050000D03*
+X108200000Y-100050000D03*
+X118050000Y-118700000D03*
+X119650000Y-118700000D03*
+D30*
+X55400000Y-90000600D03*
+X53900000Y-90000600D03*
+X99550000Y-111150000D03*
+X98050000Y-111150000D03*
+D15*
+X126450000Y-92650000D03*
+X126450000Y-94150000D03*
+D25*
+X130350000Y-125050000D03*
+X130350000Y-123350000D03*
+D22*
+X110450000Y-114800000D03*
+X110450000Y-116400000D03*
+D20*
+X103800000Y-95400000D03*
+X103800000Y-93900000D03*
+D22*
+X63817500Y-95656500D03*
+X63817500Y-97256500D03*
+X101900000Y-90700000D03*
+X101900000Y-92300000D03*
+X104900000Y-90700000D03*
+X104900000Y-92300000D03*
+D23*
+X116600000Y-118700000D03*
+X115000000Y-118700000D03*
+D30*
+X98550000Y-91650000D03*
+X97050000Y-91650000D03*
+D40*
+X115394000Y-128270000D03*
+X117094000Y-128270000D03*
+D21*
+X105700000Y-124950000D03*
+X106350000Y-124950000D03*
+X107000000Y-124950000D03*
+X107650000Y-124950000D03*
+X108300000Y-124950000D03*
+X108950000Y-124950000D03*
+X109600000Y-124950000D03*
+X110250000Y-124950000D03*
+X110900000Y-124950000D03*
+X111550000Y-124950000D03*
+X111550000Y-119050000D03*
+X110900000Y-119050000D03*
+X110250000Y-119050000D03*
+X109600000Y-119050000D03*
+X108950000Y-119050000D03*
+X108300000Y-119050000D03*
+X107650000Y-119050000D03*
+X107000000Y-119050000D03*
+X106350000Y-119050000D03*
+X105700000Y-119050000D03*
+D17*
+X55650000Y-114650000D03*
+X57250000Y-114650000D03*
+D15*
+X84300000Y-107400000D03*
+X84300000Y-108900000D03*
+D25*
+X140100000Y-125050000D03*
+X140100000Y-123350000D03*
+D35*
+X89550000Y-111150000D03*
+X91050000Y-111150000D03*
+D25*
+X132750000Y-120400000D03*
+X132750000Y-118700000D03*
+D15*
+X76600000Y-119050000D03*
+X76600000Y-120550000D03*
+X126450000Y-111850000D03*
+X126450000Y-113350000D03*
+M02*

Hardware/LCMXO2/gerber/GR8RAM-job.gbrjob

@@ -0,0 +1,164 @@
+{
+  "Header": {
+    "GenerationSoftware": {
+      "Vendor": "KiCad",
+      "Application": "Pcbnew",
+      "Version": "9.0.1"
+    },
+    "CreationDate": "2025-04-12T23:39:18-04:00"
+  },
+  "GeneralSpecs": {
+    "ProjectId": {
+      "Name": "GR8RAM",
+      "GUID": "47523852-414d-42e6-9b69-6361645f7063",
+      "Revision": "1.0"
+    },
+    "Size": {
+      "X": 100.099,
+      "Y": 59.967
+    },
+    "LayerNumber": 4,
+    "BoardThickness": 1.6108,
+    "Finish": "None"
+  },
+  "DesignRules": [
+    {
+      "Layers": "Outer",
+      "PadToPad": 0.15,
+      "PadToTrack": 0.15,
+      "TrackToTrack": 0.15,
+      "MinLineWidth": 0.15,
+      "TrackToRegion": 0.15,
+      "RegionToRegion": 0.15
+    },
+    {
+      "Layers": "Inner",
+      "PadToPad": 0.15,
+      "PadToTrack": 0.15,
+      "TrackToTrack": 0.15,
+      "TrackToRegion": 0.1524,
+      "RegionToRegion": 0.1524
+    }
+  ],
+  "FilesAttributes": [
+    {
+      "Path": "GR8RAM-F_Cu.gtl",
+      "FileFunction": "Copper,L1,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "GR8RAM-In1_Cu.g1",
+      "FileFunction": "Copper,L5,Inr",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "GR8RAM-In2_Cu.g2",
+      "FileFunction": "Copper,L7,Inr",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "GR8RAM-B_Cu.gbl",
+      "FileFunction": "Copper,L4,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "GR8RAM-F_Paste.gtp",
+      "FileFunction": "SolderPaste,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "GR8RAM-F_Silkscreen.gto",
+      "FileFunction": "Legend,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "GR8RAM-B_Silkscreen.gbo",
+      "FileFunction": "Legend,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "GR8RAM-F_Mask.gts",
+      "FileFunction": "SolderMask,Top",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "GR8RAM-B_Mask.gbs",
+      "FileFunction": "SolderMask,Bot",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "GR8RAM-Edge_Cuts.gm1",
+      "FileFunction": "Profile",
+      "FilePolarity": "Positive"
+    }
+  ],
+  "MaterialStackup": [
+    {
+      "Type": "Legend",
+      "Name": "Top Silk Screen"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Top Solder Paste"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Top Solder Mask"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "F.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 0.2104,
+      "Material": "FR4",
+      "Name": "F.Cu/In1.Cu",
+      "Notes": "Type: dielectric layer 1 (from F.Cu to In1.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.0175,
+      "Name": "In1.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 1.065,
+      "Material": "FR4",
+      "Name": "In1.Cu/In2.Cu",
+      "Notes": "Type: dielectric layer 2 (from In1.Cu to In2.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.0175,
+      "Name": "In2.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 0.2104,
+      "Material": "FR4",
+      "Name": "In2.Cu/B.Cu",
+      "Notes": "Type: dielectric layer 3 (from In2.Cu to B.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "B.Cu"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Bottom Solder Mask"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Bottom Solder Paste"
+    },
+    {
+      "Type": "Legend",
+      "Name": "Bottom Silk Screen"
+    }
+  ]
+}

Hardware/LCMXO2/gerber/GR8RAM-top-pos.JUMPER.csv

@@ -0,0 +1,95 @@
+Ref,Val,Package,MidX,MidY,Rotation,Side
+"C1","10u","C_0805",136.310000,-128.270000,180.000000,top
+"C2","10u","C_0805",119.976000,-128.270000,180.000000,top
+"C3","10u","C_0805",116.244000,-128.270000,0.000000,top
+"C4","10u","C_0805",75.350000,-128.270000,180.000000,top
+"C5","2u2","C_0603",113.650000,-90.750000,180.000000,top
+"C6","2u2","C_0603",51.650000,-97.750000,90.000000,top
+"C7","10u","C_0805",140.100000,-124.200000,90.000000,top
+"C8","22p","C_0603",51.199400,-92.600600,90.000000,top
+"C9","22p","C_0603",54.650000,-90.000600,180.000000,top
+"C10","10u","C_0805",132.750000,-124.200000,90.000000,top
+"C11","10u","C_0805",130.350000,-124.200000,90.000000,top
+"C12","2u2","C_0603",123.650000,-90.750000,180.000000,top
+"C13","2u2","C_0603",76.600000,-119.800000,-90.000000,top
+"C14","2u2","C_0603",85.800000,-119.800000,-90.000000,top
+"C15","2u2","C_0603",95.000000,-119.800000,-90.000000,top
+"C16","2u2","C_0603",104.200000,-119.800000,-90.000000,top
+"C17","2u2","C_0603",58.293000,-93.484000,90.000000,top
+"C18","2u2","C_0603",82.800000,-103.650000,90.000000,top
+"C19","2u2","C_0603",84.300000,-108.150000,-90.000000,top
+"C20","2u2","C_0603",103.800000,-94.650000,90.000000,top
+"C21","2u2","C_0603",90.300000,-111.150000,0.000000,top
+"C22","2u2","C_0603",98.800000,-111.150000,180.000000,top
+"C23","2u2","C_0603",103.800000,-107.650000,-90.000000,top
+"C24","2u2","C_0603",103.800000,-97.650000,-90.000000,top
+"C25","2u2","C_0603",97.800000,-91.650000,180.000000,top
+"C26","2u2","C_0603",89.300000,-91.650000,0.000000,top
+"C27","2u2","C_0603",84.300000,-97.150000,90.000000,top
+"C28","2u2","C_0603",123.650000,-115.350000,180.000000,top
+"C29","2u2","C_0603",126.450000,-112.600000,-90.000000,top
+"C30","2u2","C_0603",126.450000,-107.800000,-90.000000,top
+"C31","2u2","C_0603",126.450000,-103.800000,-90.000000,top
+"C32","2u2","C_0603",126.450000,-93.400000,-90.000000,top
+"C33","2u2","C_0603",110.800000,-104.050000,90.000000,top
+"C34","2u2","C_0603",110.850000,-108.700000,90.000000,top
+"C35","2u2","C_0603",113.650000,-115.350000,180.000000,top
+"C36","10u","C_0805",140.100000,-119.550000,90.000000,top
+"C37","10u","C_0805",132.750000,-119.550000,90.000000,top
+"C38","10u","C_0805",130.350000,-119.550000,90.000000,top
+"C39","2u2","C_0603",116.500000,-121.600000,90.000000,top
+"C40","2u2","C_0603",63.817500,-100.659500,90.000000,top
+"C41","22p","C_0603",60.083000,-91.376500,180.000000,top
+"C42","2u2","C_0603",121.200000,-121.600000,90.000000,top
+"C43","2u2","C_0603",104.050000,-102.400000,-90.000000,top
+"C44","2u2","C_0603",84.300000,-103.650000,90.000000,top
+"C45","2u2","C_0603",67.400000,-119.800000,-90.000000,top
+"D1","Amber","LED_0805",107.416250,-93.196250,0.000000,top
+"FID1","Fiducial","Fiducial",143.002000,-82.423000,-90.000000,top
+"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
+"FID3","Fiducial","Fiducial",59.309000,-82.423000,90.000000,top
+"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
+"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
+"J2","microUSB","USB_Micro-B_Amphenol_10118192-0001",48.300000,-99.800000,-90.000000,top
+"R1","0","R_0805",127.850000,-119.550000,-90.000000,top
+"R2","47","R_0603",107.400000,-98.550000,180.000000,top
+"R3","DNP","R_0603",107.400000,-100.050000,0.000000,top
+"R4","10k","R_0603",50.736500,-124.358500,90.000000,top
+"R5","47","R_0603",60.833000,-93.827500,90.000000,top
+"R6","10k","R_0603",50.736500,-121.259500,-90.000000,top
+"R7","DNP","R_0603",63.817500,-96.456500,-90.000000,top
+"R8","DNP","R_0603",62.966500,-93.027500,0.000000,top
+"R9","47","R_0603",80.950000,-108.500000,90.000000,top
+"R10","47","R_0603",104.450000,-115.600000,-90.000000,top
+"R11","47","R_0603",105.950000,-115.600000,-90.000000,top
+"R12","DNP","R_0603",56.450000,-114.650000,0.000000,top
+"R13","47","R_0603",107.450000,-115.600000,-90.000000,top
+"R14","3k3","R_0603",115.800000,-118.700000,180.000000,top
+"R15","3k3","R_0603",86.800000,-113.150000,0.000000,top
+"R16","3k3","R_0603",118.850000,-118.700000,0.000000,top
+"R17","10k","R_0603",68.450000,-97.450000,0.000000,top
+"R18","DNP","R_0603",68.450000,-98.950000,0.000000,top
+"R19","DNP","R_0603",68.450000,-95.950000,0.000000,top
+"R20","220","R_0805",107.396250,-95.296250,180.000000,top
+"R21","47","R_0603",108.950000,-115.600000,-90.000000,top
+"R22","47","R_0603",110.450000,-115.600000,-90.000000,top
+"R23","3k3","R_0603",86.800000,-111.150000,0.000000,top
+"R24","3k3","R_0603",94.899999,-91.656072,180.000000,top
+"R25","10k","R_0603",103.400000,-91.500000,-90.000000,top
+"R26","10k","R_0603",104.900000,-91.500000,-90.000000,top
+"R27","10k","R_0603",101.900000,-91.500000,-90.000000,top
+"SW1","FW","SW_DIP_SPSTx03_Slide_DSHP03TS_P1.27mm",135.763000,-90.805000,0.000000,top
+"U1","LCMXO2-640HC-4TG100C","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,0.000000,top
+"U2","W9825G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,90.000000,top
+"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
+"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
+"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
+"U6","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
+"U7","CH340G","SOIC-16_3.9mm",57.658000,-98.933000,180.000000,top
+"U8","XC6206P332MR","SOT-23",136.250000,-124.200000,180.000000,top
+"U9","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
+"U11","74AHCT1G125GW","SOT-353",119.000000,-121.350000,180.000000,top
+"U12","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",71.825000,-122.000000,0.000000,top
+"U13","DNP","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
+"U14","74AHCT1G125GW","SOT-353",114.350000,-121.350000,180.000000,top
+"Y1","12M","Crystal_SMD_3225-4Pin_3.2x2.5mm",54.299400,-92.500600,180.000000,top

Hardware/LCMXO2/gerber/GR8RAM-top-pos.VCORE.csv

@@ -0,0 +1,95 @@
+Ref,Val,Package,MidX,MidY,Rotation,Side
+"C1","10u","C_0805",136.310000,-128.270000,180.000000,top
+"C2","10u","C_0805",119.976000,-128.270000,180.000000,top
+"C3","10u","C_0805",116.244000,-128.270000,0.000000,top
+"C4","10u","C_0805",75.350000,-128.270000,180.000000,top
+"C5","2u2","C_0603",113.650000,-90.750000,180.000000,top
+"C6","2u2","C_0603",51.650000,-97.750000,90.000000,top
+"C7","10u","C_0805",140.100000,-124.200000,90.000000,top
+"C8","22p","C_0603",51.199400,-92.600600,90.000000,top
+"C9","22p","C_0603",54.650000,-90.000600,180.000000,top
+"C10","10u","C_0805",132.750000,-124.200000,90.000000,top
+"C11","10u","C_0805",130.350000,-124.200000,90.000000,top
+"C12","2u2","C_0603",123.650000,-90.750000,180.000000,top
+"C13","2u2","C_0603",76.600000,-119.800000,-90.000000,top
+"C14","2u2","C_0603",85.800000,-119.800000,-90.000000,top
+"C15","2u2","C_0603",95.000000,-119.800000,-90.000000,top
+"C16","2u2","C_0603",104.200000,-119.800000,-90.000000,top
+"C17","2u2","C_0603",58.293000,-93.484000,90.000000,top
+"C18","2u2","C_0603",82.800000,-103.650000,90.000000,top
+"C19","2u2","C_0603",84.300000,-108.150000,-90.000000,top
+"C20","2u2","C_0603",103.800000,-94.650000,90.000000,top
+"C21","2u2","C_0603",90.300000,-111.150000,0.000000,top
+"C22","2u2","C_0603",98.800000,-111.150000,180.000000,top
+"C23","2u2","C_0603",103.800000,-107.650000,-90.000000,top
+"C24","2u2","C_0603",103.800000,-97.650000,-90.000000,top
+"C25","2u2","C_0603",97.800000,-91.650000,180.000000,top
+"C26","2u2","C_0603",89.300000,-91.650000,0.000000,top
+"C27","2u2","C_0603",84.300000,-97.150000,90.000000,top
+"C28","2u2","C_0603",123.650000,-115.350000,180.000000,top
+"C29","2u2","C_0603",126.450000,-112.600000,-90.000000,top
+"C30","2u2","C_0603",126.450000,-107.800000,-90.000000,top
+"C31","2u2","C_0603",126.450000,-103.800000,-90.000000,top
+"C32","2u2","C_0603",126.450000,-93.400000,-90.000000,top
+"C33","2u2","C_0603",110.800000,-104.050000,90.000000,top
+"C34","2u2","C_0603",110.850000,-108.700000,90.000000,top
+"C35","2u2","C_0603",113.650000,-115.350000,180.000000,top
+"C36","10u","C_0805",140.100000,-119.550000,90.000000,top
+"C37","10u","C_0805",132.750000,-119.550000,90.000000,top
+"C38","10u","C_0805",130.350000,-119.550000,90.000000,top
+"C39","2u2","C_0603",116.500000,-121.600000,90.000000,top
+"C40","2u2","C_0603",63.817500,-100.659500,90.000000,top
+"C41","22p","C_0603",60.083000,-91.376500,180.000000,top
+"C42","2u2","C_0603",121.200000,-121.600000,90.000000,top
+"C43","2u2","C_0603",104.050000,-102.400000,-90.000000,top
+"C44","2u2","C_0603",84.300000,-103.650000,90.000000,top
+"C45","2u2","C_0603",67.400000,-119.800000,-90.000000,top
+"D1","Amber","LED_0805",107.416250,-93.196250,0.000000,top
+"FID1","Fiducial","Fiducial",143.002000,-82.423000,-90.000000,top
+"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
+"FID3","Fiducial","Fiducial",59.309000,-82.423000,90.000000,top
+"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
+"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
+"J2","microUSB","USB_Micro-B_Amphenol_10118192-0001",48.300000,-99.800000,-90.000000,top
+"R2","47","R_0603",107.400000,-98.550000,180.000000,top
+"R3","DNP","R_0603",107.400000,-100.050000,0.000000,top
+"R4","10k","R_0603",50.736500,-124.358500,90.000000,top
+"R5","47","R_0603",60.833000,-93.827500,90.000000,top
+"R6","10k","R_0603",50.736500,-121.259500,-90.000000,top
+"R7","DNP","R_0603",63.817500,-96.456500,-90.000000,top
+"R8","DNP","R_0603",62.966500,-93.027500,0.000000,top
+"R9","47","R_0603",80.950000,-108.500000,90.000000,top
+"R10","47","R_0603",104.450000,-115.600000,-90.000000,top
+"R11","47","R_0603",105.950000,-115.600000,-90.000000,top
+"R12","DNP","R_0603",56.450000,-114.650000,0.000000,top
+"R13","47","R_0603",107.450000,-115.600000,-90.000000,top
+"R14","3k3","R_0603",115.800000,-118.700000,180.000000,top
+"R15","3k3","R_0603",86.800000,-113.150000,0.000000,top
+"R16","3k3","R_0603",118.850000,-118.700000,0.000000,top
+"R17","10k","R_0603",68.450000,-97.450000,0.000000,top
+"R18","DNP","R_0603",68.450000,-98.950000,0.000000,top
+"R19","DNP","R_0603",68.450000,-95.950000,0.000000,top
+"R20","220","R_0805",107.396250,-95.296250,180.000000,top
+"R21","47","R_0603",108.950000,-115.600000,-90.000000,top
+"R22","47","R_0603",110.450000,-115.600000,-90.000000,top
+"R23","3k3","R_0603",86.800000,-111.150000,0.000000,top
+"R24","3k3","R_0603",94.899999,-91.656072,180.000000,top
+"R25","10k","R_0603",103.400000,-91.500000,-90.000000,top
+"R26","10k","R_0603",104.900000,-91.500000,-90.000000,top
+"R27","10k","R_0603",101.900000,-91.500000,-90.000000,top
+"SW1","FW","SW_DIP_SPSTx03_Slide_DSHP03TS_P1.27mm",135.763000,-90.805000,0.000000,top
+"U1","LCMXO2-640HC-4TG100C","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,0.000000,top
+"U2","W9825G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,90.000000,top
+"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
+"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
+"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
+"U6","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
+"U7","CH340G","SOIC-16_3.9mm",57.658000,-98.933000,180.000000,top
+"U8","XC6206P332MR","SOT-23",136.250000,-124.200000,180.000000,top
+"U9","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
+"U10","DNP","SOT-23-5",136.250000,-119.450000,90.000000,top
+"U11","74AHCT1G125GW","SOT-353",119.000000,-121.350000,180.000000,top
+"U12","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",71.825000,-122.000000,0.000000,top
+"U13","DNP","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
+"U14","74AHCT1G125GW","SOT-353",114.350000,-121.350000,180.000000,top
+"Y1","12M","Crystal_SMD_3225-4Pin_3.2x2.5mm",54.299400,-92.500600,180.000000,top

Hardware/LCMXO2/gerber/GR8RAM-top-pos.csv

@@ -0,0 +1,96 @@
+Ref,Val,Package,MidX,MidY,Rotation,Side
+"C1","10u","C_0805",136.310000,-128.270000,180.000000,top
+"C2","10u","C_0805",119.976000,-128.270000,180.000000,top
+"C3","10u","C_0805",116.244000,-128.270000,0.000000,top
+"C4","10u","C_0805",75.350000,-128.270000,180.000000,top
+"C5","2u2","C_0603",113.650000,-90.750000,180.000000,top
+"C6","2u2","C_0603",51.650000,-97.750000,90.000000,top
+"C7","10u","C_0805",140.100000,-124.200000,90.000000,top
+"C8","22p","C_0603",51.199400,-92.600600,90.000000,top
+"C9","22p","C_0603",54.650000,-90.000600,180.000000,top
+"C10","10u","C_0805",132.750000,-124.200000,90.000000,top
+"C11","10u","C_0805",130.350000,-124.200000,90.000000,top
+"C12","2u2","C_0603",123.650000,-90.750000,180.000000,top
+"C13","2u2","C_0603",76.600000,-119.800000,-90.000000,top
+"C14","2u2","C_0603",85.800000,-119.800000,-90.000000,top
+"C15","2u2","C_0603",95.000000,-119.800000,-90.000000,top
+"C16","2u2","C_0603",104.200000,-119.800000,-90.000000,top
+"C17","2u2","C_0603",58.293000,-93.484000,90.000000,top
+"C18","2u2","C_0603",82.800000,-103.650000,90.000000,top
+"C19","2u2","C_0603",84.300000,-108.150000,-90.000000,top
+"C20","2u2","C_0603",103.800000,-94.650000,90.000000,top
+"C21","2u2","C_0603",90.300000,-111.150000,0.000000,top
+"C22","2u2","C_0603",98.800000,-111.150000,180.000000,top
+"C23","2u2","C_0603",103.800000,-107.650000,-90.000000,top
+"C24","2u2","C_0603",103.800000,-97.650000,-90.000000,top
+"C25","2u2","C_0603",97.800000,-91.650000,180.000000,top
+"C26","2u2","C_0603",89.300000,-91.650000,0.000000,top
+"C27","2u2","C_0603",84.300000,-97.150000,90.000000,top
+"C28","2u2","C_0603",123.650000,-115.350000,180.000000,top
+"C29","2u2","C_0603",126.450000,-112.600000,-90.000000,top
+"C30","2u2","C_0603",126.450000,-107.800000,-90.000000,top
+"C31","2u2","C_0603",126.450000,-103.800000,-90.000000,top
+"C32","2u2","C_0603",126.450000,-93.400000,-90.000000,top
+"C33","2u2","C_0603",110.800000,-104.050000,90.000000,top
+"C34","2u2","C_0603",110.850000,-108.700000,90.000000,top
+"C35","2u2","C_0603",113.650000,-115.350000,180.000000,top
+"C36","10u","C_0805",140.100000,-119.550000,90.000000,top
+"C37","10u","C_0805",132.750000,-119.550000,90.000000,top
+"C38","10u","C_0805",130.350000,-119.550000,90.000000,top
+"C39","2u2","C_0603",116.500000,-121.600000,90.000000,top
+"C40","2u2","C_0603",63.817500,-100.659500,90.000000,top
+"C41","22p","C_0603",60.083000,-91.376500,180.000000,top
+"C42","2u2","C_0603",121.200000,-121.600000,90.000000,top
+"C43","2u2","C_0603",104.050000,-102.400000,-90.000000,top
+"C44","2u2","C_0603",84.300000,-103.650000,90.000000,top
+"C45","2u2","C_0603",67.400000,-119.800000,-90.000000,top
+"D1","Amber","LED_0805",107.416250,-93.196250,0.000000,top
+"FID1","Fiducial","Fiducial",143.002000,-82.423000,-90.000000,top
+"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
+"FID3","Fiducial","Fiducial",59.309000,-82.423000,90.000000,top
+"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
+"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
+"J2","microUSB","USB_Micro-B_Amphenol_10118192-0001",48.300000,-99.800000,-90.000000,top
+"R1","0","R_0805",127.850000,-119.550000,-90.000000,top
+"R2","47","R_0603",107.400000,-98.550000,180.000000,top
+"R3","DNP","R_0603",107.400000,-100.050000,0.000000,top
+"R4","10k","R_0603",50.736500,-124.358500,90.000000,top
+"R5","47","R_0603",60.833000,-93.827500,90.000000,top
+"R6","10k","R_0603",50.736500,-121.259500,-90.000000,top
+"R7","DNP","R_0603",63.817500,-96.456500,-90.000000,top
+"R8","DNP","R_0603",62.966500,-93.027500,0.000000,top
+"R9","47","R_0603",80.950000,-108.500000,90.000000,top
+"R10","47","R_0603",104.450000,-115.600000,-90.000000,top
+"R11","47","R_0603",105.950000,-115.600000,-90.000000,top
+"R12","DNP","R_0603",56.450000,-114.650000,0.000000,top
+"R13","47","R_0603",107.450000,-115.600000,-90.000000,top
+"R14","3k3","R_0603",115.800000,-118.700000,180.000000,top
+"R15","3k3","R_0603",86.800000,-113.150000,0.000000,top
+"R16","3k3","R_0603",118.850000,-118.700000,0.000000,top
+"R17","10k","R_0603",68.450000,-97.450000,0.000000,top
+"R18","DNP","R_0603",68.450000,-98.950000,0.000000,top
+"R19","DNP","R_0603",68.450000,-95.950000,0.000000,top
+"R20","220","R_0805",107.396250,-95.296250,180.000000,top
+"R21","47","R_0603",108.950000,-115.600000,-90.000000,top
+"R22","47","R_0603",110.450000,-115.600000,-90.000000,top
+"R23","3k3","R_0603",86.800000,-111.150000,0.000000,top
+"R24","3k3","R_0603",94.899999,-91.656072,180.000000,top
+"R25","10k","R_0603",103.400000,-91.500000,-90.000000,top
+"R26","10k","R_0603",104.900000,-91.500000,-90.000000,top
+"R27","10k","R_0603",101.900000,-91.500000,-90.000000,top
+"SW1","FW","SW_DIP_SPSTx03_Slide_DSHP03TS_P1.27mm",135.763000,-90.805000,0.000000,top
+"U1","LCMXO2-640HC-4TG100C","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,0.000000,top
+"U2","W9825G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,90.000000,top
+"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
+"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
+"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
+"U6","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
+"U7","CH340G","SOIC-16_3.9mm",57.658000,-98.933000,180.000000,top
+"U8","XC6206P332MR","SOT-23",136.250000,-124.200000,180.000000,top
+"U9","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
+"U10","DNP","SOT-23-5",136.250000,-119.450000,90.000000,top
+"U11","74AHCT1G125GW","SOT-353",119.000000,-121.350000,180.000000,top
+"U12","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",71.825000,-122.000000,0.000000,top
+"U13","DNP","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
+"U14","74AHCT1G125GW","SOT-353",114.350000,-121.350000,180.000000,top
+"Y1","12M","Crystal_SMD_3225-4Pin_3.2x2.5mm",54.299400,-92.500600,180.000000,top

Hardware/LCMXO2/gerber/GR8RAM.drl

@@ -0,0 +1,792 @@
+M48
+; DRILL file {KiCad 9.0.1} date 2025-04-12T23:39:18-0400
+; FORMAT={-:-/ absolute / metric / decimal}
+; #@! TF.CreationDate,2025-04-12T23:39:18-04:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,9.0.1
+; #@! TF.FileFunction,MixedPlating,1,4
+FMAT,2
+METRIC
+; #@! TA.AperFunction,Plated,PTH,ViaDrill
+T1C0.300
+; #@! TA.AperFunction,Plated,PTH,ViaDrill
+T2C0.400
+; #@! TA.AperFunction,Plated,PTH,ViaDrill
+T3C0.762
+; #@! TA.AperFunction,Plated,PTH,ComponentDrill
+T4C1.100
+; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
+T5C0.991
+; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
+T6C1.152
+; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
+T7C2.375
+%
+G90
+G05
+T1
+X46.355Y-93.472
+X46.355Y-109.601
+X46.355Y-114.681
+X46.355Y-119.761
+X46.355Y-124.841
+X46.355Y-129.54
+X46.863Y-112.268
+X47.0Y-94.65
+X47.0Y-104.95
+X48.133Y-111.316
+X48.133Y-131.318
+X48.831Y-107.061
+X48.895Y-90.805
+X48.895Y-117.221
+X48.895Y-122.301
+X49.55Y-95.2
+X49.55Y-104.4
+X49.847Y-113.221
+X49.974Y-93.345
+X50.165Y-114.3
+X50.35Y-91.85
+X50.673Y-94.615
+X50.736Y-122.809
+X50.75Y-96.7
+X50.75Y-101.1
+X50.75Y-102.9
+X50.863Y-114.998
+X51.244Y-119.57
+X51.435Y-88.265
+X51.435Y-131.318
+X51.562Y-115.697
+X51.562Y-118.491
+X51.65Y-96.2
+X52.006Y-90.297
+X52.1Y-91.651
+X52.324Y-94.551
+X52.5Y-97.0
+X52.578Y-119.507
+X52.832Y-124.65
+X53.023Y-111.442
+X53.2Y-90.651
+X53.213Y-102.806
+X53.594Y-119.634
+X53.848Y-95.123
+X53.848Y-105.981
+X53.848Y-128.016
+X53.9Y-89.101
+X53.975Y-85.725
+X54.483Y-102.806
+X54.483Y-111.379
+X55.4Y-94.351
+X55.435Y-88.773
+X55.65Y-113.75
+X55.944Y-111.316
+X55.944Y-125.984
+X56.388Y-95.059
+X56.388Y-103.441
+X56.451Y-107.95
+X56.515Y-83.185
+X56.515Y-89.916
+X56.515Y-131.318
+X56.832Y-111.823
+X57.023Y-100.012
+X57.15Y-91.186
+X57.25Y-113.75
+X57.404Y-92.9
+X57.785Y-119.38
+X57.912Y-86.36
+X58.102Y-120.713
+X58.293Y-91.885
+X58.293Y-95.059
+X58.293Y-97.853
+X58.293Y-102.806
+X58.928Y-112.776
+X58.928Y-128.016
+X59.182Y-80.645
+X59.182Y-92.9
+X59.182Y-94.043
+X59.309Y-90.487
+X59.563Y-88.265
+X59.563Y-95.059
+X59.563Y-97.853
+X59.563Y-102.806
+X59.944Y-84.328
+X59.944Y-106.87
+X60.833Y-92.265
+X60.833Y-100.012
+X60.833Y-102.806
+X61.468Y-115.316
+X61.468Y-125.476
+X61.595Y-131.318
+X62.103Y-80.645
+X62.103Y-85.725
+X62.103Y-90.805
+X62.103Y-95.059
+X62.103Y-97.853
+X62.103Y-100.012
+X62.103Y-102.806
+X62.801Y-96.456
+X62.801Y-101.409
+X62.928Y-100.076
+X63.754Y-92.138
+X63.817Y-94.869
+X63.817Y-99.06
+X63.817Y-102.235
+X64.008Y-112.776
+X64.008Y-117.856
+X64.008Y-122.936
+X64.008Y-128.016
+X64.643Y-83.185
+X64.643Y-88.265
+X64.643Y-93.345
+X64.643Y-98.425
+X64.643Y-103.505
+X64.706Y-100.076
+X64.706Y-101.219
+X65.151Y-106.617
+X66.5Y-119.2
+X66.5Y-120.4
+X66.548Y-115.316
+X66.548Y-125.476
+X66.675Y-131.318
+X66.9Y-95.95
+X66.9Y-97.45
+X66.9Y-98.95
+X67.183Y-80.645
+X67.183Y-85.725
+X67.183Y-90.805
+X67.4Y-118.2
+X67.4Y-121.4
+X68.135Y-101.409
+X68.25Y-120.65
+X68.25Y-124.95
+X68.275Y-119.05
+X68.9Y-117.95
+X68.9Y-120.15
+X68.9Y-123.8
+X69.088Y-112.776
+X69.088Y-128.016
+X69.55Y-126.1
+X69.723Y-83.185
+X69.723Y-88.265
+X69.723Y-93.345
+X69.85Y-117.6
+X70.0Y-95.95
+X70.0Y-97.45
+X70.0Y-98.95
+X70.04Y-103.378
+X70.04Y-104.648
+X70.04Y-105.918
+X70.04Y-107.188
+X70.2Y-126.9
+X70.485Y-108.394
+X70.85Y-126.1
+X71.374Y-109.283
+X71.438Y-115.316
+X71.5Y-126.9
+X71.755Y-131.318
+X72.15Y-126.1
+X72.263Y-80.645
+X72.263Y-85.725
+X72.263Y-90.805
+X72.8Y-126.9
+X73.45Y-126.1
+X74.168Y-112.776
+X74.168Y-117.729
+X74.75Y-123.8
+X74.75Y-126.1
+X74.803Y-83.185
+X74.803Y-88.265
+X75.7Y-119.2
+X75.7Y-120.4
+X76.35Y-104.7
+X76.454Y-97.091
+X76.6Y-118.2
+X76.708Y-115.316
+X77.216Y-95.822
+X77.216Y-98.298
+X77.216Y-103.124
+X77.343Y-80.645
+X77.343Y-85.725
+X77.45Y-120.65
+X77.47Y-131.318
+X77.475Y-119.05
+X77.85Y-127.2
+X78.0Y-107.6
+X78.1Y-117.95
+X78.1Y-120.15
+X78.1Y-123.8
+X78.2Y-105.95
+X78.232Y-95.694
+X78.486Y-103.124
+X78.75Y-126.1
+X78.9Y-117.25
+X79.1Y-108.1
+X79.4Y-126.85
+X79.756Y-103.124
+X79.883Y-83.185
+X79.883Y-88.265
+X79.95Y-128.35
+X80.01Y-95.694
+X80.01Y-131.318
+X80.05Y-107.65
+X80.05Y-126.1
+X80.7Y-126.85
+X80.75Y-129.9
+X81.026Y-105.6
+X81.09Y-95.694
+X81.3Y-123.35
+X81.35Y-126.1
+X81.788Y-129.35
+X81.95Y-103.05
+X81.95Y-104.4
+X82.0Y-111.6
+X82.0Y-126.85
+X82.4Y-93.5
+X82.423Y-80.645
+X82.423Y-85.725
+X82.45Y-109.1
+X82.55Y-131.318
+X82.65Y-105.2
+X82.65Y-126.1
+X82.8Y-102.1
+X82.95Y-112.55
+X83.05Y-100.9
+X83.3Y-126.85
+X83.45Y-96.55
+X83.45Y-97.75
+X83.45Y-108.75
+X83.55Y-110.45
+X83.7Y-113.3
+X83.75Y-98.8
+X83.95Y-123.8
+X83.95Y-126.1
+X84.25Y-105.2
+X84.3Y-102.1
+X84.3Y-109.7
+X84.6Y-124.95
+X84.8Y-99.3
+X84.9Y-120.4
+X84.95Y-119.15
+X84.963Y-88.392
+X85.0Y-94.75
+X85.09Y-131.318
+X85.15Y-108.75
+X85.15Y-114.75
+X85.2Y-95.75
+X85.2Y-96.75
+X85.2Y-97.55
+X85.2Y-103.25
+X85.2Y-104.05
+X85.2Y-127.381
+X85.25Y-105.4
+X86.0Y-112.15
+X86.3Y-92.3
+X86.4Y-94.85
+X86.55Y-109.7
+X86.65Y-120.65
+X86.675Y-119.05
+X86.85Y-129.95
+X86.9Y-114.75
+X86.9Y-126.2
+X87.25Y-93.25
+X87.3Y-117.95
+X87.3Y-120.15
+X87.3Y-123.8
+X87.503Y-80.645
+X87.503Y-86.931
+X87.6Y-96.75
+X87.6Y-97.55
+X87.6Y-103.25
+X87.6Y-104.05
+X87.63Y-131.318
+X87.65Y-101.65
+X87.65Y-105.65
+X88.05Y-129.65
+X88.1Y-117.95
+X88.2Y-102.5
+X88.2Y-104.8
+X88.3Y-114.75
+X88.4Y-113.3
+X88.4Y-128.05
+X88.7Y-90.8
+X88.75Y-98.25
+X88.9Y-92.55
+X88.9Y-94.95
+X88.95Y-103.25
+X89.4Y-129.85
+X89.45Y-113.75
+X89.45Y-116.35
+X89.7Y-92.55
+X89.7Y-94.95
+X89.7Y-112.0
+X89.7Y-114.75
+X89.9Y-90.8
+X89.9Y-107.85
+X89.9Y-110.25
+X90.17Y-131.318
+X90.3Y-129.35
+X90.7Y-106.85
+X90.7Y-107.85
+X90.7Y-110.25
+X90.8Y-95.0
+X90.9Y-112.0
+X90.9Y-126.3
+X91.8Y-107.8
+X91.95Y-126.75
+X91.95Y-129.85
+X92.3Y-111.45
+X92.55Y-127.95
+X92.55Y-129.05
+X92.583Y-80.645
+X92.583Y-86.931
+X92.71Y-131.318
+X92.95Y-90.8
+X93.05Y-107.95
+X93.15Y-123.8
+X93.15Y-126.1
+X93.25Y-91.8
+X93.4Y-110.25
+X93.45Y-113.15
+X93.8Y-124.95
+X94.05Y-107.6
+X94.1Y-120.4
+X94.15Y-119.15
+X94.45Y-111.3
+X94.5Y-129.9
+X94.55Y-94.9
+X95.0Y-127.9
+X95.123Y-88.265
+X95.25Y-131.318
+X95.4Y-92.6
+X95.85Y-120.65
+X95.875Y-119.05
+X96.05Y-94.9
+X96.4Y-92.6
+X96.5Y-117.95
+X96.5Y-120.15
+X96.5Y-123.8
+X96.7Y-95.7
+X97.05Y-112.5
+X97.2Y-90.8
+X97.3Y-117.95
+X97.35Y-107.8
+X97.4Y-92.55
+X97.4Y-94.95
+X97.45Y-126.9
+X97.663Y-80.645
+X97.663Y-86.931
+X97.79Y-131.318
+X97.8Y-95.9
+X98.2Y-92.55
+X98.2Y-94.95
+X98.2Y-112.0
+X98.4Y-90.8
+X98.4Y-107.85
+X98.4Y-110.25
+X98.5Y-106.85
+X98.55Y-128.05
+X98.95Y-105.15
+X99.2Y-94.9
+X99.2Y-107.85
+X99.2Y-110.25
+X99.35Y-89.4
+X99.4Y-112.0
+X99.55Y-92.6
+X99.55Y-128.55
+X99.65Y-96.9
+X99.65Y-97.9
+X99.65Y-98.9
+X99.65Y-99.9
+X99.65Y-102.4
+X99.65Y-103.4
+X99.65Y-104.4
+X99.65Y-105.9
+X99.65Y-106.9
+X100.203Y-83.185
+X100.33Y-131.318
+X100.4Y-92.05
+X100.55Y-96.4
+X100.55Y-97.4
+X100.55Y-98.4
+X100.55Y-99.4
+X100.55Y-100.4
+X100.55Y-101.9
+X100.55Y-102.9
+X100.55Y-103.9
+X100.55Y-105.4
+X100.55Y-106.4
+X100.55Y-107.4
+X100.65Y-115.75
+X101.0Y-109.4
+X101.0Y-111.55
+X101.9Y-89.9
+X101.9Y-108.5
+X102.1Y-129.7
+X102.35Y-123.8
+X102.35Y-126.1
+X102.5Y-117.6
+X102.743Y-80.645
+X102.743Y-85.725
+X102.85Y-97.4
+X102.85Y-98.4
+X102.85Y-103.95
+X102.87Y-131.318
+X102.9Y-107.25
+X102.9Y-108.05
+X102.95Y-94.05
+X102.95Y-96.08
+X103.0Y-124.95
+X103.15Y-129.1
+X103.2Y-101.8
+X103.2Y-102.95
+X103.3Y-120.4
+X103.35Y-119.15
+X103.4Y-89.4
+X104.05Y-103.95
+X104.2Y-118.2
+X104.65Y-94.05
+X104.65Y-97.05
+X104.65Y-107.05
+X104.65Y-108.25
+X104.7Y-98.15
+X104.9Y-89.1
+X104.9Y-101.65
+X104.9Y-103.7
+X104.95Y-102.6
+X105.05Y-120.65
+X105.075Y-119.05
+X105.2Y-128.7
+X105.283Y-83.185
+X105.41Y-131.318
+X105.7Y-117.95
+X105.7Y-120.15
+X105.7Y-123.8
+X106.35Y-123.05
+X106.45Y-97.1
+X106.5Y-91.3
+X106.5Y-117.95
+X106.5Y-120.15
+X106.9Y-126.8
+X107.0Y-123.8
+X107.2Y-128.4
+X107.65Y-123.05
+X107.823Y-80.645
+X107.823Y-86.931
+X107.95Y-131.318
+X108.2Y-104.35
+X108.2Y-117.15
+X108.3Y-123.8
+X109.05Y-123.1
+X109.1Y-113.7
+X109.45Y-103.35
+X109.45Y-117.6
+X109.537Y-126.809
+X109.9Y-101.55
+X109.95Y-104.65
+X109.95Y-107.85
+X110.1Y-128.45
+X110.25Y-126.1
+X110.3Y-113.4
+X110.363Y-88.55
+X110.49Y-131.318
+X110.55Y-96.45
+X110.8Y-102.45
+X110.85Y-105.65
+X110.85Y-107.0
+X110.85Y-110.25
+X111.5Y-98.1
+X111.55Y-123.8
+X111.55Y-126.1
+X111.75Y-92.65
+X111.75Y-103.05
+X111.75Y-104.65
+X111.75Y-109.45
+X111.75Y-111.85
+X111.75Y-113.45
+X112.05Y-90.75
+X112.05Y-115.35
+X112.2Y-124.95
+X112.9Y-91.95
+X112.9Y-114.05
+X112.903Y-80.645
+X112.903Y-86.931
+X113.03Y-131.318
+X113.05Y-89.85
+X113.05Y-116.25
+X113.1Y-120.5
+X113.15Y-127.7
+X113.7Y-119.6
+X113.7Y-123.35
+X114.05Y-92.65
+X114.05Y-94.25
+X114.05Y-95.85
+X114.05Y-97.45
+X114.05Y-99.05
+X114.05Y-101.45
+X114.05Y-103.05
+X114.05Y-104.65
+X114.05Y-107.05
+X114.05Y-109.45
+X114.05Y-111.85
+X114.05Y-113.45
+X114.25Y-89.85
+X114.25Y-91.65
+X114.25Y-114.45
+X114.25Y-116.25
+X114.7Y-93.45
+X114.7Y-95.05
+X114.7Y-96.65
+X114.7Y-98.25
+X114.75Y-99.85
+X114.75Y-103.85
+X114.75Y-105.35
+X114.75Y-106.35
+X114.75Y-107.75
+X114.75Y-108.75
+X114.75Y-110.15
+X114.75Y-111.15
+X114.75Y-112.65
+X115.0Y-119.6
+X115.0Y-123.1
+X115.25Y-90.75
+X115.25Y-115.35
+X115.443Y-88.55
+X115.55Y-122.2
+X115.57Y-131.318
+X115.65Y-121.0
+X116.4Y-120.05
+X116.5Y-123.15
+X117.325Y-119.6
+X117.35Y-121.0
+X117.35Y-122.2
+X117.45Y-103.05
+X117.983Y-80.645
+X117.983Y-86.931
+X117.983Y-90.805
+X117.983Y-116.205
+X118.11Y-131.318
+X118.35Y-119.6
+X118.35Y-124.2
+X118.65Y-104.65
+X118.65Y-105.85
+X118.65Y-107.05
+X118.65Y-108.25
+X118.65Y-109.45
+X118.65Y-110.65
+X118.65Y-111.85
+X118.65Y-113.45
+X119.65Y-119.6
+X119.65Y-123.1
+X119.85Y-103.05
+X120.25Y-122.2
+X120.35Y-121.0
+X120.523Y-83.185
+X120.523Y-88.55
+X120.65Y-131.318
+X121.2Y-120.05
+X121.2Y-123.15
+X121.95Y-93.45
+X122.05Y-90.75
+X122.05Y-115.35
+X122.05Y-121.0
+X122.05Y-122.2
+X122.55Y-103.85
+X122.55Y-105.35
+X122.55Y-106.35
+X122.55Y-107.75
+X122.55Y-108.75
+X122.55Y-110.15
+X122.55Y-111.15
+X122.55Y-112.65
+X122.6Y-94.25
+X122.6Y-95.85
+X122.6Y-97.45
+X122.6Y-99.05
+X122.6Y-100.65
+X122.6Y-102.25
+X123.05Y-89.85
+X123.05Y-91.65
+X123.05Y-114.45
+X123.05Y-116.25
+X123.063Y-80.645
+X123.063Y-85.725
+X123.063Y-126.365
+X123.19Y-131.318
+X123.25Y-92.65
+X123.25Y-95.05
+X123.25Y-96.65
+X123.25Y-98.25
+X123.25Y-99.85
+X123.25Y-101.45
+X123.25Y-103.05
+X123.25Y-104.65
+X123.25Y-107.05
+X123.25Y-109.45
+X123.25Y-111.85
+X123.25Y-113.45
+X124.25Y-89.85
+X124.25Y-116.25
+X124.4Y-91.95
+X124.4Y-114.05
+X125.25Y-90.75
+X125.25Y-115.35
+X125.55Y-92.65
+X125.55Y-103.05
+X125.55Y-104.65
+X125.55Y-107.05
+X125.55Y-111.85
+X125.55Y-113.05
+X125.6Y-94.15
+X125.603Y-83.185
+X125.603Y-88.55
+X125.603Y-118.745
+X125.603Y-123.825
+X125.603Y-128.905
+X125.73Y-131.318
+X126.45Y-91.8
+X126.45Y-102.1
+X126.45Y-105.4
+X126.45Y-106.2
+X126.45Y-109.5
+X126.45Y-111.0
+X127.35Y-112.0
+X127.35Y-113.2
+X127.45Y-103.3
+X127.45Y-104.3
+X127.45Y-107.3
+X127.45Y-108.3
+X128.143Y-80.645
+X128.143Y-85.725
+X128.143Y-90.805
+X128.143Y-95.885
+X128.143Y-116.205
+X128.143Y-126.365
+X128.27Y-131.318
+X130.35Y-121.35
+X130.35Y-122.4
+X130.683Y-83.185
+X130.683Y-88.55
+X130.683Y-93.345
+X130.81Y-131.318
+X132.08Y-131.191
+X132.75Y-121.35
+X132.75Y-122.4
+X133.223Y-80.645
+X133.223Y-85.725
+X133.223Y-90.805
+X133.223Y-95.885
+X133.223Y-116.586
+X133.35Y-131.318
+X134.493Y-85.788
+X134.493Y-95.822
+X134.62Y-131.191
+X135.2Y-121.15
+X135.763Y-83.185
+X135.763Y-85.788
+X135.763Y-95.822
+X135.89Y-131.318
+X136.2Y-119.45
+X137.033Y-85.788
+X137.033Y-95.822
+X137.3Y-117.75
+X137.3Y-121.15
+X138.303Y-80.645
+X138.303Y-85.725
+X138.303Y-90.805
+X138.303Y-95.885
+X138.303Y-116.586
+X138.4Y-119.45
+X138.4Y-120.4
+X138.43Y-131.318
+X139.0Y-118.55
+X140.843Y-88.265
+X140.843Y-93.345
+X141.2Y-118.55
+X143.002Y-80.645
+X143.002Y-131.318
+X143.383Y-85.725
+X143.383Y-90.805
+X143.383Y-95.885
+X143.383Y-100.965
+X143.383Y-121.285
+X144.78Y-82.423
+X144.78Y-88.265
+X144.78Y-93.345
+X144.78Y-98.425
+X144.78Y-103.505
+X144.78Y-108.585
+X144.78Y-113.665
+X144.78Y-118.745
+X144.78Y-123.825
+X144.78Y-129.54
+T2
+X73.406Y-128.524
+X74.549Y-129.54
+X76.2Y-129.54
+X77.343Y-128.27
+X85.8Y-118.1
+X95.0Y-118.1
+X95.3Y-106.8
+X114.3Y-128.27
+X115.443Y-129.54
+X117.094Y-129.54
+X119.126Y-129.54
+X120.777Y-129.54
+X121.856Y-128.27
+X126.45Y-95.1
+X126.45Y-114.3
+X126.6Y-118.6
+X126.6Y-120.5
+X127.45Y-92.9
+X127.45Y-93.9
+X127.85Y-117.65
+X129.15Y-118.7
+X129.15Y-120.2
+X129.15Y-123.35
+X129.15Y-124.85
+X130.35Y-117.65
+X130.35Y-126.1
+X131.55Y-118.9
+X131.55Y-120.2
+X131.55Y-123.55
+X131.55Y-124.85
+X132.75Y-117.65
+X132.75Y-126.1
+X134.0Y-118.95
+X134.0Y-120.4
+X134.0Y-123.5
+X134.0Y-124.9
+X135.2Y-122.3
+X135.2Y-126.05
+X135.509Y-127.0
+X135.509Y-129.54
+X137.16Y-127.0
+X138.303Y-128.27
+X138.9Y-123.45
+X140.1Y-122.3
+X141.3Y-123.55
+X141.35Y-120.15
+T3
+X137.16Y-129.794
+T4
+X140.462Y-129.54
+T5
+X55.308Y-124.714
+X55.308Y-124.714
+X56.325Y-117.094
+X56.325Y-117.094
+X57.34Y-124.714
+X57.34Y-124.714
+T6
+X48.133Y-127.0
+X57.531Y-84.201
+X140.462Y-82.423
+X143.002Y-127.0
+T7
+X53.784Y-117.094
+X53.784Y-117.094
+X53.784Y-122.809
+X53.784Y-122.809
+X58.864Y-117.094
+X58.864Y-117.094
+X58.864Y-122.809
+X58.864Y-122.809
+M30

Hardware/LCMXO2/sym-lib-table

@@ -0,0 +1,7 @@
+(sym_lib_table
+  (version 7)
+  (lib (name "GW_RAM")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
+  (lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
+  (lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
+  (lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../../../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
+)

LICENSE

@@ -0,0 +1,20 @@
+Copyright (c) Garrett's Workshop
+
+Rationale
+----------------------------------------
+We at Garrett's Workshop create our products and release their source in
+hopes of encouraging others to contribute and build their own "clones,"
+even selling them and competing with us. One day, GW will be defunct,
+and it would be a shame if our hardware and software die along with GW.
+At the same time, however, we seek to protect our trademark and ensure
+that clones and derivative products do not masquerade as genuine
+Garrett's Workshop products.
+
+License Terms
+----------------------------------------
+This project may be licensed under one of two licenses:
+
+1. You may elect to license this project under CC BY-NC-SA 4.0.
+
+2. You may elect to license this project under CC BY-SA 4.0 ONLY IF
+   you remove all "Garrett's Workshop" trademarks from the project.

Makefile

@@ -0,0 +1,69 @@
+KICAD = /Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli
+LAYERS = F.Cu,In1.Cu,In2.Cu,B.Cu,F.Paste,F.SilkS,B.SilkS,F.Mask,B.Mask,Edge.Cuts
+CHIPTYPE = $(shell echo $@ | cut -f2 -d"/")
+
+PYTHON = python3
+BOM_SCRIPT =  ../GW_KiCADBuild/export_bom.py
+
+F_PCB = $@/../GR8RAM.kicad_pcb
+F_SCH = $@/../GR8RAM.kicad_sch
+F_NETLIST = $@/GR8RAM-NET.xml
+F_BOM = $@/GR8RAM-BOM.csv
+F_POS_N = $@/GR8RAM-top-pos
+F_POS = $(F_POS_N).csv
+F_POS_VCORE = $(F_POS_N).VCORE.csv
+F_POS_JUMPER = $(F_POS_N).JUMPER.csv
+F_ZIP = $@/GR8RAM.4205B.$(CHIPTYPE)-gerber.zip
+F_SCHPDF = $@/GR8RAM.4205B.$(CHIPTYPE)-Schematic.pdf
+F_PCBPDF = $@/GR8RAM.4205B.$(CHIPTYPE)-Placement.pdf
+F_IN1OLD = $@/GR8RAM-In1_Cu.g2
+F_IN1NEW = $@/GR8RAM-In1_Cu.g1
+F_IN2OLD = $@/GR8RAM-In2_Cu.g3
+F_IN2NEW = $@/GR8RAM-In2_Cu.g2
+
+
+OPT_GERBER = -l $(LAYERS) --subtract-soldermask --no-netlist --no-x2
+CMD_GERBER = pcb export gerbers $(OPT_GERBER) -o $@/ $(F_PCB)
+
+CMD_DRILL = pcb export drill -o $@/ $(F_PCB)
+
+CMD_NETLIST = sch export netlist --format kicadxml -o $(F_NETLIST) $(F_SCH)
+
+OPT_POS = --smd-only --units mm --side front --format csv
+CMD_POS = pcb export pos $(OPT_POS) -o $(F_POS) $(F_PCB)
+
+CMD_SCHPDF = sch export pdf --black-and-white --no-background-color -o $(F_SCHPDF) $(F_SCH)
+CMD_PCBPDF = pcb export pdf --black-and-white -l F.Fab,Edge.Cuts -o $(F_PCBPDF) $(F_PCB)
+
+
+.PHONY: all clean \
+		Hardware/LCMXO2 Hardware/LCMXO2/gerber Hardware/LCMXO2/Documentation
+
+all: Hardware/LCMXO2
+clean:
+	rm -fr Hardware/LCMXO2/gerber/ Hardware/LCMXO2/Documentation/
+
+Hardware/LCMXO2: Hardware/LCMXO2/gerber Hardware/LCMXO2/Documentation
+
+Hardware/LCMXO2/gerber:
+	mkdir -p $@
+	$(KICAD) $(CMD_GERBER)
+	mv $(F_IN1NEW) $(F_IN1OLD)
+	mv $(F_IN2NEW) $(F_IN2OLD)
+	$(KICAD) $(CMD_DRILL)
+	$(KICAD) $(CMD_POS)
+	$(KICAD) $(CMD_NETLIST)
+	sed -i '' 's/PosX/MidX/g' $(F_POS)
+	sed -i '' 's/PosY/MidY/g' $(F_POS)
+	sed -i '' 's/Rot/Rotation/g' $(F_POS)
+	$(PYTHON) $(BOM_SCRIPT) $(F_NETLIST) $(F_BOM)
+	cp $(F_POS) $(F_POS_VCORE)
+	cp $(F_POS) $(F_POS_JUMPER)
+	sed -i '' '/"R1"/d' $(F_POS_VCORE)
+	sed -i '' '/"U10"/d' $(F_POS_JUMPER)
+	rm -f $(F_ZIP)
+	zip -r $(F_ZIP) $@/
+Hardware/LCMXO2/Documentation:
+	mkdir -p $@
+	$(KICAD) $(CMD_SCHPDF)
+	$(KICAD) $(CMD_PCBPDF)

cpld/BusInterface.v

@@ -0,0 +1,167 @@
+	module BusInterface(
+		/* Clock signal inputs */
+		input CLK,
+		input PHI0,
+		/* Apple II reset input */
+		input nRES,
+		/* Card select signal inputs */
+		input nDEVSEL,
+		input nIOSEL,
+		input nIOSTRB,
+		/* Buffered address, write enable inputs */
+		input [10:0] BA,
+		input nWE,
+		/* Data bus mux inputs */
+		input [7:0] RDD,
+		input [23:0] Addr,
+		/* Buffered data bus output and BD buffer control */
+		inout [7:0] BD,
+		output nDoutOE,
+		output nDinOE,
+		/* Write data output to slinky registers and RAM controller */
+		output reg [7:0] WRD,
+		/* Bus command enable input from initialization controller */
+		input BusEnable,
+		/* SDRAM command outputs */
+		output reg RAMRD,
+		output reg RAMWR,
+		output reg ROMRD,
+		output reg RAMRef,
+		/* Register command outputs */
+		output reg BankWR,
+		output reg AddrInc,
+		output reg AddrHWR,
+		output reg AddrMWR,
+		output reg AddrLWR,
+		output reg RegReset);
+
+	/* PHI0 synchronization */
+	reg [4:0] PHI0r;
+	always @(negedge CLK) PHI0r[0] <= PHI0;
+	always @(posedge CLK) PHI0r[4:1] <= PHI0r[3:0];
+	wire PHI0rise = !PHI0r[2] &&  PHI0r[1];
+
+	/* Reset synchronization */
+	reg nRESr; always @(negedge PHI0) nRESr <= nRES;
+
+	/* Bus state counter
+	 * S0 - idle/bus disabled
+	 * S1-SB - PHI0
+	 * SC - wait until PHI1
+	 * SD-SF - PHI1 */
+	reg [3:0] S = 0;
+	always @(posedge CLK) begin
+		if (S==4'h0 && BusEnable && PHI0rise) S <= 4'h1;
+		else if (S==4'hC && !PHI0r[2]) S <= 4'hD;
+		else S <= S+4'h1;
+	end
+
+	/* Refresh counter */
+	reg [2:0] RefC;
+	wire [2:0] RefCTC = RefC[2:0]==3'h6;
+	always @(posedge CLK) begin
+		if (RefC==RefCTC) RefC <= 3'h0;
+		else RefC <= RefC+3'h1;
+	end
+
+	/* Register reset command generation */
+	always @(posedge CLK) begin
+		if (S==4'h0 && !BusEnable) RegReset <= 1;
+		else if (S==4'h1) RegReset <= !nRESr;
+	end
+
+	/* Register enable */
+	reg RegEN;
+	always @(posedge CLK) begin 
+		if (RegReset) RegEN <= 0;
+		else if (S==4'h6 && !nIOSEL) RegEN <= 1;
+	end
+
+	/* IOSTRB ROM enable */
+	reg IOROMEN;
+	always @(posedge CLK) begin
+		if (RegReset) IOROMEN <= 0;
+		else if (S==4'h6 && !nIOSEL && BA[10:0]==11'h7FF) IOROMEN <= 0;
+		else if (S==4'h6 && !nIOSEL) IOROMEN <= 1;
+	end
+
+	/* Write data latch */
+	always @(negedge PHI0) WRD[7:0] <= BD[7:0];
+
+	/* Register and RAM write command generation */
+	reg BankWRpre;
+	reg RAMWRpre;
+	reg AddrHWRpre;
+	reg AddrMWRpre;
+	reg AddrLWRpre;
+	always @(posedge CLK) begin
+		if (S==6) begin
+			BankWRpre <=  S==4'h6 && !nDEVSEL && BA[3:0]==4'hF && !nWE;
+			RAMWRpre <=   S==4'h6 && !nDEVSEL && BA[3:0]==4'h3 && !nWE;
+			AddrHWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h2 && !nWE;
+			AddrMWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h1 && !nWE;
+			AddrLWRpre <= S==4'h6 && !nDEVSEL && BA[3:0]==4'h0 && !nWE;
+		end else if (S==0) begin
+			BankWRpre <= 0;
+			RAMWRpre <= 0;
+			AddrHWRpre <= 0;
+			AddrMWRpre <= 0;
+			AddrLWRpre <= 0;
+		end
+		BankWR <=  S==4'hD && BankWRpre && RegEN;
+		RAMWR <=   S==4'hD && RAMWRpre && RegEN;
+		AddrHWR <= S==4'hD && AddrHWRpre && RegEN;
+		AddrMWR <= S==4'hD && AddrMWRpre && RegEN;
+		AddrLWR <= S==4'hD && AddrLWRpre && RegEN;
+	end
+	
+	/* Address increment command generation after RAMWR */
+	always @(posedge CLK) AddrInc <= S==4'hF && RAMWRpre;
+
+	/* RAM read command generation */
+	always @(posedge CLK) begin
+		RAMRD <= S==4'h6 &&  !nDEVSEL && BA[3:0]==4'h3 &&  nWE;
+		ROMRD <= S==4'h6 && (!nIOSEL || (!nIOSTRB && IOROMEN && BA[10:0]!=11'h7FF));
+	end
+
+	/* RAM refresh command generation */
+	always @(posedge CLK) RAMRef <= S==4'h1 && RefCTC;
+
+	/* Data bus output mux */
+	reg [7:0] BDout;
+	reg BDoutLE;
+	always @(posedge CLK) BDoutLE <= S==4'hB;
+	always @(posedge CLK) begin
+		if (BDoutLE) begin
+			if (nDEVSEL) BDout[7:0] <= RDD[7:0];
+			else case (BA[3:0])
+				4'hF: BDout[7:0] <= 0;
+				4'hE: BDout[7:0] <= 0;
+				4'hD: BDout[7:0] <= 0;
+				4'hC: BDout[7:0] <= 0;
+				4'hB: BDout[7:0] <= 0;
+				4'hA: BDout[7:0] <= 0;
+				4'h9: BDout[7:0] <= 0;
+				4'h8: BDout[7:0] <= 0;
+				4'h7: BDout[7:0] <= 8'h10; // Hex 10 (meaning firmware 1.0)
+				4'h6: BDout[7:0] <= 8'h41; // ASCII "B" (meaning rev. B)
+				4'h5: BDout[7:0] <= 8'h05; // Hex 05 (meaning "4205")
+				4'h4: BDout[7:0] <= 8'h47; // ASCII "G" (meaning "GW")
+				4'h3: BDout[7:0] <= RDD[7:0];
+				4'h2: BDout[7:0] <= Addr[23:16];
+				4'h1: BDout[7:0] <= Addr[15:8];
+				4'h0: BDout[7:0] <= Addr[7:0];
+			endcase
+		end
+	end
+
+	/* Card select signal */
+	wire CardSEL = !nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && BA[10:0]!=11'h7FF);
+
+	/* Data bus buffer OE control */
+	assign nDinOE =  !(PHI0 && !nWE);
+	assign nDoutOE = !(CardSEL &&  nWE && PHI0r[4] && PHI0);
+	wire BDOE =       (CardSEL &&  nWE && PHI0r[4]);
+	assign BD[7:0] = BDOE ? BDout[7:0] : 8'bZ;
+
+endmodule

cpld/GR8RAM-LCMXO2.lpf

@@ -0,0 +1,149 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "PHI0" SITE "17" ;
+LOCATE COMP "MISO" SITE "98" ;
+LOCATE COMP "BA[0]" SITE "74" ;
+LOCATE COMP "BA[1]" SITE "78" ;
+LOCATE COMP "BA[2]" SITE "83" ;
+LOCATE COMP "BA[3]" SITE "84" ;
+LOCATE COMP "BA[4]" SITE "4" ;
+LOCATE COMP "BA[5]" SITE "85" ;
+LOCATE COMP "BA[6]" SITE "86" ;
+LOCATE COMP "BA[7]" SITE "87" ;
+LOCATE COMP "BA[8]" SITE "99" ;
+LOCATE COMP "BA[9]" SITE "2" ;
+LOCATE COMP "BA[10]" SITE "3" ;
+LOCATE COMP "BA[11]" SITE "8" ;
+LOCATE COMP "BA[12]" SITE "9" ;
+LOCATE COMP "BA[13]" SITE "10" ;
+LOCATE COMP "BA[14]" SITE "13" ;
+LOCATE COMP "BA[15]" SITE "14" ;
+LOCATE COMP "SW[1]" SITE "64" ;
+LOCATE COMP "SW[2]" SITE "63" ;
+LOCATE COMP "nDEVSEL" SITE "16" ;
+LOCATE COMP "nIOSEL" SITE "15" ;
+LOCATE COMP "nIOSTRB" SITE "18" ;
+LOCATE COMP "nRESin" SITE "20" ;
+LOCATE COMP "nWE" SITE "19" ;
+LOCATE COMP "DQMH" SITE "34" ;
+LOCATE COMP "DQML" SITE "32" ;
+LOCATE COMP "RCKE" SITE "40" ;
+LOCATE COMP "RA[0]" SITE "54" ;
+LOCATE COMP "RA[1]" SITE "59" ;
+LOCATE COMP "RA[2]" SITE "58" ;
+LOCATE COMP "RA[3]" SITE "60" ;
+LOCATE COMP "RA[4]" SITE "51" ;
+LOCATE COMP "RA[5]" SITE "52" ;
+LOCATE COMP "RA[6]" SITE "62" ;
+LOCATE COMP "RA[7]" SITE "57" ;
+LOCATE COMP "RA[8]" SITE "53" ;
+LOCATE COMP "RA[9]" SITE "49" ;
+LOCATE COMP "RA[10]" SITE "47" ;
+LOCATE COMP "RA[11]" SITE "45" ;
+LOCATE COMP "RA[12]" SITE "42" ;
+LOCATE COMP "RBA[0]" SITE "43" ;
+LOCATE COMP "RBA[1]" SITE "48" ;
+LOCATE COMP "FCK" SITE "96" ;
+LOCATE COMP "nFCS" SITE "88" ;
+LOCATE COMP "nCAS" SITE "36" ;
+LOCATE COMP "nDinOE" SITE "77" ;
+LOCATE COMP "nDoutOE" SITE "1" ;
+LOCATE COMP "nIRQout" SITE "12" ;
+LOCATE COMP "nRAS" SITE "37" ;
+LOCATE COMP "nRCS" SITE "41" ;
+LOCATE COMP "nRESout" SITE "7" ;
+LOCATE COMP "nRWE" SITE "35" ;
+LOCATE COMP "MOSI" SITE "97" ;
+LOCATE COMP "BD[0]" SITE "65" ;
+LOCATE COMP "BD[1]" SITE "66" ;
+LOCATE COMP "BD[2]" SITE "67" ;
+LOCATE COMP "BD[3]" SITE "68" ;
+LOCATE COMP "BD[4]" SITE "69" ;
+LOCATE COMP "BD[5]" SITE "70" ;
+LOCATE COMP "BD[6]" SITE "71" ;
+LOCATE COMP "RD[0]" SITE "25" ;
+LOCATE COMP "RD[1]" SITE "24" ;
+LOCATE COMP "RD[2]" SITE "21" ;
+LOCATE COMP "RD[3]" SITE "27" ;
+LOCATE COMP "RD[4]" SITE "28" ;
+LOCATE COMP "RD[5]" SITE "29" ;
+LOCATE COMP "RD[6]" SITE "30" ;
+LOCATE COMP "RD[7]" SITE "31" ;
+LOCATE COMP "BD[7]" SITE "75" ;
+IOBUF PORT "PHI0" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "MISO" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "BA[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "SW[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
+IOBUF PORT "SW[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
+IOBUF PORT "nDEVSEL" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "nIOSEL" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "nIOSTRB" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "nRESin" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "nWE" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
+IOBUF PORT "DQMH" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "DQML" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RCKE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RA[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "FCK" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=24 SLEWRATE=FAST ;
+IOBUF PORT "nFCS" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 ;
+IOBUF PORT "nCAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nDinOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nDoutOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nIRQout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nRAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nRCS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nRESout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
+IOBUF PORT "MOSI" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "BD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER ;
+IOBUF PORT "CLKin" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+LOCATE COMP "CLKin" SITE "38" ;
+LOCATE COMP "RCLK" SITE "39" ;
+IOBUF PORT "RCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=24 SLEWRATE=FAST ;
+VOLTAGE 3.300 V;
+LOCATE COMP "LED" SITE "81" ;
+IOBUF PORT "LED" IO_TYPE=LVCMOS33 DRIVE=24 PULLMODE=NONE ;

cpld/GR8RAM-LCMXO2.mem

@@ -0,0 +1,7 @@
+// Auto-generated by memint 08/19/2023 20:50:21
+#Format=Hex
+#Depth=16
+#Width=8
+#AddrRadix=3
+#DataRadix=3
+#Data

cpld/GR8RAM.sdc

@@ -0,0 +1,2 @@
+create_clock [get_nets CLK] -period 22.558087ns
+create_clock [get_ports PHI0] -period 977ns

cpld/GR8RAM.v

@@ -0,0 +1,190 @@
+module GR8RAM(
+	/* Apple II PHI0 clock */
+	input PHI0,
+	/* 25 MHz crystal oscillator input (not usually mounted) */
+	input CLKin /* synthesis syn_force_pads=1 syn_noprune=1 */,
+	/* LED output */
+	output LED,
+	/* Reset and IRQ */
+	input nRESin,
+	output nRESout,
+	output nIRQout,
+	/* DIP switch inputs */
+	input [2:1] SW,
+	/* Buffered address, write enable, data buses */
+	input [15:0] BA /* synthesis syn_force_pads=1 syn_noprune=1 */,
+	input nWE,
+	inout [7:0] BD,
+	output nDoutOE,
+	output nDinOE,
+	/* Card select signals */
+	input nIOSEL, 
+	input nDEVSEL, 
+	input nIOSTRB,
+	/* SDRAM bus */
+	output RCLK,
+	output [1:0] RBA,
+	output [12:0] RA,
+	output nRCS,
+	output RCKE,
+	output nRAS,
+	output nCAS,
+	output nRWE,
+	output DQML,
+	output DQMH,
+	inout [7:0] RD,
+	/* SPI NOR flash */
+	inout nFCS,
+	output FCK,
+	inout MOSI,
+	input MISO);
+	
+	assign LED = 1;
+	
+	/* Internal clock */
+	wire CLK;
+	defparam OSCH_inst.NOM_FREQ = "44.33";
+	OSCH OSCH_inst(.STDBY(1'b0), .OSC(CLK), .SEDSTDBY());
+
+	/* Apple II bus interface */
+	wire [7:0] BI_WRD;
+	wire BI_RAMRD, BI_ROMRD, BI_RAMWR, BI_RAMRef;
+	wire AddrHWR, AddrMWR, AddrLWR, AddrInc, BankWR, RegReset;
+
+    /* Slinky address and ROM bank registers */
+	wire [23:0] Addr;
+	wire Bank;
+
+    /* Init controller */
+	wire InitDone;
+	wire [2:0] IC_RAMCmd;
+	wire [24:0] IC_Addr;
+	wire [7:0] IC_WRD;
+	wire [1:0] SetSize;
+	wire SetRamFactorEN;
+	wire SetRestoreEN;
+	
+    /* SDRAM controller */
+    wire [7:0] RDD;
+
+	/* Apple II bus interface */
+	BusInterface bi(
+		/* Clock signal inputs */
+		.CLK(CLK),
+		.PHI0(PHI0),
+		/* Apple II reset input */
+		.nRES (nRESin),
+		/* Card select signal inputs */
+		.nDEVSEL(nDEVSEL),
+		.nIOSEL(nIOSEL),
+		.nIOSTRB(nIOSTRB),
+		/* Buffered address, write enable inputs */
+		.BA(BA[10:0]),
+		.nWE(nWE),
+		/* Data bus mux inputs */
+		.RDD(RDD),
+		.Addr(Addr),
+		/* Data bus output and BD buffer control */
+		.BD(BD),
+		.nDoutOE(nDoutOE),
+		.nDinOE(nDinOE),
+		/* Write data output to slinky registers and RAM controller */
+		.WRD(BI_WRD),
+		/* Initialization done input from initialization controller */
+		.BusEnable(InitDone),
+		/* SDRAM command outputs */
+		.RAMRD(BI_RAMRD),
+		.ROMRD(BI_ROMRD),
+		.RAMWR(BI_RAMWR),
+		.RAMRef(BI_RAMRef),
+		/* Register command outputs */
+		.AddrHWR(AddrHWR),
+		.AddrMWR(AddrMWR),
+		.AddrLWR(AddrLWR),
+		.AddrInc(AddrInc),
+		.BankWR(BankWR),
+		.RegReset(RegReset));
+
+
+    /* Slinky address and ROM bank registers */
+	SlinkyRegisters registers(
+		/* Clock signal */
+		.CLK(CLK),
+		/* Slinky/RamFactor mode bit */
+		.SetRamFactorEN(SetRamFactorEN),
+		/* Register command inputs */
+		.AddrHWR(AddrHWR),
+		.AddrMWR(AddrMWR),
+		.AddrLWR(AddrLWR),
+		.AddrInc(AddrInc),
+		.BankWR(BankWR),
+		.RegReset(RegReset),
+		/* Write data input */
+		.WRD(BI_WRD),
+		/* Slinky address register output */
+		.Addr(Addr),
+		/* ROM bank register output */
+		.Bank(Bank));
+
+
+    /* Init controller */
+	InitController ic(
+		/* Clock signal */
+		.CLK(CLK),
+		/* Settings input and outputs */
+		.SW({ RD[0], SW[2:1] }),
+		.SetSize(SetSize),
+		.SetRamFactorEN(SetRamFactorEN),
+		.SetRestoreEN(SetRestoreEN),
+		/* Initialization done and POR outputs */
+		.InitDone(InitDone),
+		/* SDRAM command outputs */
+		.RAMCmd(IC_RAMCmd),
+		.RAMAddr(IC_Addr),
+		/* SDRAM write data output */
+		.WRD(IC_WRD),
+		/* SPI flash bus */
+		.nFCS(nFCS),
+		.FCK(FCK),
+		.MOSI(MOSI),
+		.MISO(MISO));
+
+
+    /* SDRAM controller */
+	SDRAMController ram(
+		/* Clock signal */
+		.CLK(CLK),
+		/* POR input from init controller */
+		.InitDone(InitDone),
+		/* Command inputs from bus interface */
+		.BI_RAMRD(BI_RAMRD),
+		.BI_RAMWR(BI_RAMWR),
+		.BI_RAMRef(BI_RAMRef),
+		.Addr(Addr),
+		.BD(BD),
+		/* Command inputs from init controller */
+		.IC_RAMCmd(IC_RAMCmd),
+		.IC_Addr(IC_Addr),
+		.IC_WRD(IC_WRD),
+		/* SDRAM bus */
+		.RCLK(RCLK),
+		.RBA(RBA),
+		.RA(RA),
+		.nRCS(nRCS),
+		.RCKE(RCKE),
+		.nRAS(nRAS),
+		.nCAS(nCAS),
+		.nRWE(nRWE),
+		.DQML(DQML),
+		.DQMH(DQMH),
+		.RD(RD),
+		/* SDRAM read data */
+		.RDD(RDD));
+
+    /* Reset output is InitDone */
+    assign nRESout = InitDone;
+
+	/* IRQ always disabled */
+	assign nIRQout = 1;
+
+endmodule

cpld/IIci PDS (75)

@@ -0,0 +1,45 @@
+SE/30 PDS (54)
+--------
+(1) CPUCLK
+(32) AD[31:0]
+(3) ALE, nAOE, nDOE
+(2) /RESETin, /RESETout
+(5) /AS, /DS, R/W, SIZ[1:0]
+(5) /DSACK[1:0], /STERM, /BERR, /HALT
+(2) /BR, /BG
+(3) /IPL[2:0]
+(1) /IRQ
+
+SDRAM (29)
+--------
+(4) RCLK[3:0] 
+(15) RBA[1:0], RA[12:0]
+(2) /CS[1:0]
+(4) DQM[3:0]
+(4) CKE, /RAS, /CAS, /WE
+
+SRAM (9)
+--------
+(6) /L2OE, /L2WE, /B[3:0]
+(3) /GCOE, /GSTERM, /GSTERMEN, /GRDOE, /GRDOEEN
+/DCOE
+
+ROM (6)
+--------
+(4) FCK[1:0], /CS[1:0]
+(2) MISO, MOSI
+
+Fast CPU (84)
+--------
+(2) CPUCLK, FPUCLK
+(35) FC[2:0], A[31:0]
+(32) D[31:0]
+(3) /BALOE
+(6) /AS, SIZ[1:0], R/W, /RMC, /CBREQ
+(5) /DSACK[1:0], /CBACK, /HALT, /BERR
+(1) /FSTERMD
+
+Link (10)
+--------
+(2) LCLK, /LSOF
+(8) LD[7:0]

cpld/InitController.v

@@ -0,0 +1,489 @@
+module InitController(
+		/* Clock signal */
+		input CLK,
+		/* Settings input and outputs */
+		input [3:1] SW,
+		output reg [1:0] SetSize,
+		output reg SetRamFactorEN,
+		output reg SetRestoreEN,
+		/* Initialization done and POR outputs */
+		output reg InitDone,
+		/* SDRAM command outputs */
+		output reg [2:0] RAMCmd,
+		output reg [24:0] RAMAddr,
+		/* SDRAM write data output */
+		output reg [7:0] WRD,
+		/* SPI flash bus */
+		inout nFCS,
+		output FCK,
+		inout MOSI,
+		input MISO);
+
+	/* RAM command definitions */
+	`define RC_NOP (3'h0)
+	`define RC_LDM (3'h1)
+	`define RC_ACT (3'h2)
+	`define RC_WR  (3'h3)
+	`define RC_PC  (3'h4)
+	`define RC_Ref (3'h5)
+		
+	/* Init state */
+	reg [12:0] CS = 0;
+	reg [12:0] LS = 0;
+	reg [3:0] IS = 0;
+
+	/* /FCS output */
+	reg FOE = 0;
+	reg nFCSout;
+	wire nFCSin;
+	BB fcs_bb(.I(nFCSout), .T(FOE), .O(nFCSin), .B(nFCS));
+
+	/* FCK output */
+	reg FCKEN;
+	wire FCKout;
+    ODDRX1F fck_oddr(.D0(1'b0), .D1(FCKEN), 
+        .SCLK(CLK), .RST(1'b0), .Q(FCKout));
+	OBZ fck_iobz(.I(FCKout), .T(FOE), .O(FCK));
+
+	/* MOSI output */
+	reg MOSIOE = 0;
+	reg MOSIout;
+	wire MOSIin;
+	BB mosi_bb(.I(MOSIout), .T(MOSIOE), .O(MOSIin), .B(MOSI));
+
+	/* Flash alternate master detect */
+	reg FlashProgDetected;
+	always @(posedge CLK) begin
+		if (IS==0) FlashProgDetected <= 0;
+		else if (!nFCSin) FlashProgDetected <= 1;
+	end
+
+	/* CS (command state) control -- lowest order */
+	wire CSTC = CS[12:0]==13'h103F;
+	always @(posedge CLK) begin
+		if (CSTC) CS[12:0] <= 0;
+		else CS[12:0] <= CS+13'h0001;
+	end
+
+	/* LS (long state) control -- medium order */
+	wire LSTC =
+		IS==0 ? LS[12:0]==13'h003F : // POR pause
+		IS==1 ? LS[12:0]==13'h01FF : // Check to see if flash programmer attached
+		IS==2 ? LS[12:0]==13'h0000 : // Issue flash command
+		IS==3 ? LS[12:0]==13'h0007 : // Load flash to RAM
+		IS==4 ? LS[12:0]==13'h0000 : // End flash command
+		IS==5 ? LS[12:0]==13'h0000 : // Issue flash command
+		IS==6 ? LS[12:0]==13'h1FFF : // Load flash to RAM
+		IS==7 ? LS[12:0]==13'h0000 : // End flash command
+		IS==8 ? LS[12:0]==13'h0000 : // Operation mode
+		IS==9 ? LS[12:0]==13'h0000 : // Inhibit mode
+		1; // Other
+	always @(posedge CLK) begin
+		if (CSTC) begin
+			if (LSTC) LS <= 0;
+			else LS <= LS+13'h0001;
+		end
+	end
+
+	/* IS (init state) control -- high order */
+	always @(posedge CLK) begin
+		if (LSTC && CSTC) case (IS)
+			4'h0: IS <= 4'h1;
+			4'h1: IS <= FlashProgDetected ? 4'h9 : 4'h2;
+			4'h2, 4'h3, 4'h4, 4'h5, 4'h6, 4'h7: IS <= IS+4'h1;
+			4'h8: IS <= 4'h8;
+			4'h9: IS <= 4'h9;
+			default: IS <= 4'h9;
+		endcase
+	end
+
+	/* Apple II reset output control */
+	always @(posedge CLK) InitDone <= IS==8;
+	
+	/* RAM write address generation */
+	wire [24:0] RAMDriverAddr = 25'h1000000;
+	wire [24:0] RAMImageAddr = 25'h0000000;
+	always @(posedge CLK) RAMAddr[24:0] <=
+		IS==3 ? { RAMDriverAddr[24:13],  LS[2:0], CS[11:2] } :
+		IS==6 ? {  RAMImageAddr[24:23], LS[12:0], CS[11:2] } :
+		25'h1FFFFFF;
+
+	/* Flash driver address */
+	wire [23:0] FlashDriverRFAddr = 24'hFF8000;
+	wire [23:0] FlashDriverSlinkyAddr = 24'hFF0000;
+	wire [23:0] FlashDriverAddr =
+		SetRamFactorEN ? FlashDriverRFAddr : FlashDriverSlinkyAddr;
+
+	/* Flash image address */
+	wire [23:0] FlashImageRF1MBAddr = 24'h900000;
+	wire [23:0] FlashImageSlinky1MBAddr = 24'h800000;
+	wire [23:0] FlashImageRF8MBAddr = 24'h000000;
+	wire [23:0] FlashImageAddr =
+		(SetRamFactorEN && SetSize==2'b00) ? FlashImageRF1MBAddr :
+		(SetRamFactorEN && SetSize!=2'b00) ? FlashImageRF8MBAddr :
+		FlashImageSlinky1MBAddr;
+
+	/* Flash address */
+	wire [23:0] FlashAddr = 
+		(IS==1) ? FlashDriverAddr[23:0] : FlashImageAddr[23:0];
+
+	/* Flash command */
+	wire [7:0] FlashCommand = 8'h3B;
+
+	/* Settings decode */
+	always @(posedge CLK) begin
+		if (IS==0 && LSTC && CSTC) case (SW[2:1])
+			2'b00: begin // 16 MB RamFactor
+				SetSize <= 2'b11;
+				SetRamFactorEN <= 1;
+				SetRestoreEN <= 0;
+			end 2'b01: begin // 8 MB RamFactor
+				SetSize <= 2'b01;
+				SetRamFactorEN <= 1;
+				SetRestoreEN <= /*!*/SW[3];
+			end 2'b10: begin // 1 MB RamFactor
+				SetSize <= 2'b00;
+				SetRamFactorEN <= 1;
+				SetRestoreEN <= /*!*/SW[3];
+			end 2'b11: begin // 1 MB Slinky
+				SetSize <= 2'b00;
+				SetRamFactorEN <= 0;
+				SetRestoreEN <= /*!*/SW[3];
+			end
+		endcase
+	end
+
+	/* SPI flash control */
+	always @(posedge CLK) begin
+		case (IS)
+			0, 1: begin // POR pause and flash check
+				FOE <= 0;
+				nFCSout <= 1;
+				FCKEN <= 0;
+				MOSIOE <= 0;
+				MOSIout <= 0;
+				RAMCmd <= `RC_NOP;
+			end 2, 5: begin
+				FOE <= 1;
+				case (CS[12:0]) // Send command
+					13'h0000: begin
+						nFCSout <= 1;
+						FCKEN <= 0;
+						MOSIout <= 0;
+						MOSIOE <= 1;
+						RAMCmd <= `RC_PC;
+					end 13'h0004: begin
+						nFCSout <= 1;
+						FCKEN <= 0;
+						MOSIout <= 0;
+						MOSIOE <= 1;
+						RAMCmd <= `RC_LDM;
+					end 13'h0008, 13'h000C,
+						13'h0010, 13'h0014, 13'h0018, 13'h001C,
+						13'h0020, 13'h0024, 13'h0028, 13'h002C,
+						13'h0030, 13'h0034, 13'h0038, 13'h003C,
+						13'h0040, 13'h0044, 13'h0048, 13'h004C,
+						13'h0050, 13'h0054, 13'h0058, 13'h005C,
+						13'h0060, 13'h0064, 13'h0068, 13'h006C,
+						13'h0070, 13'h0074, 13'h0078, 13'h007C: begin
+						nFCSout <= 1;
+						FCKEN <= 0;
+						MOSIout <= 0;
+						MOSIOE <= 1;
+						RAMCmd <= `RC_Ref;
+					end 13'h1010, 13'h1011, 13'h1012, 13'h1013,
+						13'h1014, 13'h1015, 13'h1016: begin // /CS low
+						nFCSout <= 0;
+						FCKEN <= 0;
+						MOSIout <= 0;
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1017: begin // Command bit 7 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[7];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1018: begin // Command bit 6 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[6];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1019: begin // Command bit 5 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[5];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h101A: begin // Command bit 4 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[4];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h101B: begin // Command bit 3 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[3];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h101C: begin // Command bit 2 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[2];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h101D: begin // Command bit 1 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[1];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h101E: begin // Command bit 0 (0x3B)
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashCommand[0];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h101F: begin // Address bit 23
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[23];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1020: begin // Address bit 22
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[22];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1021: begin // Address bit 21
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[23];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1022: begin // Address bit 20
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[20];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1023: begin // Address bit 19
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[19];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1024: begin // Address bit 18
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[18];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1025: begin // Address bit 17
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[17];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1026: begin // Address bit 16
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[16];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1027: begin // Address bit 15
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[15];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1028: begin // Address bit 14
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[14];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1029: begin // Address bit 13
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[13];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h102A: begin // Address bit 12
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[12];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h102B: begin // Address bit 11
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[11];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h102C: begin // Address bit 10
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[10];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h102D: begin // Address bit 9
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[9];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h102E: begin // Address bit 8
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[8];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h102F: begin // Address bit 7
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[7];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1030: begin // Address bit 6
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[6];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_Ref;
+					end 13'h1031: begin // Address bit 5
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[5];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1032: begin // Address bit 4
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[4];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1033: begin // Address bit 3
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[3];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1034: begin // Address bit 2
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[2];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1035: begin // Address bit 1
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[1];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1036: begin // Address bit 0
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= FlashAddr[0];
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end 13'h1037: begin // First dummy bit
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= 0;
+						MOSIOE <= 0;
+						RAMCmd <= `RC_NOP;
+					end 13'h1038, 13'h1039, 13'h103A, // Dummy bits 2-8
+					    13'h103B, 13'h103C, 13'h103D, 13'h103E: begin
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= 0;
+						MOSIOE <= 0;
+						RAMCmd <= `RC_NOP;
+					end 13'h103F: begin // First data bit output
+						nFCSout <= 0;
+						FCKEN <= 1;
+						MOSIout <= 0;
+						MOSIOE <= 0;
+						RAMCmd <= `RC_NOP;
+					end default: begin
+						nFCSout <= 1;
+						FCKEN <= 0;
+						MOSIout <= 0;
+						MOSIOE <= 1;
+						RAMCmd <= `RC_NOP;
+					end
+				endcase
+			end 3, 6: begin // Load flash to RAM
+				FOE <= 1;
+				nFCSout <= 0;
+				MOSIout <= 0;
+				MOSIOE <= 0;
+				if (!CS[12]) begin
+					FCKEN <= 1;
+					if (CS[11:0]==0) RAMCmd <= `RC_ACT;
+					else if (CS[1:0]==2'b11) RAMCmd <= `RC_WR;
+					else RAMCmd <= `RC_NOP;
+				end else begin
+					FCKEN <= 0;
+					case (CS)
+						13'h1002: RAMCmd <= `RC_PC;
+						13'h1004, 13'h1008, 13'h100C,
+						13'h1010, 13'h1014, 13'h1018, 13'h101C,
+						13'h1020, 13'h1024, 13'h1028, 13'h102C,
+						13'h1030, 13'h1034, 13'h1038, 13'h103C: RAMCmd <= `RC_Ref;
+						default: RAMCmd <= `RC_NOP;
+					endcase
+				end
+			end 4, 7: begin // End flash command
+				FOE <= 1;
+				nFCSout <= 1;
+				FCKEN <= 0;
+				MOSIout <= 0;
+				MOSIOE <= 0;
+				case (CS)
+					13'h1002: RAMCmd <= `RC_PC;
+					13'h1004, 13'h1008, 13'h100C,
+					13'h1010, 13'h1014, 13'h1018, 13'h101C,
+					13'h1020, 13'h1024, 13'h1028, 13'h102C,
+					13'h1030, 13'h1034, 13'h1038, 13'h103C: RAMCmd <= `RC_Ref;
+					default: RAMCmd <= `RC_NOP;
+				endcase
+			end 8: begin // Operating mode
+				FOE <= 1;
+				nFCSout <= 1;
+				FCKEN <= 0;
+				MOSIout <= 0;
+				MOSIOE <= 0;
+				RAMCmd <= `RC_NOP;
+			end 9: begin // Flash sleep
+				FOE <= 0;
+				nFCSout <= 1;
+				FCKEN <= 0;
+				MOSIout <= 0;
+				MOSIOE <= 0;
+				RAMCmd <= `RC_NOP;
+			end default: begin // Else
+				FOE <= 1;
+				nFCSout <= 1;
+				FCKEN <= 0;
+				MOSIout <= 0;
+				MOSIOE <= 0;
+				RAMCmd <= `RC_NOP;
+			end
+		endcase
+	end
+
+	/* MISO and MOSI capture on falling edge */
+	reg MISOr, MOSIr;
+	always @(negedge CLK) MISOr <= MISO;
+	always @(negedge CLK) MOSIr <= MOSIin;
+
+	/* Input data shift register */
+	always @(posedge CLK) begin
+		WRD[7:0] <= SetRestoreEN ? { WRD[5:0], MISOr, MOSIr } : 8'h00;
+	end
+endmodule

cpld/LCMXO2-1200HC/.run_manager.ini

@@ -0,0 +1,9 @@
+[Runmanager]
+Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
+windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
+
+[impl1%3CStrategy1%3E]
+isChecked=false
+isHidden=false
+isExpanded=false

cpld/LCMXO2-1200HC/.setting.ini

@@ -0,0 +1,4 @@
+[General]
+Export.auto_tasks=Jedecgen
+PAR.auto_tasks=@@empty()
+AutoAssign=true

cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="GR8RAM_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="GR8RAM"/>
+        <Source name="../GR8RAM.v" type="Verilog" type_short="Verilog">
+            <Options top_module="GR8RAM"/>
+        </Source>
+        <Source name="../GR8RAM-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="GR8RAM_LCMXO2_1200HC1.sty"/>
+</BaliProject>

cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC1.sty

@@ -0,0 +1,203 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
+    <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+    <Property name="PROP_SYN_LibPath" value="" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+    <Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
+</Strategy>

cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC_tcl.html

@@ -0,0 +1,70 @@
+<HTML>
+<HEAD><TITLE>Lattice TCL Log</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{␍    font-family:'Courier New', monospace;␍    color: #000000;␍    font-size:88%;␍    background-color: #ffffff;␍}␍h1 {␍    font-weight: bold;␍    margin-top: 24px;␍    margin-bottom: 10px;␍    border-bottom: 3px solid #000;    font-size: 1em;␍}␍h2 {␍    font-weight: bold;␍    margin-top: 18px;␍    margin-bottom: 5px;␍    font-size: 0.90em;␍}␍h3 {␍    font-weight: bold;␍    margin-top: 12px;␍    margin-bottom: 5px;␍    font-size: 0.80em;␍}␍p {␍    font-size:78%;␍}␍P.Table {␍    margin-top: 4px;␍    margin-bottom: 4px;␍    margin-right: 4px;␍    margin-left: 4px;␍}␍table␍{␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    border-collapse: collapse;␍}␍th {␍    font-weight:bold;␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    text-align:left;␍    font-size:78%;␍}␍td {␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    font-size:78%;␍}␍a {␍    color:#013C9A;␍    text-decoration:none;␍}␍␍a:visited {␍    color:#013C9A;␍}␍␍a:hover, a:active {␍    text-decoration:underline;␍    color:#5BAFD4;␍}␍.pass␍{␍background-color: #00ff00;␍}␍.fail␍{␍background-color: #ff0000;␍}␍.comment␍{␍    font-size: 90%;␍    font-style: italic;␍}␍
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="pn240613003303"></A><B><U><big>pn240613003303</big></U></B>
+#Start recording tcl command: 6/13/2024 00:16:33
+#Project Location: //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC; Project name: GR8RAM_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1
+#Stop recording: 6/13/2024 00:33:03
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>

cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC_tcr.dir/pn240613003303.tcr

@@ -0,0 +1,5 @@
+#Start recording tcl command: 6/13/2024 00:16:33
+#Project Location: //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC; Project name: GR8RAM_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1
+#Stop recording: 6/13/2024 00:33:03

cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC_tcr.dir/pn240614200121.tcr

@@ -0,0 +1,6 @@
+#Start recording tcl command: 6/13/2024 00:37:49
+#Project Location: //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC; Project name: GR8RAM_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 6/14/2024 20:01:21

cpld/LCMXO2-1200HC/REFB.ipx

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 21 04:34:51.977" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
+  <Package>
+		<File name="REFB.lpc" type="lpc" modified="2023 09 21 04:34:49.038"/>
+		<File name="REFB.v" type="top_level_verilog" modified="2023 09 21 04:34:49.107"/>
+		<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 21 04:34:49.108"/>
+  </Package>
+</DiamondModule>

cpld/LCMXO2-1200HC/impl1/.build_status

@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BuildStatus>
+    <Strategy name="Strategy1">
+        <Milestone name="Export" build_result="0" build_time="0">
+            <Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
+            <Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
+            <Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
+            <Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
+            <Task name="Jedecgen" build_result="2" update_result="0" update_time="1718253547"/>
+        </Milestone>
+        <Milestone name="Map" build_result="2" build_time="1718253533">
+            <Task name="Map" build_result="2" update_result="0" update_time="1718253533"/>
+            <Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
+            <Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
+            <Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
+        </Milestone>
+        <Milestone name="PAR" build_result="2" build_time="1718253543">
+            <Task name="PAR" build_result="2" update_result="0" update_time="1718253543"/>
+            <Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
+            <Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
+        </Milestone>
+        <Milestone name="Synthesis" build_result="2" build_time="1718253532">
+            <Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1718253532"/>
+        </Milestone>
+        <Milestone name="TOOL_Report" build_result="0" build_time="0">
+            <Task name="HDLE" build_result="0" update_result="3" update_time="0"/>
+        </Milestone>
+        <Milestone name="Translate" build_result="2" build_time="1718253532">
+            <Task name="Translate" build_result="2" update_result="0" update_time="1718253532"/>
+        </Milestone>
+        <Report name="GR8RAM_LCMXO2_1200HC_impl1.bgn" last_build_time="1718253547" last_build_size="4416"/>
+        <Report name="GR8RAM_LCMXO2_1200HC_impl1.edi" last_build_time="1718253531" last_build_size="215733"/>
+        <Report name="GR8RAM_LCMXO2_1200HC_impl1.jed" last_build_time="1718253547" last_build_size="352059"/>
+        <Report name="GR8RAM_LCMXO2_1200HC_impl1.ncd" last_build_time="1718253543" last_build_size="323416"/>
+        <Report name="GR8RAM_LCMXO2_1200HC_impl1.ngd" last_build_time="1718253532" last_build_size="232595"/>
+        <Report name="GR8RAM_LCMXO2_1200HC_impl1_map.ncd" last_build_time="1718253533" last_build_size="229621"/>
+    </Strategy>
+</BuildStatus>

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.alt

@@ -0,0 +1,81 @@
+NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
+NOTE All Rights Reserved *
+NOTE DATE CREATED: Thu Jun 13 00:39:07 2024 *
+NOTE DESIGN NAME: GR8RAM *
+NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
+NOTE PIN ASSIGNMENTS *
+NOTE PINS RD[0] : 65 : inout *
+NOTE PINS nFCS : 88 : out *
+NOTE PINS RCLKout : 39 : out *
+NOTE PINS RCLK : 38 : in *
+NOTE PINS MOSI : 97 : inout *
+NOTE PINS MISO : 98 : in *
+NOTE PINS FCK : 96 : out *
+NOTE PINS SD[7] : 31 : inout *
+NOTE PINS SD[6] : 30 : inout *
+NOTE PINS SD[5] : 29 : inout *
+NOTE PINS SD[4] : 28 : inout *
+NOTE PINS SD[3] : 27 : inout *
+NOTE PINS SD[2] : 21 : inout *
+NOTE PINS SD[1] : 24 : inout *
+NOTE PINS SD[0] : 25 : inout *
+NOTE PINS RCKE : 40 : out *
+NOTE PINS DQMH : 34 : out *
+NOTE PINS DQML : 32 : out *
+NOTE PINS nSWE : 35 : out *
+NOTE PINS nCAS : 36 : out *
+NOTE PINS nRAS : 37 : out *
+NOTE PINS nRCS : 41 : out *
+NOTE PINS SA[12] : 42 : out *
+NOTE PINS SA[11] : 45 : out *
+NOTE PINS SA[10] : 47 : out *
+NOTE PINS SA[9] : 49 : out *
+NOTE PINS SA[8] : 53 : out *
+NOTE PINS SA[7] : 57 : out *
+NOTE PINS SA[6] : 62 : out *
+NOTE PINS SA[5] : 52 : out *
+NOTE PINS SA[4] : 51 : out *
+NOTE PINS SA[3] : 60 : out *
+NOTE PINS SA[2] : 58 : out *
+NOTE PINS SA[1] : 59 : out *
+NOTE PINS SA[0] : 54 : out *
+NOTE PINS SBA[1] : 48 : out *
+NOTE PINS SBA[0] : 43 : out *
+NOTE PINS nIOSTRB : 18 : in *
+NOTE PINS nDEVSEL : 16 : in *
+NOTE PINS nIOSEL : 15 : in *
+NOTE PINS nDinOE : 77 : out *
+NOTE PINS nDoutOE : 1 : out *
+NOTE PINS RD[7] : 75 : inout *
+NOTE PINS RD[6] : 71 : inout *
+NOTE PINS RD[5] : 70 : inout *
+NOTE PINS RD[4] : 69 : inout *
+NOTE PINS RD[3] : 68 : inout *
+NOTE PINS RD[2] : 67 : inout *
+NOTE PINS RD[1] : 66 : inout *
+NOTE PINS nWE : 19 : in *
+NOTE PINS RA[15] : 14 : in *
+NOTE PINS RA[14] : 13 : in *
+NOTE PINS RA[13] : 10 : in *
+NOTE PINS RA[12] : 9 : in *
+NOTE PINS RA[11] : 8 : in *
+NOTE PINS RA[10] : 3 : in *
+NOTE PINS RA[9] : 2 : in *
+NOTE PINS RA[8] : 99 : in *
+NOTE PINS RA[7] : 87 : in *
+NOTE PINS RA[6] : 86 : in *
+NOTE PINS RA[5] : 85 : in *
+NOTE PINS RA[4] : 4 : in *
+NOTE PINS RA[3] : 84 : in *
+NOTE PINS RA[2] : 83 : in *
+NOTE PINS RA[1] : 78 : in *
+NOTE PINS RA[0] : 74 : in *
+NOTE PINS LED : 81 : out *
+NOTE PINS SetFW[1] : 63 : in *
+NOTE PINS SetFW[0] : 64 : in *
+NOTE PINS nIRQout : 12 : out *
+NOTE PINS nRESout : 7 : out *
+NOTE PINS nRES : 20 : in *
+NOTE PINS PHI0 : 17 : in *
+NOTE CONFIGURATION MODE: NONE *
+NOTE COMPRESSION: on *

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.areasrr

@@ -0,0 +1,31 @@
+----------------------------------------------------------------------
+Report for cell GR8RAM.verilog
+
+Register bits: 118 of 1280 (9%)
+PIC Latch:       0
+I/O cells:       73
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                                 BB       17       100.0
+                              CCU2D       13       100.0
+                            FD1P3AX       24       100.0
+                            FD1S3AX       17       100.0
+                            FD1S3DX       27       100.0
+                                GSR        1       100.0
+                                 IB       26       100.0
+                           IFS1P3DX       18       100.0
+                                INV        7       100.0
+                                 OB       28       100.0
+                                OBZ        2       100.0
+                             ODDRXE        1       100.0
+                           OFS1P3BX        7       100.0
+                           OFS1P3DX       12       100.0
+                           OFS1P3IX       10       100.0
+                           OFS1P3JX        3       100.0
+                           ORCALUT4      240       100.0
+                              PFUMX        7       100.0
+                                PUR        1       100.0
+                                VHI        1       100.0
+                                VLO        1       100.0
+                            
+                         TOTAL           463           

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.bgn

@@ -0,0 +1,86 @@
+BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:39:03 2024
+
+
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml GR8RAM_LCMXO2_1200HC_impl1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf 
+
+Loading design for application Bitgen from file GR8RAM_LCMXO2_1200HC_impl1.ncd.
+Design name: GR8RAM
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from GR8RAM_LCMXO2_1200HC_impl1.prf.
+
+Preference Summary:
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "GR8RAM_LCMXO2_1200HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 3 secs 
+Total REAL Time: 4 secs 
+Peak Memory Usage: 275 MB

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.pad

@@ -0,0 +1,321 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Jun 13 00:38:57 2024
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| DQMH      | 34/2     | LVCMOS33_OUT  | PB9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| DQML      | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| FCK       | 96/0     | LVCMOS33_OUT  | PT10B |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
+| LED       | 81/0     | LVCMOS33_OUT  | PT15D |           |           | DRIVE:24mA SLEW:SLOW                                       |
+| MISO      | 98/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MOSI      | 97/0     | LVCMOS33_BIDI | PT10A |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| PHI0      | 17/3     | LVCMOS33_IN   | PL8B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 74/1     | LVCMOS33_IN   | PR2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[10]    | 3/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[11]    | 8/3      | LVCMOS33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[12]    | 9/3      | LVCMOS33_IN   | PL4A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[13]    | 10/3     | LVCMOS33_IN   | PL4B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[14]    | 13/3     | LVCMOS33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[15]    | 14/3     | LVCMOS33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[1]     | 78/0     | LVCMOS33_IN   | PT16C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[2]     | 83/0     | LVCMOS33_IN   | PT15B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[3]     | 84/0     | LVCMOS33_IN   | PT15A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[4]     | 4/3      | LVCMOS33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[5]     | 85/0     | LVCMOS33_IN   | PT12D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[6]     | 86/0     | LVCMOS33_IN   | PT12C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[7]     | 87/0     | LVCMOS33_IN   | PT12B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[8]     | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[9]     | 2/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RCKE      | 40/2     | LVCMOS33_OUT  | PB15A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 38/2     | LVCMOS33_IN   | PB11A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RCLKout   | 39/2     | LVCMOS33_OUT  | PB11B |           |           | DRIVE:24mA SLEW:FAST                                       |
+| RD[0]     | 65/1     | LVCMOS33_BIDI | PR5A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 66/1     | LVCMOS33_BIDI | PR4D  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 67/1     | LVCMOS33_BIDI | PR4C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 68/1     | LVCMOS33_BIDI | PR4B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 69/1     | LVCMOS33_BIDI | PR4A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 70/1     | LVCMOS33_BIDI | PR3B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 71/1     | LVCMOS33_BIDI | PR3A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 75/1     | LVCMOS33_BIDI | PR2A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SA[0]     | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[10]    | 47/2     | LVCMOS33_OUT  | PB18D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[11]    | 45/2     | LVCMOS33_OUT  | PB18C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[12]    | 42/2     | LVCMOS33_OUT  | PB18A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[1]     | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[2]     | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[3]     | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[4]     | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[5]     | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[6]     | 62/1     | LVCMOS33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[7]     | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[8]     | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[9]     | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SBA[0]    | 43/2     | LVCMOS33_OUT  | PB18B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SBA[1]    | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SD[0]     | 25/3     | LVCMOS33_BIDI | PL10D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[1]     | 24/3     | LVCMOS33_BIDI | PL10C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[2]     | 21/3     | LVCMOS33_BIDI | PL9B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[3]     | 27/2     | LVCMOS33_BIDI | PB4C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[4]     | 28/2     | LVCMOS33_BIDI | PB4D  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[5]     | 29/2     | LVCMOS33_BIDI | PB6A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[6]     | 30/2     | LVCMOS33_BIDI | PB6B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[7]     | 31/2     | LVCMOS33_BIDI | PB6C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SetFW[0]  | 64/1     | LVCMOS33_IN   | PR5B  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
+| SetFW[1]  | 63/1     | LVCMOS33_IN   | PR5C  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
+| nCAS      | 36/2     | LVCMOS33_OUT  | PB11C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDEVSEL   | 16/3     | LVCMOS33_IN   | PL8A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nDinOE    | 77/0     | LVCMOS33_OUT  | PT17C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDoutOE   | 1/3      | LVCMOS33_OUT  | PL2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nFCS      | 88/0     | LVCMOS33_OUT  | PT12A |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
+| nIOSEL    | 15/3     | LVCMOS33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nIOSTRB   | 18/3     | LVCMOS33_IN   | PL8C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nIRQout   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRAS      | 37/2     | LVCMOS33_OUT  | PB11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 41/2     | LVCMOS33_OUT  | PB15B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRES      | 20/3     | LVCMOS33_IN   | PL9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRESout   | 7/3      | LVCMOS33_OUT  | PL3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nSWE      | 35/2     | LVCMOS33_OUT  | PB9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nWE       | 19/3     | LVCMOS33_IN   | PL8D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | nDoutOE               | LOCATED    | LVCMOS33_OUT  | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      | RA[9]                 | LOCATED    | LVCMOS33_IN   | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      | RA[10]                | LOCATED    | LVCMOS33_IN   | PL3A  | PCLKT3_2      |           |           |
+| 4/3      | RA[4]                 | LOCATED    | LVCMOS33_IN   | PL3B  | PCLKC3_2      |           |           |
+| 7/3      | nRESout               | LOCATED    | LVCMOS33_OUT  | PL3C  |               |           |           |
+| 8/3      | RA[11]                | LOCATED    | LVCMOS33_IN   | PL3D  |               |           |           |
+| 9/3      | RA[12]                | LOCATED    | LVCMOS33_IN   | PL4A  |               |           |           |
+| 10/3     | RA[13]                | LOCATED    | LVCMOS33_IN   | PL4B  |               |           |           |
+| 12/3     | nIRQout               | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | RA[14]                | LOCATED    | LVCMOS33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | RA[15]                | LOCATED    | LVCMOS33_IN   | PL5C  |               |           |           |
+| 15/3     | nIOSEL                | LOCATED    | LVCMOS33_IN   | PL5D  |               |           |           |
+| 16/3     | nDEVSEL               | LOCATED    | LVCMOS33_IN   | PL8A  |               |           |           |
+| 17/3     | PHI0                  | LOCATED    | LVCMOS33_IN   | PL8B  |               |           |           |
+| 18/3     | nIOSTRB               | LOCATED    | LVCMOS33_IN   | PL8C  |               |           |           |
+| 19/3     | nWE                   | LOCATED    | LVCMOS33_IN   | PL8D  |               |           |           |
+| 20/3     | nRES                  | LOCATED    | LVCMOS33_IN   | PL9A  | PCLKT3_0      |           |           |
+| 21/3     | SD[2]                 | LOCATED    | LVCMOS33_BIDI | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | SD[1]                 | LOCATED    | LVCMOS33_BIDI | PL10C |               |           |           |
+| 25/3     | SD[0]                 | LOCATED    | LVCMOS33_BIDI | PL10D |               |           |           |
+| 27/2     | SD[3]                 | LOCATED    | LVCMOS33_BIDI | PB4C  | CSSPIN        |           |           |
+| 28/2     | SD[4]                 | LOCATED    | LVCMOS33_BIDI | PB4D  |               |           |           |
+| 29/2     | SD[5]                 | LOCATED    | LVCMOS33_BIDI | PB6A  |               |           |           |
+| 30/2     | SD[6]                 | LOCATED    | LVCMOS33_BIDI | PB6B  |               |           |           |
+| 31/2     | SD[7]                 | LOCATED    | LVCMOS33_BIDI | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB6D  | SO/SPISO      |           |           |
+| 34/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB9A  | PCLKT2_0      |           |           |
+| 35/2     | nSWE                  | LOCATED    | LVCMOS33_OUT  | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PB11C |               |           |           |
+| 37/2     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PB11D |               |           |           |
+| 38/2     | RCLK                  | LOCATED    | LVCMOS33_IN   | PB11A | PCLKT2_1      |           |           |
+| 39/2     | RCLKout               | LOCATED    | LVCMOS33_OUT  | PB11B | PCLKC2_1      |           |           |
+| 40/2     | RCKE                  | LOCATED    | LVCMOS33_OUT  | PB15A |               |           |           |
+| 41/2     | nRCS                  | LOCATED    | LVCMOS33_OUT  | PB15B |               |           |           |
+| 42/2     | SA[12]                | LOCATED    | LVCMOS33_OUT  | PB18A |               |           |           |
+| 43/2     | SBA[0]                | LOCATED    | LVCMOS33_OUT  | PB18B |               |           |           |
+| 45/2     | SA[11]                | LOCATED    | LVCMOS33_OUT  | PB18C |               |           |           |
+| 47/2     | SA[10]                | LOCATED    | LVCMOS33_OUT  | PB18D |               |           |           |
+| 48/2     | SBA[1]                | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
+| 49/2     | SA[9]                 | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | SA[4]                 | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | SA[5]                 | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | SA[8]                 | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | SA[0]                 | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | SA[7]                 | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
+| 58/1     | SA[2]                 | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
+| 59/1     | SA[1]                 | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
+| 60/1     | SA[3]                 | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
+| 62/1     | SA[6]                 | LOCATED    | LVCMOS33_OUT  | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | SetFW[1]              | LOCATED    | LVCMOS33_IN   | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | SetFW[0]              | LOCATED    | LVCMOS33_IN   | PR5B  | DQS0N         |           |           |
+| 65/1     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PR5A  | DQS0          |           |           |
+| 66/1     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PR4D  | DQ0           |           |           |
+| 67/1     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PR4C  | DQ0           |           |           |
+| 68/1     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PR4B  | DQ0           |           |           |
+| 69/1     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PR4A  | DQ0           |           |           |
+| 70/1     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PR3B  | DQ0           |           |           |
+| 71/1     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PR3A  | DQ0           |           |           |
+| 74/1     | RA[0]                 | LOCATED    | LVCMOS33_IN   | PR2B  | DQ0           |           |           |
+| 75/1     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
+| 77/0     | nDinOE                | LOCATED    | LVCMOS33_OUT  | PT17C | INITN         |           |           |
+| 78/0     | RA[1]                 | LOCATED    | LVCMOS33_IN   | PT16C |               |           |           |
+| 81/0     | LED                   | LOCATED    | LVCMOS33_OUT  | PT15D | PROGRAMN      |           |           |
+| 82/0     |     unused, PULL:DOWN |            |               | PT15C | JTAGENB       |           |           |
+| 83/0     | RA[2]                 | LOCATED    | LVCMOS33_IN   | PT15B |               |           |           |
+| 84/0     | RA[3]                 | LOCATED    | LVCMOS33_IN   | PT15A |               |           |           |
+| 85/0     | RA[5]                 | LOCATED    | LVCMOS33_IN   | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | RA[6]                 | LOCATED    | LVCMOS33_IN   | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | RA[7]                 | LOCATED    | LVCMOS33_IN   | PT12B | PCLKC0_1      |           |           |
+| 88/0     | nFCS                  | LOCATED    | LVCMOS33_OUT  | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | FCK                   | LOCATED    | LVCMOS33_OUT  | PT10B |               |           |           |
+| 97/0     | MOSI                  | LOCATED    | LVCMOS33_BIDI | PT10A |               |           |           |
+| 98/0     | MISO                  | LOCATED    | LVCMOS33_IN   | PT9B  |               |           |           |
+| 99/0     | RA[8]                 | LOCATED    | LVCMOS33_IN   | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "DQMH"  SITE  "34";
+LOCATE  COMP  "DQML"  SITE  "32";
+LOCATE  COMP  "FCK"  SITE  "96";
+LOCATE  COMP  "LED"  SITE  "81";
+LOCATE  COMP  "MISO"  SITE  "98";
+LOCATE  COMP  "MOSI"  SITE  "97";
+LOCATE  COMP  "PHI0"  SITE  "17";
+LOCATE  COMP  "RA[0]"  SITE  "74";
+LOCATE  COMP  "RA[10]"  SITE  "3";
+LOCATE  COMP  "RA[11]"  SITE  "8";
+LOCATE  COMP  "RA[12]"  SITE  "9";
+LOCATE  COMP  "RA[13]"  SITE  "10";
+LOCATE  COMP  "RA[14]"  SITE  "13";
+LOCATE  COMP  "RA[15]"  SITE  "14";
+LOCATE  COMP  "RA[1]"  SITE  "78";
+LOCATE  COMP  "RA[2]"  SITE  "83";
+LOCATE  COMP  "RA[3]"  SITE  "84";
+LOCATE  COMP  "RA[4]"  SITE  "4";
+LOCATE  COMP  "RA[5]"  SITE  "85";
+LOCATE  COMP  "RA[6]"  SITE  "86";
+LOCATE  COMP  "RA[7]"  SITE  "87";
+LOCATE  COMP  "RA[8]"  SITE  "99";
+LOCATE  COMP  "RA[9]"  SITE  "2";
+LOCATE  COMP  "RCKE"  SITE  "40";
+LOCATE  COMP  "RCLK"  SITE  "38";
+LOCATE  COMP  "RCLKout"  SITE  "39";
+LOCATE  COMP  "RD[0]"  SITE  "65";
+LOCATE  COMP  "RD[1]"  SITE  "66";
+LOCATE  COMP  "RD[2]"  SITE  "67";
+LOCATE  COMP  "RD[3]"  SITE  "68";
+LOCATE  COMP  "RD[4]"  SITE  "69";
+LOCATE  COMP  "RD[5]"  SITE  "70";
+LOCATE  COMP  "RD[6]"  SITE  "71";
+LOCATE  COMP  "RD[7]"  SITE  "75";
+LOCATE  COMP  "SA[0]"  SITE  "54";
+LOCATE  COMP  "SA[10]"  SITE  "47";
+LOCATE  COMP  "SA[11]"  SITE  "45";
+LOCATE  COMP  "SA[12]"  SITE  "42";
+LOCATE  COMP  "SA[1]"  SITE  "59";
+LOCATE  COMP  "SA[2]"  SITE  "58";
+LOCATE  COMP  "SA[3]"  SITE  "60";
+LOCATE  COMP  "SA[4]"  SITE  "51";
+LOCATE  COMP  "SA[5]"  SITE  "52";
+LOCATE  COMP  "SA[6]"  SITE  "62";
+LOCATE  COMP  "SA[7]"  SITE  "57";
+LOCATE  COMP  "SA[8]"  SITE  "53";
+LOCATE  COMP  "SA[9]"  SITE  "49";
+LOCATE  COMP  "SBA[0]"  SITE  "43";
+LOCATE  COMP  "SBA[1]"  SITE  "48";
+LOCATE  COMP  "SD[0]"  SITE  "25";
+LOCATE  COMP  "SD[1]"  SITE  "24";
+LOCATE  COMP  "SD[2]"  SITE  "21";
+LOCATE  COMP  "SD[3]"  SITE  "27";
+LOCATE  COMP  "SD[4]"  SITE  "28";
+LOCATE  COMP  "SD[5]"  SITE  "29";
+LOCATE  COMP  "SD[6]"  SITE  "30";
+LOCATE  COMP  "SD[7]"  SITE  "31";
+LOCATE  COMP  "SetFW[0]"  SITE  "64";
+LOCATE  COMP  "SetFW[1]"  SITE  "63";
+LOCATE  COMP  "nCAS"  SITE  "36";
+LOCATE  COMP  "nDEVSEL"  SITE  "16";
+LOCATE  COMP  "nDinOE"  SITE  "77";
+LOCATE  COMP  "nDoutOE"  SITE  "1";
+LOCATE  COMP  "nFCS"  SITE  "88";
+LOCATE  COMP  "nIOSEL"  SITE  "15";
+LOCATE  COMP  "nIOSTRB"  SITE  "18";
+LOCATE  COMP  "nIRQout"  SITE  "12";
+LOCATE  COMP  "nRAS"  SITE  "37";
+LOCATE  COMP  "nRCS"  SITE  "41";
+LOCATE  COMP  "nRES"  SITE  "20";
+LOCATE  COMP  "nRESout"  SITE  "7";
+LOCATE  COMP  "nSWE"  SITE  "35";
+LOCATE  COMP  "nWE"  SITE  "19";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:39:01 2024
+

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.par

@@ -0,0 +1,205 @@
+
+Lattice Place and Route Report for Design "GR8RAM_LCMXO2_1200HC_impl1_map.ncd"
+Thu Jun 13 00:38:53 2024
+
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
+Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
+Design name: GR8RAM
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   73+4(JTAG)/108     71% used
+                  73+4(JTAG)/80      96% bonded
+   IOLOGIC           51/108          47% used
+
+   SLICE            136/640          21% used
+
+   GSR                1/1           100% used
+
+
+Number of Signals: 430
+Number of Connections: 1211
+
+Pin Constraint Summary:
+   73 out of 73 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 80)
+    PHI0_c (driver: PHI0, clk load #: 14)
+
+WARNING - par: Signal "PHI0_c" is selected to use Primary clock resources. However, its driver comp "PHI0" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
+
+Signal nRESr is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 87858.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  86903
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 1 out of 108 (0%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "38 (PB11A)", clk load = 80
+  PRIMARY "PHI0_c" from comp "PHI0" on PIO site "17 (PL8B)", clk load = 14
+  SECONDARY "FCKout120" from F0 on comp "SLICE_54" on site "R7C12B", clk load = 0, ce load = 0, sr load = 13
+
+  PRIMARY  : 2 out of 8 (25%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
+   73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
+   Number of PIO comps: 73; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
+| 2        | 20 / 20 (100%) | 3.3V       | -         |
+| 3        | 20 / 20 (100%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 3 secs 
+
+Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+-----------------------------------------------------------------
+INFO - par: ASE feature is off due to non timing-driven settings.  
+-----------------------------------------------------------------
+
+0 connections routed; 1211 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 9 secs 
+
+Start NBR router at 00:39:02 06/13/24
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 00:39:02 06/13/24
+
+Start NBR section for initial routing at 00:39:02 06/13/24
+Level 4, iteration 1
+19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 00:39:02 06/13/24
+Level 4, iteration 1
+4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Start NBR section for re-routing at 00:39:02 06/13/24
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Start NBR section for post-routing at 00:39:02 06/13/24
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : <n/a>
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 8 secs 
+Total REAL time: 9 secs 
+Completely routed.
+End of route.  1211 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = <n/a>
+PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
+PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
+PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/5_1_par.asd

@@ -0,0 +1,38 @@
+[ActiveSupport PAR]
+; Global primary clocks
+GLOBAL_PRIMARY_USED = 2;
+; Global primary clock #0
+GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
+GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
+GLOBAL_PRIMARY_0_LOADNUM = 80;
+; Global primary clock #1
+GLOBAL_PRIMARY_1_SIGNALNAME = PHI0_c;
+GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
+GLOBAL_PRIMARY_1_LOADNUM = 14;
+; # of global secondary clocks
+GLOBAL_SECONDARY_USED = 1;
+; Global secondary clock #0
+GLOBAL_SECONDARY_0_SIGNALNAME = FCKout120;
+GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
+GLOBAL_SECONDARY_0_LOADNUM = 18;
+GLOBAL_SECONDARY_0_SIGTYPE = RST;
+; I/O Bank 0 Usage
+BANK_0_USED = 13;
+BANK_0_AVAIL = 19;
+BANK_0_VCCIO = 3.3V;
+BANK_0_VREF1 = NA;
+; I/O Bank 1 Usage
+BANK_1_USED = 20;
+BANK_1_AVAIL = 21;
+BANK_1_VCCIO = 3.3V;
+BANK_1_VREF1 = NA;
+; I/O Bank 2 Usage
+BANK_2_USED = 20;
+BANK_2_AVAIL = 20;
+BANK_2_VCCIO = 3.3V;
+BANK_2_VREF1 = NA;
+; I/O Bank 3 Usage
+BANK_3_USED = 20;
+BANK_3_AVAIL = 20;
+BANK_3_VCCIO = 3.3V;
+BANK_3_VREF1 = NA;

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.dir/GR8RAM_LCMXO2_1200HC_impl1.par

@@ -0,0 +1,28 @@
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:38:53 2024
+
+C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
+GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
+GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
+//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
+
+
+Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -            -            -            -            10           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.drc

@@ -0,0 +1 @@
+DRC detected 0 errors and 0 warnings.

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.htm

@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/GR8RAM_LCMXO2_1200HC_impl1_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/GR8RAM_LCMXO2_1200HC_impl1_toc.htm" name="tocFrame" />
+ 				 <frame src="syntmp/GR8RAM_LCMXO2_1200HC_impl1_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.log

@@ -0,0 +1,4 @@
+---- MParTrce Tool Log File ----
+
+==== Par Standard Out ====
+==== End of Par Standard Out ====

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.mrp

@@ -0,0 +1,402 @@
+
+            Lattice Mapping Report File for Design Module 'GR8RAM'
+
+
+Design Information
+------------------
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     GR8RAM_LCMXO2_1200HC_impl1.ngd -o GR8RAM_LCMXO2_1200HC_impl1_map.ncd -pr
+     GR8RAM_LCMXO2_1200HC_impl1.prf -mp GR8RAM_LCMXO2_1200HC_impl1.mrp -lpf //Ma
+     c/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_s
+     ynplify.lpf -lpf //Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM-LCMXO2.lpf -c 0 -gui
+     -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.11.3.469
+Mapped on:  06/13/24  00:38:52
+
+Design Summary
+--------------
+
+   Number of registers:    118 out of  1520 (8%)
+      PFU registers:           68 out of  1280 (5%)
+      PIO registers:           50 out of   240 (21%)
+   Number of SLICEs:       136 out of   640 (21%)
+      SLICEs as Logic/ROM:    136 out of   640 (21%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:         13 out of   640 (2%)
+   Number of LUT4s:        268 out of  1280 (21%)
+      Number used as logic LUTs:        242
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       26
+      Number used as shift registers:     0
+   Number of PIO sites used: 73 + 4(JTAG) out of 80 (96%)
+   Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
+      Number of IDDR cells:   0
+      Number of ODDR cells:   1
+      Number of TDDR cells:   0
+   Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
+      Number of PIO using IDDR only:        0 (0 differential)
+      Number of PIO using ODDR only:        1 (0 differential)
+      Number of PIO using TDDR only:        0 (0 differential)
+      Number of PIO using IDDR/ODDR:        0 (0 differential)
+      Number of PIO using IDDR/TDDR:        0 (0 differential)
+      Number of PIO using ODDR/TDDR:        0 (0 differential)
+      Number of PIO using IDDR/ODDR/TDDR:   0 (0 differential)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:        1 out of 1 (100%)
+   EFB used :        No
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+
+                                    Page 1
+
+
+
+
+Design:  GR8RAM                                        Date:  06/13/24  00:38:52
+
+Design Summary (cont)
+---------------------
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  2
+     Net RCLK_c: 80 loads, 72 rising, 8 falling (Driver: PIO RCLK )
+     Net PHI0_c: 14 loads, 14 rising, 0 falling (Driver: PIO PHI0 )
+   Number of Clock Enables:  6
+     Net un1_nRESout4_1_i_0: 2 loads, 2 LSLICEs
+     Net PS[0]: 5 loads, 3 LSLICEs
+     Net SetFWr3: 2 loads, 0 LSLICEs
+     Net N_254_i: 8 loads, 8 LSLICEs
+     Net Bank5: 1 loads, 0 LSLICEs
+     Net RDD37: 8 loads, 1 LSLICEs
+   Number of local set/reset loads for net nRESr merged into GSR:  28
+   Number of LSRs:  1
+     Net FCKout120: 13 loads, 0 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net PS[0]: 33 loads
+     Net SBA14: 31 loads
+     Net N_248: 29 loads
+     Net PS[3]: 28 loads
+     Net PS[2]: 24 loads
+     Net PS[1]: 23 loads
+     Net RAr[1]: 20 loads
+     Net RAMSpecSEL: 19 loads
+     Net FCKout120: 18 loads
+     Net un1_PS_6: 14 loads
+
+
+
+
+   Number of warnings:  1
+   Number of errors:    0
+     
+
+Design Errors/Warnings
+----------------------
+
+WARNING - map: Using local reset signal 'nRESr' to infer global GSR net.
+
+IO (PIO) Attributes
+-------------------
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+                                    Page 2
+
+
+
+
+Design:  GR8RAM                                        Date:  06/13/24  00:38:52
+
+IO (PIO) Attributes (cont)
+--------------------------
+| nFCS                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RCLKout             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| MOSI                | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| MISO                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| FCK                 | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SD[7]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SD[6]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SD[5]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[4]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[3]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[2]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[1]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[0]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nSWE                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[12]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[11]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[10]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[9]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[8]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[7]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[6]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+
+                                    Page 3
+
+
+
+
+Design:  GR8RAM                                        Date:  06/13/24  00:38:52
+
+IO (PIO) Attributes (cont)
+--------------------------
+| SA[5]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[4]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[3]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[2]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[1]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[0]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SBA[1]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SBA[0]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nIOSTRB             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nDEVSEL             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nIOSEL              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nDinOE              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nDoutOE             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nWE                 | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[15]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[14]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[13]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[12]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[10]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[9]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+                                    Page 4
+
+
+
+
+Design:  GR8RAM                                        Date:  06/13/24  00:38:52
+
+IO (PIO) Attributes (cont)
+--------------------------
+| RA[8]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[7]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[6]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[5]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[4]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[3]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[2]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[1]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[0]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SetFW[1]            | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| SetFW[0]            | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| nIRQout             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nRESout             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nRES                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| PHI0                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+Removed logic
+-------------
+
+Signal SDOE_i was merged into signal SDOE
+Signal MOSIOE_i was merged into signal MOSIOE
+Signal FCKOE_i was merged into signal FCKOE
+Signal nRESr_i was merged into signal nRESr
+Signal PS_i[0] was merged into signal PS[0]
+Signal RDD_0_.CN was merged into signal RCLK_c
+Signal LS_s_0_S1[13] undriven or does not drive anything - clipped.
+Signal LS_s_0_COUT[13] undriven or does not drive anything - clipped.
+Signal un1_Addr_1_cry_0_0_S0 undriven or does not drive anything - clipped.
+Signal N_2 undriven or does not drive anything - clipped.
+Signal un1_Addr_1_s_7_0_S1 undriven or does not drive anything - clipped.
+Signal un1_Addr_1_s_7_0_COUT undriven or does not drive anything - clipped.
+Signal LS_cry_0_S0[0] undriven or does not drive anything - clipped.
+Signal N_1 undriven or does not drive anything - clipped.
+Block SDOE_RNIBPBD was optimized away.
+Block MOSI_pad_RNO was optimized away.
+Block FCKOE_RNI8HE1 was optimized away.
+Block nRESr_RNIAPB9 was optimized away.
+Block PS_RNIBBDD[0] was optimized away.
+Block RDD_0_.CN was optimized away.
+
+                                    Page 5
+
+
+
+
+Design:  GR8RAM                                        Date:  06/13/24  00:38:52
+
+Removed logic (cont)
+--------------------
+
+     
+
+GSR Usage
+---------
+
+GSR Component:
+   The local reset signal 'nRESr' of the design has been inferred as Global Set
+        Reset (GSR). The reset signal used for GSR control is 'nRESr'.
+        
+
+     GSR Property:
+   The design components with GSR property set to ENABLED will respond to global
+        set reset while the components with GSR property set to DISABLED will
+        not.
+        
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 64 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+                                    Page 6
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.p2t

@@ -0,0 +1,9 @@
+-w
+-l 5
+-i 6
+-n 1
+-t 1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.p3t

@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "GR8RAM_LCMXO2_1200HC_impl1.log"
+-o "GR8RAM_LCMXO2_1200HC_impl1.csv"
+-pr "GR8RAM_LCMXO2_1200HC_impl1.prf"

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.pad

@@ -0,0 +1,321 @@
+PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Jun 13 00:38:57 2024
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| DQMH      | 34/2     | LVCMOS33_OUT  | PB9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| DQML      | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| FCK       | 96/0     | LVCMOS33_OUT  | PT10B |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
+| LED       | 81/0     | LVCMOS33_OUT  | PT15D |           |           | DRIVE:24mA SLEW:SLOW                                       |
+| MISO      | 98/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MOSI      | 97/0     | LVCMOS33_BIDI | PT10A |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| PHI0      | 17/3     | LVCMOS33_IN   | PL8B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 74/1     | LVCMOS33_IN   | PR2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[10]    | 3/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[11]    | 8/3      | LVCMOS33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[12]    | 9/3      | LVCMOS33_IN   | PL4A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[13]    | 10/3     | LVCMOS33_IN   | PL4B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[14]    | 13/3     | LVCMOS33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[15]    | 14/3     | LVCMOS33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[1]     | 78/0     | LVCMOS33_IN   | PT16C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[2]     | 83/0     | LVCMOS33_IN   | PT15B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[3]     | 84/0     | LVCMOS33_IN   | PT15A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[4]     | 4/3      | LVCMOS33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[5]     | 85/0     | LVCMOS33_IN   | PT12D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[6]     | 86/0     | LVCMOS33_IN   | PT12C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[7]     | 87/0     | LVCMOS33_IN   | PT12B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[8]     | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[9]     | 2/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RCKE      | 40/2     | LVCMOS33_OUT  | PB15A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 38/2     | LVCMOS33_IN   | PB11A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RCLKout   | 39/2     | LVCMOS33_OUT  | PB11B |           |           | DRIVE:24mA SLEW:FAST                                       |
+| RD[0]     | 65/1     | LVCMOS33_BIDI | PR5A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 66/1     | LVCMOS33_BIDI | PR4D  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 67/1     | LVCMOS33_BIDI | PR4C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 68/1     | LVCMOS33_BIDI | PR4B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 69/1     | LVCMOS33_BIDI | PR4A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 70/1     | LVCMOS33_BIDI | PR3B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 71/1     | LVCMOS33_BIDI | PR3A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 75/1     | LVCMOS33_BIDI | PR2A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SA[0]     | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[10]    | 47/2     | LVCMOS33_OUT  | PB18D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[11]    | 45/2     | LVCMOS33_OUT  | PB18C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[12]    | 42/2     | LVCMOS33_OUT  | PB18A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[1]     | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[2]     | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[3]     | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[4]     | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[5]     | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[6]     | 62/1     | LVCMOS33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[7]     | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[8]     | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[9]     | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SBA[0]    | 43/2     | LVCMOS33_OUT  | PB18B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SBA[1]    | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SD[0]     | 25/3     | LVCMOS33_BIDI | PL10D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[1]     | 24/3     | LVCMOS33_BIDI | PL10C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[2]     | 21/3     | LVCMOS33_BIDI | PL9B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[3]     | 27/2     | LVCMOS33_BIDI | PB4C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[4]     | 28/2     | LVCMOS33_BIDI | PB4D  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[5]     | 29/2     | LVCMOS33_BIDI | PB6A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[6]     | 30/2     | LVCMOS33_BIDI | PB6B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[7]     | 31/2     | LVCMOS33_BIDI | PB6C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SetFW[0]  | 64/1     | LVCMOS33_IN   | PR5B  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
+| SetFW[1]  | 63/1     | LVCMOS33_IN   | PR5C  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
+| nCAS      | 36/2     | LVCMOS33_OUT  | PB11C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDEVSEL   | 16/3     | LVCMOS33_IN   | PL8A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nDinOE    | 77/0     | LVCMOS33_OUT  | PT17C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDoutOE   | 1/3      | LVCMOS33_OUT  | PL2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nFCS      | 88/0     | LVCMOS33_OUT  | PT12A |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
+| nIOSEL    | 15/3     | LVCMOS33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nIOSTRB   | 18/3     | LVCMOS33_IN   | PL8C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nIRQout   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRAS      | 37/2     | LVCMOS33_OUT  | PB11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 41/2     | LVCMOS33_OUT  | PB15B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRES      | 20/3     | LVCMOS33_IN   | PL9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRESout   | 7/3      | LVCMOS33_OUT  | PL3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nSWE      | 35/2     | LVCMOS33_OUT  | PB9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nWE       | 19/3     | LVCMOS33_IN   | PL8D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | nDoutOE               | LOCATED    | LVCMOS33_OUT  | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      | RA[9]                 | LOCATED    | LVCMOS33_IN   | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      | RA[10]                | LOCATED    | LVCMOS33_IN   | PL3A  | PCLKT3_2      |           |           |
+| 4/3      | RA[4]                 | LOCATED    | LVCMOS33_IN   | PL3B  | PCLKC3_2      |           |           |
+| 7/3      | nRESout               | LOCATED    | LVCMOS33_OUT  | PL3C  |               |           |           |
+| 8/3      | RA[11]                | LOCATED    | LVCMOS33_IN   | PL3D  |               |           |           |
+| 9/3      | RA[12]                | LOCATED    | LVCMOS33_IN   | PL4A  |               |           |           |
+| 10/3     | RA[13]                | LOCATED    | LVCMOS33_IN   | PL4B  |               |           |           |
+| 12/3     | nIRQout               | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | RA[14]                | LOCATED    | LVCMOS33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | RA[15]                | LOCATED    | LVCMOS33_IN   | PL5C  |               |           |           |
+| 15/3     | nIOSEL                | LOCATED    | LVCMOS33_IN   | PL5D  |               |           |           |
+| 16/3     | nDEVSEL               | LOCATED    | LVCMOS33_IN   | PL8A  |               |           |           |
+| 17/3     | PHI0                  | LOCATED    | LVCMOS33_IN   | PL8B  |               |           |           |
+| 18/3     | nIOSTRB               | LOCATED    | LVCMOS33_IN   | PL8C  |               |           |           |
+| 19/3     | nWE                   | LOCATED    | LVCMOS33_IN   | PL8D  |               |           |           |
+| 20/3     | nRES                  | LOCATED    | LVCMOS33_IN   | PL9A  | PCLKT3_0      |           |           |
+| 21/3     | SD[2]                 | LOCATED    | LVCMOS33_BIDI | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | SD[1]                 | LOCATED    | LVCMOS33_BIDI | PL10C |               |           |           |
+| 25/3     | SD[0]                 | LOCATED    | LVCMOS33_BIDI | PL10D |               |           |           |
+| 27/2     | SD[3]                 | LOCATED    | LVCMOS33_BIDI | PB4C  | CSSPIN        |           |           |
+| 28/2     | SD[4]                 | LOCATED    | LVCMOS33_BIDI | PB4D  |               |           |           |
+| 29/2     | SD[5]                 | LOCATED    | LVCMOS33_BIDI | PB6A  |               |           |           |
+| 30/2     | SD[6]                 | LOCATED    | LVCMOS33_BIDI | PB6B  |               |           |           |
+| 31/2     | SD[7]                 | LOCATED    | LVCMOS33_BIDI | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB6D  | SO/SPISO      |           |           |
+| 34/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB9A  | PCLKT2_0      |           |           |
+| 35/2     | nSWE                  | LOCATED    | LVCMOS33_OUT  | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PB11C |               |           |           |
+| 37/2     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PB11D |               |           |           |
+| 38/2     | RCLK                  | LOCATED    | LVCMOS33_IN   | PB11A | PCLKT2_1      |           |           |
+| 39/2     | RCLKout               | LOCATED    | LVCMOS33_OUT  | PB11B | PCLKC2_1      |           |           |
+| 40/2     | RCKE                  | LOCATED    | LVCMOS33_OUT  | PB15A |               |           |           |
+| 41/2     | nRCS                  | LOCATED    | LVCMOS33_OUT  | PB15B |               |           |           |
+| 42/2     | SA[12]                | LOCATED    | LVCMOS33_OUT  | PB18A |               |           |           |
+| 43/2     | SBA[0]                | LOCATED    | LVCMOS33_OUT  | PB18B |               |           |           |
+| 45/2     | SA[11]                | LOCATED    | LVCMOS33_OUT  | PB18C |               |           |           |
+| 47/2     | SA[10]                | LOCATED    | LVCMOS33_OUT  | PB18D |               |           |           |
+| 48/2     | SBA[1]                | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
+| 49/2     | SA[9]                 | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | SA[4]                 | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | SA[5]                 | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | SA[8]                 | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | SA[0]                 | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | SA[7]                 | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
+| 58/1     | SA[2]                 | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
+| 59/1     | SA[1]                 | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
+| 60/1     | SA[3]                 | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
+| 62/1     | SA[6]                 | LOCATED    | LVCMOS33_OUT  | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | SetFW[1]              | LOCATED    | LVCMOS33_IN   | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | SetFW[0]              | LOCATED    | LVCMOS33_IN   | PR5B  | DQS0N         |           |           |
+| 65/1     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PR5A  | DQS0          |           |           |
+| 66/1     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PR4D  | DQ0           |           |           |
+| 67/1     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PR4C  | DQ0           |           |           |
+| 68/1     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PR4B  | DQ0           |           |           |
+| 69/1     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PR4A  | DQ0           |           |           |
+| 70/1     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PR3B  | DQ0           |           |           |
+| 71/1     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PR3A  | DQ0           |           |           |
+| 74/1     | RA[0]                 | LOCATED    | LVCMOS33_IN   | PR2B  | DQ0           |           |           |
+| 75/1     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
+| 77/0     | nDinOE                | LOCATED    | LVCMOS33_OUT  | PT17C | INITN         |           |           |
+| 78/0     | RA[1]                 | LOCATED    | LVCMOS33_IN   | PT16C |               |           |           |
+| 81/0     | LED                   | LOCATED    | LVCMOS33_OUT  | PT15D | PROGRAMN      |           |           |
+| 82/0     |     unused, PULL:DOWN |            |               | PT15C | JTAGENB       |           |           |
+| 83/0     | RA[2]                 | LOCATED    | LVCMOS33_IN   | PT15B |               |           |           |
+| 84/0     | RA[3]                 | LOCATED    | LVCMOS33_IN   | PT15A |               |           |           |
+| 85/0     | RA[5]                 | LOCATED    | LVCMOS33_IN   | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | RA[6]                 | LOCATED    | LVCMOS33_IN   | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | RA[7]                 | LOCATED    | LVCMOS33_IN   | PT12B | PCLKC0_1      |           |           |
+| 88/0     | nFCS                  | LOCATED    | LVCMOS33_OUT  | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | FCK                   | LOCATED    | LVCMOS33_OUT  | PT10B |               |           |           |
+| 97/0     | MOSI                  | LOCATED    | LVCMOS33_BIDI | PT10A |               |           |           |
+| 98/0     | MISO                  | LOCATED    | LVCMOS33_IN   | PT9B  |               |           |           |
+| 99/0     | RA[8]                 | LOCATED    | LVCMOS33_IN   | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "DQMH"  SITE  "34";
+LOCATE  COMP  "DQML"  SITE  "32";
+LOCATE  COMP  "FCK"  SITE  "96";
+LOCATE  COMP  "LED"  SITE  "81";
+LOCATE  COMP  "MISO"  SITE  "98";
+LOCATE  COMP  "MOSI"  SITE  "97";
+LOCATE  COMP  "PHI0"  SITE  "17";
+LOCATE  COMP  "RA[0]"  SITE  "74";
+LOCATE  COMP  "RA[10]"  SITE  "3";
+LOCATE  COMP  "RA[11]"  SITE  "8";
+LOCATE  COMP  "RA[12]"  SITE  "9";
+LOCATE  COMP  "RA[13]"  SITE  "10";
+LOCATE  COMP  "RA[14]"  SITE  "13";
+LOCATE  COMP  "RA[15]"  SITE  "14";
+LOCATE  COMP  "RA[1]"  SITE  "78";
+LOCATE  COMP  "RA[2]"  SITE  "83";
+LOCATE  COMP  "RA[3]"  SITE  "84";
+LOCATE  COMP  "RA[4]"  SITE  "4";
+LOCATE  COMP  "RA[5]"  SITE  "85";
+LOCATE  COMP  "RA[6]"  SITE  "86";
+LOCATE  COMP  "RA[7]"  SITE  "87";
+LOCATE  COMP  "RA[8]"  SITE  "99";
+LOCATE  COMP  "RA[9]"  SITE  "2";
+LOCATE  COMP  "RCKE"  SITE  "40";
+LOCATE  COMP  "RCLK"  SITE  "38";
+LOCATE  COMP  "RCLKout"  SITE  "39";
+LOCATE  COMP  "RD[0]"  SITE  "65";
+LOCATE  COMP  "RD[1]"  SITE  "66";
+LOCATE  COMP  "RD[2]"  SITE  "67";
+LOCATE  COMP  "RD[3]"  SITE  "68";
+LOCATE  COMP  "RD[4]"  SITE  "69";
+LOCATE  COMP  "RD[5]"  SITE  "70";
+LOCATE  COMP  "RD[6]"  SITE  "71";
+LOCATE  COMP  "RD[7]"  SITE  "75";
+LOCATE  COMP  "SA[0]"  SITE  "54";
+LOCATE  COMP  "SA[10]"  SITE  "47";
+LOCATE  COMP  "SA[11]"  SITE  "45";
+LOCATE  COMP  "SA[12]"  SITE  "42";
+LOCATE  COMP  "SA[1]"  SITE  "59";
+LOCATE  COMP  "SA[2]"  SITE  "58";
+LOCATE  COMP  "SA[3]"  SITE  "60";
+LOCATE  COMP  "SA[4]"  SITE  "51";
+LOCATE  COMP  "SA[5]"  SITE  "52";
+LOCATE  COMP  "SA[6]"  SITE  "62";
+LOCATE  COMP  "SA[7]"  SITE  "57";
+LOCATE  COMP  "SA[8]"  SITE  "53";
+LOCATE  COMP  "SA[9]"  SITE  "49";
+LOCATE  COMP  "SBA[0]"  SITE  "43";
+LOCATE  COMP  "SBA[1]"  SITE  "48";
+LOCATE  COMP  "SD[0]"  SITE  "25";
+LOCATE  COMP  "SD[1]"  SITE  "24";
+LOCATE  COMP  "SD[2]"  SITE  "21";
+LOCATE  COMP  "SD[3]"  SITE  "27";
+LOCATE  COMP  "SD[4]"  SITE  "28";
+LOCATE  COMP  "SD[5]"  SITE  "29";
+LOCATE  COMP  "SD[6]"  SITE  "30";
+LOCATE  COMP  "SD[7]"  SITE  "31";
+LOCATE  COMP  "SetFW[0]"  SITE  "64";
+LOCATE  COMP  "SetFW[1]"  SITE  "63";
+LOCATE  COMP  "nCAS"  SITE  "36";
+LOCATE  COMP  "nDEVSEL"  SITE  "16";
+LOCATE  COMP  "nDinOE"  SITE  "77";
+LOCATE  COMP  "nDoutOE"  SITE  "1";
+LOCATE  COMP  "nFCS"  SITE  "88";
+LOCATE  COMP  "nIOSEL"  SITE  "15";
+LOCATE  COMP  "nIOSTRB"  SITE  "18";
+LOCATE  COMP  "nIRQout"  SITE  "12";
+LOCATE  COMP  "nRAS"  SITE  "37";
+LOCATE  COMP  "nRCS"  SITE  "41";
+LOCATE  COMP  "nRES"  SITE  "20";
+LOCATE  COMP  "nRESout"  SITE  "7";
+LOCATE  COMP  "nSWE"  SITE  "35";
+LOCATE  COMP  "nWE"  SITE  "19";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:39:01 2024
+

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.par

@@ -0,0 +1,233 @@
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:38:53 2024
+
+C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
+GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
+GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
+//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
+
+
+Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
+
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -            -            -            -            10           Completed
+
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "GR8RAM_LCMXO2_1200HC_impl1_map.ncd"
+Thu Jun 13 00:38:53 2024
+
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
+Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
+Design name: GR8RAM
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+Device utilization summary:
+
+   PIO (prelim)   73+4(JTAG)/108     71% used
+                  73+4(JTAG)/80      96% bonded
+   IOLOGIC           51/108          47% used
+
+   SLICE            136/640          21% used
+
+   GSR                1/1           100% used
+
+
+Number of Signals: 430
+Number of Connections: 1211
+
+Pin Constraint Summary:
+   73 out of 73 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 80)
+    PHI0_c (driver: PHI0, clk load #: 14)
+
+WARNING - par: Signal "PHI0_c" is selected to use Primary clock resources. However, its driver comp "PHI0" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
+
+Signal nRESr is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 87858.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  86903
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+------------------ Clock Report ------------------
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 1 out of 108 (0%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "38 (PB11A)", clk load = 80
+  PRIMARY "PHI0_c" from comp "PHI0" on PIO site "17 (PL8B)", clk load = 14
+  SECONDARY "FCKout120" from F0 on comp "SLICE_54" on site "R7C12B", clk load = 0, ce load = 0, sr load = 13
+
+  PRIMARY  : 2 out of 8 (25%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+--------------- End of Clock Report ---------------
+
+
+I/O Usage Summary (final):
+   73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
+   73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
+   Number of PIO comps: 73; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
+| 2        | 20 / 20 (100%) | 3.3V       | -         |
+| 3        | 20 / 20 (100%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 3 secs 
+
+Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+-----------------------------------------------------------------
+INFO - par: ASE feature is off due to non timing-driven settings.  
+-----------------------------------------------------------------
+
+0 connections routed; 1211 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 9 secs 
+
+Start NBR router at 00:39:02 06/13/24
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 00:39:02 06/13/24
+
+Start NBR section for initial routing at 00:39:02 06/13/24
+Level 4, iteration 1
+19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 00:39:02 06/13/24
+Level 4, iteration 1
+4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Start NBR section for re-routing at 00:39:02 06/13/24
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Start NBR section for post-routing at 00:39:02 06/13/24
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : <n/a>
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 8 secs 
+Total REAL time: 9 secs 
+Completely routed.
+End of route.  1211 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = <n/a>
+PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
+PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
+PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.prf

@@ -0,0 +1,82 @@
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Thu Jun 13 00:38:53 2024
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "RD[0]" SITE "65" ;
+LOCATE COMP "nFCS" SITE "88" ;
+LOCATE COMP "RCLKout" SITE "39" ;
+LOCATE COMP "RCLK" SITE "38" ;
+LOCATE COMP "MOSI" SITE "97" ;
+LOCATE COMP "MISO" SITE "98" ;
+LOCATE COMP "FCK" SITE "96" ;
+LOCATE COMP "SD[7]" SITE "31" ;
+LOCATE COMP "SD[6]" SITE "30" ;
+LOCATE COMP "SD[5]" SITE "29" ;
+LOCATE COMP "SD[4]" SITE "28" ;
+LOCATE COMP "SD[3]" SITE "27" ;
+LOCATE COMP "SD[2]" SITE "21" ;
+LOCATE COMP "SD[1]" SITE "24" ;
+LOCATE COMP "SD[0]" SITE "25" ;
+LOCATE COMP "RCKE" SITE "40" ;
+LOCATE COMP "DQMH" SITE "34" ;
+LOCATE COMP "DQML" SITE "32" ;
+LOCATE COMP "nSWE" SITE "35" ;
+LOCATE COMP "nCAS" SITE "36" ;
+LOCATE COMP "nRAS" SITE "37" ;
+LOCATE COMP "nRCS" SITE "41" ;
+LOCATE COMP "SA[12]" SITE "42" ;
+LOCATE COMP "SA[11]" SITE "45" ;
+LOCATE COMP "SA[10]" SITE "47" ;
+LOCATE COMP "SA[9]" SITE "49" ;
+LOCATE COMP "SA[8]" SITE "53" ;
+LOCATE COMP "SA[7]" SITE "57" ;
+LOCATE COMP "SA[6]" SITE "62" ;
+LOCATE COMP "SA[5]" SITE "52" ;
+LOCATE COMP "SA[4]" SITE "51" ;
+LOCATE COMP "SA[3]" SITE "60" ;
+LOCATE COMP "SA[2]" SITE "58" ;
+LOCATE COMP "SA[1]" SITE "59" ;
+LOCATE COMP "SA[0]" SITE "54" ;
+LOCATE COMP "SBA[1]" SITE "48" ;
+LOCATE COMP "SBA[0]" SITE "43" ;
+LOCATE COMP "nIOSTRB" SITE "18" ;
+LOCATE COMP "nDEVSEL" SITE "16" ;
+LOCATE COMP "nIOSEL" SITE "15" ;
+LOCATE COMP "nDinOE" SITE "77" ;
+LOCATE COMP "nDoutOE" SITE "1" ;
+LOCATE COMP "RD[7]" SITE "75" ;
+LOCATE COMP "RD[6]" SITE "71" ;
+LOCATE COMP "RD[5]" SITE "70" ;
+LOCATE COMP "RD[4]" SITE "69" ;
+LOCATE COMP "RD[3]" SITE "68" ;
+LOCATE COMP "RD[2]" SITE "67" ;
+LOCATE COMP "RD[1]" SITE "66" ;
+LOCATE COMP "nWE" SITE "19" ;
+LOCATE COMP "RA[15]" SITE "14" ;
+LOCATE COMP "RA[14]" SITE "13" ;
+LOCATE COMP "RA[13]" SITE "10" ;
+LOCATE COMP "RA[12]" SITE "9" ;
+LOCATE COMP "RA[11]" SITE "8" ;
+LOCATE COMP "RA[10]" SITE "3" ;
+LOCATE COMP "RA[9]" SITE "2" ;
+LOCATE COMP "RA[8]" SITE "99" ;
+LOCATE COMP "RA[7]" SITE "87" ;
+LOCATE COMP "RA[6]" SITE "86" ;
+LOCATE COMP "RA[5]" SITE "85" ;
+LOCATE COMP "RA[4]" SITE "4" ;
+LOCATE COMP "RA[3]" SITE "84" ;
+LOCATE COMP "RA[2]" SITE "83" ;
+LOCATE COMP "RA[1]" SITE "78" ;
+LOCATE COMP "RA[0]" SITE "74" ;
+LOCATE COMP "LED" SITE "81" ;
+LOCATE COMP "SetFW[1]" SITE "63" ;
+LOCATE COMP "SetFW[0]" SITE "64" ;
+LOCATE COMP "nIRQout" SITE "12" ;
+LOCATE COMP "nRESout" SITE "7" ;
+LOCATE COMP "nRES" SITE "20" ;
+LOCATE COMP "PHI0" SITE "17" ;
+SCHEMATIC END ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+VOLTAGE 3.300 V;
+COMMERCIAL ;

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.pt

@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 4
+-sphld m

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srf

@@ -0,0 +1,561 @@
+#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr  1 2019
+#install: C:\lscc\diamond\3.11_x64\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Thu Jun 13 00:38:45 2024
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
+Verilog syntax check successful!
+File \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v changed - recompiling
+Selecting top level module GR8RAM
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
+Running optimization stage 1 on ODDRXE .......
+@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
+Running optimization stage 1 on GR8RAM .......
+Running optimization stage 2 on GR8RAM .......
+@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
+Running optimization stage 2 on ODDRXE .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:47 2024
+
+###########################################################]
+# Thu Jun 13 00:38:47 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt 
+Printing clock  summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":36:1:36:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+syn_allowed_resources : blockrams=7  set on top level netlist GR8RAM
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start           Requested     Requested     Clock        Clock                   Clock
+Level     Clock           Frequency     Period        Type         Group                   Load 
+------------------------------------------------------------------------------------------------
+0 -       GR8RAM|RCLK     100.0 MHz     10.000        inferred     Inferred_clkgroup_1     104  
+                                                                                                
+0 -       GR8RAM|PHI0     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     18   
+================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                Clock     Source         Clock Pin        Non-clock Pin       Non-clock Pin     
+Clock           Load      Pin            Seq Example      Seq Example         Comb Example      
+------------------------------------------------------------------------------------------------
+GR8RAM|RCLK     104       RCLK(port)     PHI0r[4:1].C     -                   un1_RCLK.I[0](inv)
+                                                                                                
+GR8RAM|PHI0     18        PHI0(port)     RAr[11:0].C      PHI0r[4:1].D[0]     nDoutOE.I[0](inv) 
+================================================================================================
+
+@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+2 non-gated/non-generated clock tree(s) driving 118 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                Unconstrained_port     104        nRESf          
+@KP:ckid0_1       PHI0                Unconstrained_port     14         CXXXr          
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Jun 13 00:38:48 2024
+
+###########################################################]
+# Thu Jun 13 00:38:48 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
+@N: FX493 |Applying initial value "000" on instance IS[2:0].
+@N: FX493 |Applying initial value "0000" on instance PS[3:0].
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
+
+@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     1.70ns		 247 /       118
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 166MB)
+
+Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 167MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
+N-2018.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
+@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Thu Jun 13 00:38:51 2024
+#
+
+
+Top view:               GR8RAM
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 1.955
+
+                   Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group              
+---------------------------------------------------------------------------------------------------------------------
+GR8RAM|PHI0        100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_0
+GR8RAM|RCLK        100.0 MHz     134.3 MHz     10.000        7.448         1.955     inferred     Inferred_clkgroup_1
+System             100.0 MHz     NA            10.000        NA            NA        system       system_clkgroup    
+=====================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+----------------------------------------------------------------------------------------------------------------
+Starting     Ending       |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+----------------------------------------------------------------------------------------------------------------
+GR8RAM|PHI0  GR8RAM|RCLK  |  Diff grp    -      |  No paths    -      |  Diff grp    -      |  No paths    -    
+GR8RAM|RCLK  GR8RAM|RCLK  |  10.000      2.552  |  No paths    -      |  5.000       1.955  |  No paths    -    
+================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: GR8RAM|RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                  Starting                                           Arrival          
+Instance          Reference       Type         Pin     Net           Time        Slack
+                  Clock                                                               
+--------------------------------------------------------------------------------------
+PS[3]             GR8RAM|RCLK     FD1S3AX      Q       PS[3]         1.309       1.955
+PS[0]             GR8RAM|RCLK     FD1S3AX      Q       PS[0]         1.305       1.958
+PS[2]             GR8RAM|RCLK     FD1S3AX      Q       PS[2]         1.296       1.968
+PS[1]             GR8RAM|RCLK     FD1S3AX      Q       PS[1]         1.288       1.976
+Addr[1]           GR8RAM|RCLK     FD1S3DX      Q       Addr[1]       1.232       2.009
+SetFWr_0io[1]     GR8RAM|RCLK     IFS1P3DX     Q       SetFWr[1]     1.232       2.009
+Addr[2]           GR8RAM|RCLK     FD1S3DX      Q       Addr[2]       1.228       2.013
+Addr[3]           GR8RAM|RCLK     FD1S3DX      Q       Addr[3]       1.220       2.021
+Addr[10]          GR8RAM|RCLK     FD1S3DX      Q       Addr[10]      1.220       2.021
+Addr[4]           GR8RAM|RCLK     FD1S3DX      Q       Addr[4]       1.204       2.037
+======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required          
+Instance       Reference       Type         Pin     Net          Time         Slack
+               Clock                                                               
+-----------------------------------------------------------------------------------
+RDD[0]         GR8RAM|RCLK     FD1P3AX      SP      RDD37        4.528        1.955
+RDD_0io[1]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[2]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[3]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[4]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[5]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[6]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[7]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[1]     GR8RAM|RCLK     OFS1P3DX     D       RDD_8[1]     5.089        2.009
+RDD_0io[4]     GR8RAM|RCLK     OFS1P3DX     D       RDD_8[4]     5.089        2.009
+===================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.528
+
+    - Propagation time:                      2.573
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     1.955
+
+    Number of logic level(s):                1
+    Starting point:                          PS[3] / Q
+    Ending point:                            RDD[0] / SP
+    The start point is clocked by            GR8RAM|RCLK [rising] on pin CK
+    The end   point is clocked by            GR8RAM|RCLK [falling] on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PS[3]              FD1S3AX      Q        Out     1.309     1.309       -         
+PS[3]              Net          -        -       -         -           28        
+RDD37_0_a2         ORCALUT4     D        In      0.000     1.309       -         
+RDD37_0_a2         ORCALUT4     Z        Out     1.265     2.573       -         
+RDD37              Net          -        -       -         -           8         
+RDD[0]             FD1P3AX      SP       In      0.000     2.573       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_1200hc-4
+
+Register bits: 118 of 1280 (9%)
+PIC Latch:       0
+I/O cells:       73
+
+
+Details:
+BB:             17
+CCU2D:          13
+FD1P3AX:        24
+FD1S3AX:        17
+FD1S3DX:        27
+GSR:            1
+IB:             26
+IFS1P3DX:       18
+INV:            7
+OB:             28
+OBZ:            2
+ODDRXE:         1
+OFS1P3BX:       7
+OFS1P3DX:       12
+OFS1P3IX:       10
+OFS1P3JX:       3
+ORCALUT4:       240
+PFUMX:          7
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 171MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Thu Jun 13 00:38:51 2024
+
+###########################################################]

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.srr

@@ -0,0 +1,561 @@
+#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr  1 2019
+#install: C:\lscc\diamond\3.11_x64\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Thu Jun 13 00:38:45 2024
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
+Verilog syntax check successful!
+File \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v changed - recompiling
+Selecting top level module GR8RAM
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
+Running optimization stage 1 on ODDRXE .......
+@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
+Running optimization stage 1 on GR8RAM .......
+Running optimization stage 2 on GR8RAM .......
+@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
+Running optimization stage 2 on ODDRXE .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:47 2024
+
+###########################################################]
+# Thu Jun 13 00:38:47 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt 
+Printing clock  summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":36:1:36:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+syn_allowed_resources : blockrams=7  set on top level netlist GR8RAM
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start           Requested     Requested     Clock        Clock                   Clock
+Level     Clock           Frequency     Period        Type         Group                   Load 
+------------------------------------------------------------------------------------------------
+0 -       GR8RAM|RCLK     100.0 MHz     10.000        inferred     Inferred_clkgroup_1     104  
+                                                                                                
+0 -       GR8RAM|PHI0     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     18   
+================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                Clock     Source         Clock Pin        Non-clock Pin       Non-clock Pin     
+Clock           Load      Pin            Seq Example      Seq Example         Comb Example      
+------------------------------------------------------------------------------------------------
+GR8RAM|RCLK     104       RCLK(port)     PHI0r[4:1].C     -                   un1_RCLK.I[0](inv)
+                                                                                                
+GR8RAM|PHI0     18        PHI0(port)     RAr[11:0].C      PHI0r[4:1].D[0]     nDoutOE.I[0](inv) 
+================================================================================================
+
+@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+2 non-gated/non-generated clock tree(s) driving 118 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                Unconstrained_port     104        nRESf          
+@KP:ckid0_1       PHI0                Unconstrained_port     14         CXXXr          
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Jun 13 00:38:48 2024
+
+###########################################################]
+# Thu Jun 13 00:38:48 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
+@N: FX493 |Applying initial value "000" on instance IS[2:0].
+@N: FX493 |Applying initial value "0000" on instance PS[3:0].
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
+
+@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     1.70ns		 247 /       118
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 166MB)
+
+Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 167MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
+N-2018.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
+@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Thu Jun 13 00:38:51 2024
+#
+
+
+Top view:               GR8RAM
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 1.955
+
+                   Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group              
+---------------------------------------------------------------------------------------------------------------------
+GR8RAM|PHI0        100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_0
+GR8RAM|RCLK        100.0 MHz     134.3 MHz     10.000        7.448         1.955     inferred     Inferred_clkgroup_1
+System             100.0 MHz     NA            10.000        NA            NA        system       system_clkgroup    
+=====================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+----------------------------------------------------------------------------------------------------------------
+Starting     Ending       |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+----------------------------------------------------------------------------------------------------------------
+GR8RAM|PHI0  GR8RAM|RCLK  |  Diff grp    -      |  No paths    -      |  Diff grp    -      |  No paths    -    
+GR8RAM|RCLK  GR8RAM|RCLK  |  10.000      2.552  |  No paths    -      |  5.000       1.955  |  No paths    -    
+================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: GR8RAM|RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                  Starting                                           Arrival          
+Instance          Reference       Type         Pin     Net           Time        Slack
+                  Clock                                                               
+--------------------------------------------------------------------------------------
+PS[3]             GR8RAM|RCLK     FD1S3AX      Q       PS[3]         1.309       1.955
+PS[0]             GR8RAM|RCLK     FD1S3AX      Q       PS[0]         1.305       1.958
+PS[2]             GR8RAM|RCLK     FD1S3AX      Q       PS[2]         1.296       1.968
+PS[1]             GR8RAM|RCLK     FD1S3AX      Q       PS[1]         1.288       1.976
+Addr[1]           GR8RAM|RCLK     FD1S3DX      Q       Addr[1]       1.232       2.009
+SetFWr_0io[1]     GR8RAM|RCLK     IFS1P3DX     Q       SetFWr[1]     1.232       2.009
+Addr[2]           GR8RAM|RCLK     FD1S3DX      Q       Addr[2]       1.228       2.013
+Addr[3]           GR8RAM|RCLK     FD1S3DX      Q       Addr[3]       1.220       2.021
+Addr[10]          GR8RAM|RCLK     FD1S3DX      Q       Addr[10]      1.220       2.021
+Addr[4]           GR8RAM|RCLK     FD1S3DX      Q       Addr[4]       1.204       2.037
+======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required          
+Instance       Reference       Type         Pin     Net          Time         Slack
+               Clock                                                               
+-----------------------------------------------------------------------------------
+RDD[0]         GR8RAM|RCLK     FD1P3AX      SP      RDD37        4.528        1.955
+RDD_0io[1]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[2]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[3]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[4]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[5]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[6]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[7]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[1]     GR8RAM|RCLK     OFS1P3DX     D       RDD_8[1]     5.089        2.009
+RDD_0io[4]     GR8RAM|RCLK     OFS1P3DX     D       RDD_8[4]     5.089        2.009
+===================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.528
+
+    - Propagation time:                      2.573
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     1.955
+
+    Number of logic level(s):                1
+    Starting point:                          PS[3] / Q
+    Ending point:                            RDD[0] / SP
+    The start point is clocked by            GR8RAM|RCLK [rising] on pin CK
+    The end   point is clocked by            GR8RAM|RCLK [falling] on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PS[3]              FD1S3AX      Q        Out     1.309     1.309       -         
+PS[3]              Net          -        -       -         -           28        
+RDD37_0_a2         ORCALUT4     D        In      0.000     1.309       -         
+RDD37_0_a2         ORCALUT4     Z        Out     1.265     2.573       -         
+RDD37              Net          -        -       -         -           8         
+RDD[0]             FD1P3AX      SP       In      0.000     2.573       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_1200hc-4
+
+Register bits: 118 of 1280 (9%)
+PIC Latch:       0
+I/O cells:       73
+
+
+Details:
+BB:             17
+CCU2D:          13
+FD1P3AX:        24
+FD1S3AX:        17
+FD1S3DX:        27
+GSR:            1
+IB:             26
+IFS1P3DX:       18
+INV:            7
+OB:             28
+OBZ:            2
+ODDRXE:         1
+OFS1P3BX:       7
+OFS1P3DX:       12
+OFS1P3IX:       10
+OFS1P3JX:       3
+ORCALUT4:       240
+PFUMX:          7
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 171MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Thu Jun 13 00:38:51 2024
+
+###########################################################]

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1.t2b

@@ -0,0 +1,5 @@
+
+
+-g RamCfg:Reset
+
+-path "//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC"  

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_bgn.html

@@ -0,0 +1,152 @@
+<HTML>
+<HEAD><TITLE>Bitgen Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{␍    font-family:'Courier New', monospace;␍    color: #000000;␍    font-size:88%;␍    background-color: #ffffff;␍}␍h1 {␍    font-weight: bold;␍    margin-top: 24px;␍    margin-bottom: 10px;␍    border-bottom: 3px solid #000;    font-size: 1em;␍}␍h2 {␍    font-weight: bold;␍    margin-top: 18px;␍    margin-bottom: 5px;␍    font-size: 0.90em;␍}␍h3 {␍    font-weight: bold;␍    margin-top: 12px;␍    margin-bottom: 5px;␍    font-size: 0.80em;␍}␍p {␍    font-size:78%;␍}␍P.Table {␍    margin-top: 4px;␍    margin-bottom: 4px;␍    margin-right: 4px;␍    margin-left: 4px;␍}␍table␍{␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    border-collapse: collapse;␍}␍th {␍    font-weight:bold;␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    text-align:left;␍    font-size:78%;␍}␍td {␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    font-size:78%;␍}␍a {␍    color:#013C9A;␍    text-decoration:none;␍}␍␍a:visited {␍    color:#013C9A;␍}␍␍a:hover, a:active {␍    text-decoration:underline;␍    color:#5BAFD4;␍}␍.pass␍{␍background-color: #00ff00;␍}␍.fail␍{␍background-color: #ff0000;␍}␍.comment␍{␍    font-size: 90%;␍    font-style: italic;␍}␍
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:38:22 2024
+
+
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml GR8RAM_LCMXO2_1200HC_impl1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf 
+
+Loading design for application Bitgen from file GR8RAM_LCMXO2_1200HC_impl1.ncd.
+Design name: GR8RAM
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from GR8RAM_LCMXO2_1200HC_impl1.prf.
+
+<A name="bgn_ps"></A>
+<B><U><big>Preference Summary:</big></U></B>
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "GR8RAM_LCMXO2_1200HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 3 secs 
+Total REAL Time: 4 secs 
+Peak Memory Usage: 275 MB
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_cck.rpt

@@ -0,0 +1,161 @@
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+
+# Written on Thu Jun 13 00:38:48 2024
+
+##### DESIGN INFO #######################################################
+
+Top View:                "GR8RAM"
+Constraint File(s):      (none)
+
+
+
+
+##### SUMMARY ############################################################
+
+Found 0 issues in 0 out of 0 constraints
+
+
+##### DETAILS ############################################################
+
+
+
+Clock Relationships
+*******************
+
+Starting        Ending          |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
+-------------------------------------------------------------------------------------------------------------------------------------------
+GR8RAM|PHI0     GR8RAM|RCLK     |     Diff grp         |     No paths         |     Diff grp         |     No paths                         
+GR8RAM|RCLK     GR8RAM|RCLK     |     10.000           |     No paths         |     5.000            |     No paths                         
+===========================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+Unconstrained Start/End Points
+******************************
+
+p:DQMH
+p:DQML
+p:FCK
+p:LED
+p:MISO
+p:MOSI (bidir end point)
+p:MOSI (bidir start point)
+p:RA[0]
+p:RA[1]
+p:RA[2]
+p:RA[3]
+p:RA[4]
+p:RA[5]
+p:RA[6]
+p:RA[7]
+p:RA[8]
+p:RA[9]
+p:RA[10]
+p:RA[11]
+p:RA[12]
+p:RA[13]
+p:RA[14]
+p:RA[15]
+p:RCKE
+p:RCLKout
+p:RD[0] (bidir end point)
+p:RD[0] (bidir start point)
+p:RD[1] (bidir end point)
+p:RD[1] (bidir start point)
+p:RD[2] (bidir end point)
+p:RD[2] (bidir start point)
+p:RD[3] (bidir end point)
+p:RD[3] (bidir start point)
+p:RD[4] (bidir end point)
+p:RD[4] (bidir start point)
+p:RD[5] (bidir end point)
+p:RD[5] (bidir start point)
+p:RD[6] (bidir end point)
+p:RD[6] (bidir start point)
+p:RD[7] (bidir end point)
+p:RD[7] (bidir start point)
+p:SA[0]
+p:SA[1]
+p:SA[2]
+p:SA[3]
+p:SA[4]
+p:SA[5]
+p:SA[6]
+p:SA[7]
+p:SA[8]
+p:SA[9]
+p:SA[10]
+p:SA[11]
+p:SA[12]
+p:SBA[0]
+p:SBA[1]
+p:SD[0] (bidir end point)
+p:SD[0] (bidir start point)
+p:SD[1] (bidir end point)
+p:SD[1] (bidir start point)
+p:SD[2] (bidir end point)
+p:SD[2] (bidir start point)
+p:SD[3] (bidir end point)
+p:SD[3] (bidir start point)
+p:SD[4] (bidir end point)
+p:SD[4] (bidir start point)
+p:SD[5] (bidir end point)
+p:SD[5] (bidir start point)
+p:SD[6] (bidir end point)
+p:SD[6] (bidir start point)
+p:SD[7] (bidir end point)
+p:SD[7] (bidir start point)
+p:SetFW[0]
+p:SetFW[1]
+p:nCAS
+p:nDEVSEL
+p:nDinOE
+p:nFCS
+p:nIOSEL
+p:nIOSTRB
+p:nIRQout
+p:nRAS
+p:nRCS
+p:nRES
+p:nRESout
+p:nSWE
+p:nWE
+
+
+Inapplicable constraints
+************************
+
+(none)
+
+
+Applicable constraints with issues
+**********************************
+
+(none)
+
+
+Constraints with matching wildcard expressions
+**********************************************
+
+(none)
+
+
+Library Report
+**************
+
+
+# End of Constraint Checker Report

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_map.asd

@@ -0,0 +1,15 @@
+[ActiveSupport MAP]
+Device = LCMXO2-1200HC;
+Package = TQFP100;
+Performance = 4;
+LUTS_avail = 1280;
+LUTS_used = 268;
+FF_avail = 1360;
+FF_used = 118;
+INPUT_LVCMOS33 = 26;
+OUTPUT_LVCMOS33 = 30;
+BIDI_LVCMOS33 = 17;
+IO_avail = 80;
+IO_used = 73;
+EBR_avail = 7;
+EBR_used = 0;

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_map.cam

@@ -0,0 +1,98 @@
+[ START MERGED ]
+FCKOE_i FCKOE
+nRESr_i nRESr
+PS_i[0] PS[0]
+RDD_0_.CN RCLK_c
+MOSIOE_i MOSIOE
+SDOE_i SDOE
+[ END MERGED ]
+[ START CLIPPED ]
+LS_s_0_S1[13]
+LS_s_0_COUT[13]
+un1_Addr_1_cry_0_0_S0
+N_2
+un1_Addr_1_s_7_0_S1
+un1_Addr_1_s_7_0_COUT
+LS_cry_0_S0[0]
+N_1
+[ END CLIPPED ]
+[ START DESIGN PREFS ]
+SCHEMATIC START ;
+# map:  version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Thu Jun 13 00:38:53 2024
+
+SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
+LOCATE COMP "RD[0]" SITE "65" ;
+LOCATE COMP "nFCS" SITE "88" ;
+LOCATE COMP "RCLKout" SITE "39" ;
+LOCATE COMP "RCLK" SITE "38" ;
+LOCATE COMP "MOSI" SITE "97" ;
+LOCATE COMP "MISO" SITE "98" ;
+LOCATE COMP "FCK" SITE "96" ;
+LOCATE COMP "SD[7]" SITE "31" ;
+LOCATE COMP "SD[6]" SITE "30" ;
+LOCATE COMP "SD[5]" SITE "29" ;
+LOCATE COMP "SD[4]" SITE "28" ;
+LOCATE COMP "SD[3]" SITE "27" ;
+LOCATE COMP "SD[2]" SITE "21" ;
+LOCATE COMP "SD[1]" SITE "24" ;
+LOCATE COMP "SD[0]" SITE "25" ;
+LOCATE COMP "RCKE" SITE "40" ;
+LOCATE COMP "DQMH" SITE "34" ;
+LOCATE COMP "DQML" SITE "32" ;
+LOCATE COMP "nSWE" SITE "35" ;
+LOCATE COMP "nCAS" SITE "36" ;
+LOCATE COMP "nRAS" SITE "37" ;
+LOCATE COMP "nRCS" SITE "41" ;
+LOCATE COMP "SA[12]" SITE "42" ;
+LOCATE COMP "SA[11]" SITE "45" ;
+LOCATE COMP "SA[10]" SITE "47" ;
+LOCATE COMP "SA[9]" SITE "49" ;
+LOCATE COMP "SA[8]" SITE "53" ;
+LOCATE COMP "SA[7]" SITE "57" ;
+LOCATE COMP "SA[6]" SITE "62" ;
+LOCATE COMP "SA[5]" SITE "52" ;
+LOCATE COMP "SA[4]" SITE "51" ;
+LOCATE COMP "SA[3]" SITE "60" ;
+LOCATE COMP "SA[2]" SITE "58" ;
+LOCATE COMP "SA[1]" SITE "59" ;
+LOCATE COMP "SA[0]" SITE "54" ;
+LOCATE COMP "SBA[1]" SITE "48" ;
+LOCATE COMP "SBA[0]" SITE "43" ;
+LOCATE COMP "nIOSTRB" SITE "18" ;
+LOCATE COMP "nDEVSEL" SITE "16" ;
+LOCATE COMP "nIOSEL" SITE "15" ;
+LOCATE COMP "nDinOE" SITE "77" ;
+LOCATE COMP "nDoutOE" SITE "1" ;
+LOCATE COMP "RD[7]" SITE "75" ;
+LOCATE COMP "RD[6]" SITE "71" ;
+LOCATE COMP "RD[5]" SITE "70" ;
+LOCATE COMP "RD[4]" SITE "69" ;
+LOCATE COMP "RD[3]" SITE "68" ;
+LOCATE COMP "RD[2]" SITE "67" ;
+LOCATE COMP "RD[1]" SITE "66" ;
+LOCATE COMP "nWE" SITE "19" ;
+LOCATE COMP "RA[15]" SITE "14" ;
+LOCATE COMP "RA[14]" SITE "13" ;
+LOCATE COMP "RA[13]" SITE "10" ;
+LOCATE COMP "RA[12]" SITE "9" ;
+LOCATE COMP "RA[11]" SITE "8" ;
+LOCATE COMP "RA[10]" SITE "3" ;
+LOCATE COMP "RA[9]" SITE "2" ;
+LOCATE COMP "RA[8]" SITE "99" ;
+LOCATE COMP "RA[7]" SITE "87" ;
+LOCATE COMP "RA[6]" SITE "86" ;
+LOCATE COMP "RA[5]" SITE "85" ;
+LOCATE COMP "RA[4]" SITE "4" ;
+LOCATE COMP "RA[3]" SITE "84" ;
+LOCATE COMP "RA[2]" SITE "83" ;
+LOCATE COMP "RA[1]" SITE "78" ;
+LOCATE COMP "RA[0]" SITE "74" ;
+LOCATE COMP "LED" SITE "81" ;
+LOCATE COMP "SetFW[1]" SITE "63" ;
+LOCATE COMP "SetFW[0]" SITE "64" ;
+LOCATE COMP "nIRQout" SITE "12" ;
+LOCATE COMP "nRESout" SITE "7" ;
+LOCATE COMP "nRES" SITE "20" ;
+LOCATE COMP "PHI0" SITE "17" ;
+SCHEMATIC END ;
+[ END DESIGN PREFS ]

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_map.hrr

@@ -0,0 +1,12 @@
+---------------------------------------------------
+Report for cell GR8RAM
+   Instance path: GR8RAM
+                     Cell usage:
+                                  cell	      count    Res Usage(%)
+                                  SLIC	     136.00        100.0
+                                 IOLGC	      50.00        100.0
+                                  LUT4	     242.00        100.0
+                                 IOREG	         50        100.0
+                                 IOBUF	         73        100.0
+                                PFUREG	         68        100.0
+                                RIPPLE	         13        100.0

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_mrp.html

@@ -0,0 +1,427 @@
+<HTML>
+<HEAD><TITLE>Project Summary</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{␍    font-family:'Courier New', monospace;␍    color: #000000;␍    font-size:88%;␍    background-color: #ffffff;␍}␍h1 {␍    font-weight: bold;␍    margin-top: 24px;␍    margin-bottom: 10px;␍    border-bottom: 3px solid #000;    font-size: 1em;␍}␍h2 {␍    font-weight: bold;␍    margin-top: 18px;␍    margin-bottom: 5px;␍    font-size: 0.90em;␍}␍h3 {␍    font-weight: bold;␍    margin-top: 12px;␍    margin-bottom: 5px;␍    font-size: 0.80em;␍}␍p {␍    font-size:78%;␍}␍P.Table {␍    margin-top: 4px;␍    margin-bottom: 4px;␍    margin-right: 4px;␍    margin-left: 4px;␍}␍table␍{␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    border-collapse: collapse;␍}␍th {␍    font-weight:bold;␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    text-align:left;␍    font-size:78%;␍}␍td {␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    font-size:78%;␍}␍a {␍    color:#013C9A;␍    text-decoration:none;␍}␍␍a:visited {␍    color:#013C9A;␍}␍␍a:hover, a:active {␍    text-decoration:underline;␍    color:#5BAFD4;␍}␍.pass␍{␍background-color: #00ff00;␍}␍.fail␍{␍background-color: #ff0000;␍}␍.comment␍{␍    font-size: 90%;␍    font-style: italic;␍}␍
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Mrp"></A>
+            Lattice Mapping Report File for Design Module 'GR8RAM'
+
+
+
+<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     GR8RAM_LCMXO2_1200HC_impl1.ngd -o GR8RAM_LCMXO2_1200HC_impl1_map.ncd -pr
+     GR8RAM_LCMXO2_1200HC_impl1.prf -mp GR8RAM_LCMXO2_1200HC_impl1.mrp -lpf //Ma
+     c/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_s
+     ynplify.lpf -lpf //Mac/iCloud/Repos/GR8RAM/cpld/GR8RAM-LCMXO2.lpf -c 0 -gui
+     -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.11.3.469
+Mapped on:  06/13/24  00:38:52
+
+
+<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
+   Number of registers:    118 out of  1520 (8%)
+      PFU registers:           68 out of  1280 (5%)
+      PIO registers:           50 out of   240 (21%)
+   Number of SLICEs:       136 out of   640 (21%)
+      SLICEs as Logic/ROM:    136 out of   640 (21%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:         13 out of   640 (2%)
+   Number of LUT4s:        268 out of  1280 (21%)
+      Number used as logic LUTs:        242
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       26
+      Number used as shift registers:     0
+   Number of PIO sites used: 73 + 4(JTAG) out of 80 (96%)
+   Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
+      Number of IDDR cells:   0
+      Number of ODDR cells:   1
+      Number of TDDR cells:   0
+   Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
+      Number of PIO using IDDR only:        0 (0 differential)
+      Number of PIO using ODDR only:        1 (0 differential)
+      Number of PIO using TDDR only:        0 (0 differential)
+      Number of PIO using IDDR/ODDR:        0 (0 differential)
+      Number of PIO using IDDR/TDDR:        0 (0 differential)
+      Number of PIO using ODDR/TDDR:        0 (0 differential)
+      Number of PIO using IDDR/ODDR/TDDR:   0 (0 differential)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:        1 out of 1 (100%)
+   EFB used :        No
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  2
+     Net RCLK_c: 80 loads, 72 rising, 8 falling (Driver: PIO RCLK )
+     Net PHI0_c: 14 loads, 14 rising, 0 falling (Driver: PIO PHI0 )
+   Number of Clock Enables:  6
+     Net un1_nRESout4_1_i_0: 2 loads, 2 LSLICEs
+     Net PS[0]: 5 loads, 3 LSLICEs
+     Net SetFWr3: 2 loads, 0 LSLICEs
+     Net N_254_i: 8 loads, 8 LSLICEs
+     Net Bank5: 1 loads, 0 LSLICEs
+     Net RDD37: 8 loads, 1 LSLICEs
+   Number of local set/reset loads for net nRESr merged into GSR:  28
+   Number of LSRs:  1
+     Net FCKout120: 13 loads, 0 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net PS[0]: 33 loads
+     Net SBA14: 31 loads
+     Net N_248: 29 loads
+     Net PS[3]: 28 loads
+     Net PS[2]: 24 loads
+     Net PS[1]: 23 loads
+     Net RAr[1]: 20 loads
+     Net RAMSpecSEL: 19 loads
+     Net FCKout120: 18 loads
+     Net un1_PS_6: 14 loads
+
+
+
+
+   Number of warnings:  1
+   Number of errors:    0
+     
+
+
+
+
+<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
+
+WARNING - map: Using local reset signal 'nRESr' to infer global GSR net.
+
+
+
+<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+| nFCS                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RCLKout             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| MOSI                | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| MISO                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| FCK                 | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SD[7]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SD[6]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SD[5]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[4]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[3]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[2]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[1]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SD[0]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nSWE                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[12]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[11]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[10]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[9]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[8]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[7]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[6]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+
+| SA[5]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[4]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[3]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[2]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[1]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SA[0]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SBA[1]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| SBA[0]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nIOSTRB             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nDEVSEL             | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nIOSEL              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nDinOE              | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nDoutOE             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nWE                 | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[15]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[14]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[13]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[12]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[10]              | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[9]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+| RA[8]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[7]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[6]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[5]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[4]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[3]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[2]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[1]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| RA[0]               | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| SetFW[1]            | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| SetFW[0]            | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| nIRQout             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nRESout             | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nRES                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+| PHI0                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+
+
+<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
+
+Signal SDOE_i was merged into signal SDOE
+Signal MOSIOE_i was merged into signal MOSIOE
+Signal FCKOE_i was merged into signal FCKOE
+Signal nRESr_i was merged into signal nRESr
+Signal PS_i[0] was merged into signal PS[0]
+Signal RDD_0_.CN was merged into signal RCLK_c
+Signal LS_s_0_S1[13] undriven or does not drive anything - clipped.
+Signal LS_s_0_COUT[13] undriven or does not drive anything - clipped.
+Signal un1_Addr_1_cry_0_0_S0 undriven or does not drive anything - clipped.
+Signal N_2 undriven or does not drive anything - clipped.
+Signal un1_Addr_1_s_7_0_S1 undriven or does not drive anything - clipped.
+Signal un1_Addr_1_s_7_0_COUT undriven or does not drive anything - clipped.
+Signal LS_cry_0_S0[0] undriven or does not drive anything - clipped.
+Signal N_1 undriven or does not drive anything - clipped.
+Block SDOE_RNIBPBD was optimized away.
+Block MOSI_pad_RNO was optimized away.
+Block FCKOE_RNI8HE1 was optimized away.
+Block nRESr_RNIAPB9 was optimized away.
+Block PS_RNIBBDD[0] was optimized away.
+Block RDD_0_.CN was optimized away.
+
+
+     
+
+
+
+<A name="mrp_gsr"></A><B><U><big>GSR Usage</big></U></B>
+---------
+
+GSR Component:
+   The local reset signal 'nRESr' of the design has been inferred as Global Set
+        Reset (GSR). The reset signal used for GSR control is 'nRESr'.
+        
+
+     GSR Property:
+   The design components with GSR property set to ENABLED will respond to global
+        set reset while the components with GSR property set to DISABLED will
+        not.
+        
+
+
+
+<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 64 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_ngd.asd

@@ -0,0 +1 @@
+[ActiveSupport NGD]

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_pad.html

@@ -0,0 +1,386 @@
+<HTML>
+<HEAD><TITLE>PAD Specification File</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{␍    font-family:'Courier New', monospace;␍    color: #000000;␍    font-size:88%;␍    background-color: #ffffff;␍}␍h1 {␍    font-weight: bold;␍    margin-top: 24px;␍    margin-bottom: 10px;␍    border-bottom: 3px solid #000;    font-size: 1em;␍}␍h2 {␍    font-weight: bold;␍    margin-top: 18px;␍    margin-bottom: 5px;␍    font-size: 0.90em;␍}␍h3 {␍    font-weight: bold;␍    margin-top: 12px;␍    margin-bottom: 5px;␍    font-size: 0.80em;␍}␍p {␍    font-size:78%;␍}␍P.Table {␍    margin-top: 4px;␍    margin-bottom: 4px;␍    margin-right: 4px;␍    margin-left: 4px;␍}␍table␍{␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    border-collapse: collapse;␍}␍th {␍    font-weight:bold;␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    text-align:left;␍    font-size:78%;␍}␍td {␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    font-size:78%;␍}␍a {␍    color:#013C9A;␍    text-decoration:none;␍}␍␍a:visited {␍    color:#013C9A;␍}␍␍a:hover, a:active {␍    text-decoration:underline;␍    color:#5BAFD4;␍}␍.pass␍{␍background-color: #00ff00;␍}␍.fail␍{␍background-color: #ff0000;␍}␍.comment␍{␍    font-size: 90%;␍    font-style: italic;␍}␍
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Pad"></A>PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.42
+
+Thu Jun 13 00:38:57 2024
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| DQMH      | 34/2     | LVCMOS33_OUT  | PB9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| DQML      | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| FCK       | 96/0     | LVCMOS33_OUT  | PT10B |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
+| LED       | 81/0     | LVCMOS33_OUT  | PT15D |           |           | DRIVE:24mA SLEW:SLOW                                       |
+| MISO      | 98/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| MOSI      | 97/0     | LVCMOS33_BIDI | PT10A |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| PHI0      | 17/3     | LVCMOS33_IN   | PL8B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 74/1     | LVCMOS33_IN   | PR2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[10]    | 3/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[11]    | 8/3      | LVCMOS33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[12]    | 9/3      | LVCMOS33_IN   | PL4A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[13]    | 10/3     | LVCMOS33_IN   | PL4B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[14]    | 13/3     | LVCMOS33_IN   | PL5B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[15]    | 14/3     | LVCMOS33_IN   | PL5C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[1]     | 78/0     | LVCMOS33_IN   | PT16C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[2]     | 83/0     | LVCMOS33_IN   | PT15B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[3]     | 84/0     | LVCMOS33_IN   | PT15A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[4]     | 4/3      | LVCMOS33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[5]     | 85/0     | LVCMOS33_IN   | PT12D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[6]     | 86/0     | LVCMOS33_IN   | PT12C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[7]     | 87/0     | LVCMOS33_IN   | PT12B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[8]     | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[9]     | 2/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RCKE      | 40/2     | LVCMOS33_OUT  | PB15A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RCLK      | 38/2     | LVCMOS33_IN   | PB11A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RCLKout   | 39/2     | LVCMOS33_OUT  | PB11B |           |           | DRIVE:24mA SLEW:FAST                                       |
+| RD[0]     | 65/1     | LVCMOS33_BIDI | PR5A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 66/1     | LVCMOS33_BIDI | PR4D  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 67/1     | LVCMOS33_BIDI | PR4C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 68/1     | LVCMOS33_BIDI | PR4B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 69/1     | LVCMOS33_BIDI | PR4A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 70/1     | LVCMOS33_BIDI | PR3B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 71/1     | LVCMOS33_BIDI | PR3A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 75/1     | LVCMOS33_BIDI | PR2A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SA[0]     | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[10]    | 47/2     | LVCMOS33_OUT  | PB18D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[11]    | 45/2     | LVCMOS33_OUT  | PB18C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[12]    | 42/2     | LVCMOS33_OUT  | PB18A |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[1]     | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[2]     | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[3]     | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[4]     | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[5]     | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[6]     | 62/1     | LVCMOS33_OUT  | PR5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[7]     | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[8]     | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SA[9]     | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SBA[0]    | 43/2     | LVCMOS33_OUT  | PB18B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SBA[1]    | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| SD[0]     | 25/3     | LVCMOS33_BIDI | PL10D |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[1]     | 24/3     | LVCMOS33_BIDI | PL10C |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[2]     | 21/3     | LVCMOS33_BIDI | PL9B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[3]     | 27/2     | LVCMOS33_BIDI | PB4C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[4]     | 28/2     | LVCMOS33_BIDI | PB4D  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[5]     | 29/2     | LVCMOS33_BIDI | PB6A  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[6]     | 30/2     | LVCMOS33_BIDI | PB6B  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SD[7]     | 31/2     | LVCMOS33_BIDI | PB6C  |           |           | DRIVE:8mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| SetFW[0]  | 64/1     | LVCMOS33_IN   | PR5B  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
+| SetFW[1]  | 63/1     | LVCMOS33_IN   | PR5C  |           |           | PULL:UP CLAMP:ON HYSTERESIS:SMALL                          |
+| nCAS      | 36/2     | LVCMOS33_OUT  | PB11C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDEVSEL   | 16/3     | LVCMOS33_IN   | PL8A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nDinOE    | 77/0     | LVCMOS33_OUT  | PT17C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDoutOE   | 1/3      | LVCMOS33_OUT  | PL2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nFCS      | 88/0     | LVCMOS33_OUT  | PT12A |           |           | DRIVE:4mA PULL:KEEPER SLEW:SLOW                            |
+| nIOSEL    | 15/3     | LVCMOS33_IN   | PL5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nIOSTRB   | 18/3     | LVCMOS33_IN   | PL8C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nIRQout   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRAS      | 37/2     | LVCMOS33_OUT  | PB11D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRCS      | 41/2     | LVCMOS33_OUT  | PB15B |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRES      | 20/3     | LVCMOS33_IN   | PL9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRESout   | 7/3      | LVCMOS33_OUT  | PL3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nSWE      | 35/2     | LVCMOS33_OUT  | PB9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nWE       | 19/3     | LVCMOS33_IN   | PL8D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | nDoutOE               | LOCATED    | LVCMOS33_OUT  | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      | RA[9]                 | LOCATED    | LVCMOS33_IN   | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      | RA[10]                | LOCATED    | LVCMOS33_IN   | PL3A  | PCLKT3_2      |           |           |
+| 4/3      | RA[4]                 | LOCATED    | LVCMOS33_IN   | PL3B  | PCLKC3_2      |           |           |
+| 7/3      | nRESout               | LOCATED    | LVCMOS33_OUT  | PL3C  |               |           |           |
+| 8/3      | RA[11]                | LOCATED    | LVCMOS33_IN   | PL3D  |               |           |           |
+| 9/3      | RA[12]                | LOCATED    | LVCMOS33_IN   | PL4A  |               |           |           |
+| 10/3     | RA[13]                | LOCATED    | LVCMOS33_IN   | PL4B  |               |           |           |
+| 12/3     | nIRQout               | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | RA[14]                | LOCATED    | LVCMOS33_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | RA[15]                | LOCATED    | LVCMOS33_IN   | PL5C  |               |           |           |
+| 15/3     | nIOSEL                | LOCATED    | LVCMOS33_IN   | PL5D  |               |           |           |
+| 16/3     | nDEVSEL               | LOCATED    | LVCMOS33_IN   | PL8A  |               |           |           |
+| 17/3     | PHI0                  | LOCATED    | LVCMOS33_IN   | PL8B  |               |           |           |
+| 18/3     | nIOSTRB               | LOCATED    | LVCMOS33_IN   | PL8C  |               |           |           |
+| 19/3     | nWE                   | LOCATED    | LVCMOS33_IN   | PL8D  |               |           |           |
+| 20/3     | nRES                  | LOCATED    | LVCMOS33_IN   | PL9A  | PCLKT3_0      |           |           |
+| 21/3     | SD[2]                 | LOCATED    | LVCMOS33_BIDI | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | SD[1]                 | LOCATED    | LVCMOS33_BIDI | PL10C |               |           |           |
+| 25/3     | SD[0]                 | LOCATED    | LVCMOS33_BIDI | PL10D |               |           |           |
+| 27/2     | SD[3]                 | LOCATED    | LVCMOS33_BIDI | PB4C  | CSSPIN        |           |           |
+| 28/2     | SD[4]                 | LOCATED    | LVCMOS33_BIDI | PB4D  |               |           |           |
+| 29/2     | SD[5]                 | LOCATED    | LVCMOS33_BIDI | PB6A  |               |           |           |
+| 30/2     | SD[6]                 | LOCATED    | LVCMOS33_BIDI | PB6B  |               |           |           |
+| 31/2     | SD[7]                 | LOCATED    | LVCMOS33_BIDI | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB6D  | SO/SPISO      |           |           |
+| 34/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB9A  | PCLKT2_0      |           |           |
+| 35/2     | nSWE                  | LOCATED    | LVCMOS33_OUT  | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PB11C |               |           |           |
+| 37/2     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PB11D |               |           |           |
+| 38/2     | RCLK                  | LOCATED    | LVCMOS33_IN   | PB11A | PCLKT2_1      |           |           |
+| 39/2     | RCLKout               | LOCATED    | LVCMOS33_OUT  | PB11B | PCLKC2_1      |           |           |
+| 40/2     | RCKE                  | LOCATED    | LVCMOS33_OUT  | PB15A |               |           |           |
+| 41/2     | nRCS                  | LOCATED    | LVCMOS33_OUT  | PB15B |               |           |           |
+| 42/2     | SA[12]                | LOCATED    | LVCMOS33_OUT  | PB18A |               |           |           |
+| 43/2     | SBA[0]                | LOCATED    | LVCMOS33_OUT  | PB18B |               |           |           |
+| 45/2     | SA[11]                | LOCATED    | LVCMOS33_OUT  | PB18C |               |           |           |
+| 47/2     | SA[10]                | LOCATED    | LVCMOS33_OUT  | PB18D |               |           |           |
+| 48/2     | SBA[1]                | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
+| 49/2     | SA[9]                 | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | SA[4]                 | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | SA[5]                 | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | SA[8]                 | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | SA[0]                 | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | SA[7]                 | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
+| 58/1     | SA[2]                 | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
+| 59/1     | SA[1]                 | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
+| 60/1     | SA[3]                 | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
+| 62/1     | SA[6]                 | LOCATED    | LVCMOS33_OUT  | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | SetFW[1]              | LOCATED    | LVCMOS33_IN   | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | SetFW[0]              | LOCATED    | LVCMOS33_IN   | PR5B  | DQS0N         |           |           |
+| 65/1     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PR5A  | DQS0          |           |           |
+| 66/1     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PR4D  | DQ0           |           |           |
+| 67/1     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PR4C  | DQ0           |           |           |
+| 68/1     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PR4B  | DQ0           |           |           |
+| 69/1     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PR4A  | DQ0           |           |           |
+| 70/1     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PR3B  | DQ0           |           |           |
+| 71/1     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PR3A  | DQ0           |           |           |
+| 74/1     | RA[0]                 | LOCATED    | LVCMOS33_IN   | PR2B  | DQ0           |           |           |
+| 75/1     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
+| 77/0     | nDinOE                | LOCATED    | LVCMOS33_OUT  | PT17C | INITN         |           |           |
+| 78/0     | RA[1]                 | LOCATED    | LVCMOS33_IN   | PT16C |               |           |           |
+| 81/0     | LED                   | LOCATED    | LVCMOS33_OUT  | PT15D | PROGRAMN      |           |           |
+| 82/0     |     unused, PULL:DOWN |            |               | PT15C | JTAGENB       |           |           |
+| 83/0     | RA[2]                 | LOCATED    | LVCMOS33_IN   | PT15B |               |           |           |
+| 84/0     | RA[3]                 | LOCATED    | LVCMOS33_IN   | PT15A |               |           |           |
+| 85/0     | RA[5]                 | LOCATED    | LVCMOS33_IN   | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | RA[6]                 | LOCATED    | LVCMOS33_IN   | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | RA[7]                 | LOCATED    | LVCMOS33_IN   | PT12B | PCLKC0_1      |           |           |
+| 88/0     | nFCS                  | LOCATED    | LVCMOS33_OUT  | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | FCK                   | LOCATED    | LVCMOS33_OUT  | PT10B |               |           |           |
+| 97/0     | MOSI                  | LOCATED    | LVCMOS33_BIDI | PT10A |               |           |           |
+| 98/0     | MISO                  | LOCATED    | LVCMOS33_IN   | PT9B  |               |           |           |
+| 99/0     | RA[8]                 | LOCATED    | LVCMOS33_IN   | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "DQMH"  SITE  "34";
+LOCATE  COMP  "DQML"  SITE  "32";
+LOCATE  COMP  "FCK"  SITE  "96";
+LOCATE  COMP  "LED"  SITE  "81";
+LOCATE  COMP  "MISO"  SITE  "98";
+LOCATE  COMP  "MOSI"  SITE  "97";
+LOCATE  COMP  "PHI0"  SITE  "17";
+LOCATE  COMP  "RA[0]"  SITE  "74";
+LOCATE  COMP  "RA[10]"  SITE  "3";
+LOCATE  COMP  "RA[11]"  SITE  "8";
+LOCATE  COMP  "RA[12]"  SITE  "9";
+LOCATE  COMP  "RA[13]"  SITE  "10";
+LOCATE  COMP  "RA[14]"  SITE  "13";
+LOCATE  COMP  "RA[15]"  SITE  "14";
+LOCATE  COMP  "RA[1]"  SITE  "78";
+LOCATE  COMP  "RA[2]"  SITE  "83";
+LOCATE  COMP  "RA[3]"  SITE  "84";
+LOCATE  COMP  "RA[4]"  SITE  "4";
+LOCATE  COMP  "RA[5]"  SITE  "85";
+LOCATE  COMP  "RA[6]"  SITE  "86";
+LOCATE  COMP  "RA[7]"  SITE  "87";
+LOCATE  COMP  "RA[8]"  SITE  "99";
+LOCATE  COMP  "RA[9]"  SITE  "2";
+LOCATE  COMP  "RCKE"  SITE  "40";
+LOCATE  COMP  "RCLK"  SITE  "38";
+LOCATE  COMP  "RCLKout"  SITE  "39";
+LOCATE  COMP  "RD[0]"  SITE  "65";
+LOCATE  COMP  "RD[1]"  SITE  "66";
+LOCATE  COMP  "RD[2]"  SITE  "67";
+LOCATE  COMP  "RD[3]"  SITE  "68";
+LOCATE  COMP  "RD[4]"  SITE  "69";
+LOCATE  COMP  "RD[5]"  SITE  "70";
+LOCATE  COMP  "RD[6]"  SITE  "71";
+LOCATE  COMP  "RD[7]"  SITE  "75";
+LOCATE  COMP  "SA[0]"  SITE  "54";
+LOCATE  COMP  "SA[10]"  SITE  "47";
+LOCATE  COMP  "SA[11]"  SITE  "45";
+LOCATE  COMP  "SA[12]"  SITE  "42";
+LOCATE  COMP  "SA[1]"  SITE  "59";
+LOCATE  COMP  "SA[2]"  SITE  "58";
+LOCATE  COMP  "SA[3]"  SITE  "60";
+LOCATE  COMP  "SA[4]"  SITE  "51";
+LOCATE  COMP  "SA[5]"  SITE  "52";
+LOCATE  COMP  "SA[6]"  SITE  "62";
+LOCATE  COMP  "SA[7]"  SITE  "57";
+LOCATE  COMP  "SA[8]"  SITE  "53";
+LOCATE  COMP  "SA[9]"  SITE  "49";
+LOCATE  COMP  "SBA[0]"  SITE  "43";
+LOCATE  COMP  "SBA[1]"  SITE  "48";
+LOCATE  COMP  "SD[0]"  SITE  "25";
+LOCATE  COMP  "SD[1]"  SITE  "24";
+LOCATE  COMP  "SD[2]"  SITE  "21";
+LOCATE  COMP  "SD[3]"  SITE  "27";
+LOCATE  COMP  "SD[4]"  SITE  "28";
+LOCATE  COMP  "SD[5]"  SITE  "29";
+LOCATE  COMP  "SD[6]"  SITE  "30";
+LOCATE  COMP  "SD[7]"  SITE  "31";
+LOCATE  COMP  "SetFW[0]"  SITE  "64";
+LOCATE  COMP  "SetFW[1]"  SITE  "63";
+LOCATE  COMP  "nCAS"  SITE  "36";
+LOCATE  COMP  "nDEVSEL"  SITE  "16";
+LOCATE  COMP  "nDinOE"  SITE  "77";
+LOCATE  COMP  "nDoutOE"  SITE  "1";
+LOCATE  COMP  "nFCS"  SITE  "88";
+LOCATE  COMP  "nIOSEL"  SITE  "15";
+LOCATE  COMP  "nIOSTRB"  SITE  "18";
+LOCATE  COMP  "nIRQout"  SITE  "12";
+LOCATE  COMP  "nRAS"  SITE  "37";
+LOCATE  COMP  "nRCS"  SITE  "41";
+LOCATE  COMP  "nRES"  SITE  "20";
+LOCATE  COMP  "nRESout"  SITE  "7";
+LOCATE  COMP  "nSWE"  SITE  "35";
+LOCATE  COMP  "nWE"  SITE  "19";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:39:01 2024
+
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_par.html

@@ -0,0 +1,301 @@
+<HTML>
+<HEAD><TITLE>Place & Route Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{␍    font-family:'Courier New', monospace;␍    color: #000000;␍    font-size:88%;␍    background-color: #ffffff;␍}␍h1 {␍    font-weight: bold;␍    margin-top: 24px;␍    margin-bottom: 10px;␍    border-bottom: 3px solid #000;    font-size: 1em;␍}␍h2 {␍    font-weight: bold;␍    margin-top: 18px;␍    margin-bottom: 5px;␍    font-size: 0.90em;␍}␍h3 {␍    font-weight: bold;␍    margin-top: 12px;␍    margin-bottom: 5px;␍    font-size: 0.80em;␍}␍p {␍    font-size:78%;␍}␍P.Table {␍    margin-top: 4px;␍    margin-bottom: 4px;␍    margin-right: 4px;␍    margin-left: 4px;␍}␍table␍{␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    border-collapse: collapse;␍}␍th {␍    font-weight:bold;␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    text-align:left;␍    font-size:78%;␍}␍td {␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    font-size:78%;␍}␍a {␍    color:#013C9A;␍    text-decoration:none;␍}␍␍a:visited {␍    color:#013C9A;␍}␍␍a:hover, a:active {␍    text-decoration:underline;␍    color:#5BAFD4;␍}␍.pass␍{␍background-color: #00ff00;␍}␍.fail␍{␍background-color: #ff0000;␍}␍.comment␍{␍    font-size: 90%;␍    font-style: italic;␍}␍
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Jun 13 00:38:53 2024
+
+C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f GR8RAM_LCMXO2_1200HC_impl1.p2t
+GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir
+GR8RAM_LCMXO2_1200HC_impl1.prf -gui -msgset
+//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml
+
+
+Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
+
+<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -            -            -            -            10           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 10 secs 
+
+par done!
+
+Note: user must run &apos;Trace&apos; for timing closure signoff.
+
+Lattice Place and Route Report for Design &quot;GR8RAM_LCMXO2_1200HC_impl1_map.ncd&quot;
+Thu Jun 13 00:38:53 2024
+
+
+<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
+PAR: Place And Route Diamond (64-bit) 3.11.3.469.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF GR8RAM_LCMXO2_1200HC_impl1_map.ncd GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd GR8RAM_LCMXO2_1200HC_impl1.prf
+Preference file: GR8RAM_LCMXO2_1200HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file GR8RAM_LCMXO2_1200HC_impl1_map.ncd.
+Design name: GR8RAM
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file &apos;xo2c1200.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
+Package Status:                     Final          Version 1.42.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
+
+   PIO (prelim)   73+4(JTAG)/108     71% used
+                  73+4(JTAG)/80      96% bonded
+   IOLOGIC           51/108          47% used
+
+   SLICE            136/640          21% used
+
+   GSR                1/1           100% used
+
+
+Number of Signals: 430
+Number of Connections: 1211
+
+Pin Constraint Summary:
+   73 out of 73 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 80)
+    PHI0_c (driver: PHI0, clk load #: 14)
+
+WARNING - par: Signal &quot;PHI0_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;PHI0&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    FCKout120 (driver: SLICE_54, clk load #: 0, sr load #: 13, ce load #: 0)
+
+Signal nRESr is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+....................
+Placer score = 87858.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  86903
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+
+<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 8 (12%)
+  General PIO: 1 out of 108 (0%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on CLK_PIN site &quot;38 (PB11A)&quot;, clk load = 80
+  PRIMARY &quot;PHI0_c&quot; from comp &quot;PHI0&quot; on PIO site &quot;17 (PL8B)&quot;, clk load = 14
+  SECONDARY &quot;FCKout120&quot; from F0 on comp &quot;SLICE_54&quot; on site &quot;R7C12B&quot;, clk load = 0, ce load = 0, sr load = 13
+
+  PRIMARY  : 2 out of 8 (25%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+
+
+
+I/O Usage Summary (final):
+   73 + 4(JTAG) out of 108 (71.3%) PIO sites used.
+   73 + 4(JTAG) out of 80 (96.3%) bonded PIO sites used.
+   Number of PIO comps: 73; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 3.3V       | -         |
+| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
+| 2        | 20 / 20 (100%) | 3.3V       | -         |
+| 3        | 20 / 20 (100%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 3 secs 
+
+Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+-----------------------------------------------------------------
+INFO - par: ASE feature is off due to non timing-driven settings.  
+-----------------------------------------------------------------
+
+0 connections routed; 1211 unrouted.
+Starting router resource preassignment
+
+Completed router resource preassignment. Real time: 9 secs 
+
+Start NBR router at 00:39:02 06/13/24
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 00:39:02 06/13/24
+
+Start NBR section for initial routing at 00:39:02 06/13/24
+Level 4, iteration 1
+19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 00:39:02 06/13/24
+Level 4, iteration 1
+4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+Level 4, iteration 2
+1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+Level 4, iteration 3
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Start NBR section for re-routing at 00:39:02 06/13/24
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 9 secs 
+
+Start NBR section for post-routing at 00:39:02 06/13/24
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack&lt;setup&gt; : &lt;n/a&gt;
+  Timing score&lt;setup&gt; : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 8 secs 
+Total REAL time: 9 secs 
+Completely routed.
+End of route.  1211 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file GR8RAM_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
+PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
+PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
+PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 9 secs 
+Total REAL time to completion: 10 secs 
+
+par done!
+
+Note: user must run &apos;Trace&apos; for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_scck.rpt

@@ -0,0 +1,51 @@
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+
+# Written on Thu Jun 13 00:38:47 2024
+
+##### FILES SYNTAX CHECKED ##############################################
+Constraint File(s):      (none)
+
+#Run constraint checker to find more issues with constraints.
+#########################################################################
+
+
+
+No issues found in constraint syntax.
+
+
+
+Clock Summary
+*************
+
+          Start           Requested     Requested     Clock        Clock                   Clock
+Level     Clock           Frequency     Period        Type         Group                   Load 
+------------------------------------------------------------------------------------------------
+0 -       GR8RAM|RCLK     100.0 MHz     10.000        inferred     Inferred_clkgroup_1     104  
+                                                                                                
+0 -       GR8RAM|PHI0     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     18   
+================================================================================================
+
+
+Clock Load Summary
+******************
+
+                Clock     Source         Clock Pin        Non-clock Pin       Non-clock Pin     
+Clock           Load      Pin            Seq Example      Seq Example         Comb Example      
+------------------------------------------------------------------------------------------------
+GR8RAM|RCLK     104       RCLK(port)     PHI0r[4:1].C     -                   un1_RCLK.I[0](inv)
+                                                                                                
+GR8RAM|PHI0     18        PHI0(port)     RAr[11:0].C      PHI0r[4:1].D[0]     nDoutOE.I[0](inv) 
+================================================================================================

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_summary.html

@@ -0,0 +1,83 @@
+<HTML>
+<HEAD><TITLE>Project Summary</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{␍    font-family:'Courier New', monospace;␍    color: #000000;␍    font-size:88%;␍    background-color: #ffffff;␍}␍h1 {␍    font-weight: bold;␍    margin-top: 24px;␍    margin-bottom: 10px;␍    border-bottom: 3px solid #000;    font-size: 1em;␍}␍h2 {␍    font-weight: bold;␍    margin-top: 18px;␍    margin-bottom: 5px;␍    font-size: 0.90em;␍}␍h3 {␍    font-weight: bold;␍    margin-top: 12px;␍    margin-bottom: 5px;␍    font-size: 0.80em;␍}␍p {␍    font-size:78%;␍}␍P.Table {␍    margin-top: 4px;␍    margin-bottom: 4px;␍    margin-right: 4px;␍    margin-left: 4px;␍}␍table␍{␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    border-collapse: collapse;␍}␍th {␍    font-weight:bold;␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    text-align:left;␍    font-size:78%;␍}␍td {␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    font-size:78%;␍}␍a {␍    color:#013C9A;␍    text-decoration:none;␍}␍␍a:visited {␍    color:#013C9A;␍}␍␍a:hover, a:active {␍    text-decoration:underline;␍    color:#5BAFD4;␍}␍.pass␍{␍background-color: #00ff00;␍}␍.fail␍{␍background-color: #ff0000;␍}␍.comment␍{␍    font-size: 90%;␍    font-style: italic;␍}␍
+-->
+</STYLE>
+</HEAD>
+<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
+<TR>
+<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>GR8RAM_LCMXO2_1200HC project summary</B></SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">GR8RAM_LCMXO2_1200HC</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">GR8RAM-LCMXO2.lpf</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/GR8RAM_LCMXO2_1200HC_impl1.prf</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.3.469</SPAN></TD>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/13 00:39:07</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/impl1</SPAN></TD>
+</TR>
+<TR>
+<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
+<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/GR8RAM/cpld/LCMXO2-1200HC/GR8RAM_LCMXO2_1200HC.ldf</SPAN></TD>
+</TR>
+</small></TABLE>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>

cpld/LCMXO2-1200HC/impl1/GR8RAM_LCMXO2_1200HC_impl1_synplify.html

@@ -0,0 +1,626 @@
+<HTML>
+<HEAD><TITLE>Synthesis Report</TITLE>
+<STYLE TYPE="text/css">
+<!--
+ body,pre{␍    font-family:'Courier New', monospace;␍    color: #000000;␍    font-size:88%;␍    background-color: #ffffff;␍}␍h1 {␍    font-weight: bold;␍    margin-top: 24px;␍    margin-bottom: 10px;␍    border-bottom: 3px solid #000;    font-size: 1em;␍}␍h2 {␍    font-weight: bold;␍    margin-top: 18px;␍    margin-bottom: 5px;␍    font-size: 0.90em;␍}␍h3 {␍    font-weight: bold;␍    margin-top: 12px;␍    margin-bottom: 5px;␍    font-size: 0.80em;␍}␍p {␍    font-size:78%;␍}␍P.Table {␍    margin-top: 4px;␍    margin-bottom: 4px;␍    margin-right: 4px;␍    margin-left: 4px;␍}␍table␍{␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    border-collapse: collapse;␍}␍th {␍    font-weight:bold;␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    text-align:left;␍    font-size:78%;␍}␍td {␍    padding: 4px;␍    border-width: 1px 1px 1px 1px;␍    border-style: solid solid solid solid;␍    border-color: black black black black;␍    vertical-align:top;␍    font-size:78%;␍}␍a {␍    color:#013C9A;␍    text-decoration:none;␍}␍␍a:visited {␍    color:#013C9A;␍}␍␍a:hover, a:active {␍    text-decoration:underline;␍    color:#5BAFD4;␍}␍.pass␍{␍background-color: #00ff00;␍}␍.fail␍{␍background-color: #ff0000;␍}␍.comment␍{␍    font-size: 90%;␍    font-style: italic;␍}␍
+-->
+</STYLE>
+</HEAD>
+<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
+#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr  1 2019
+#install: C:\lscc\diamond\3.11_x64\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Thu Jun 13 00:38:45 2024
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v" (library work)
+Verilog syntax check successful!
+File \\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v changed - recompiling
+Selecting top level module GR8RAM
+@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
+Running optimization stage 1 on ODDRXE .......
+@N: CG364 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":1:7:1:12|Synthesizing module GR8RAM in library work.
+Running optimization stage 1 on GR8RAM .......
+Running optimization stage 2 on GR8RAM .......
+@N: CL201 :"\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":49:1:49:6|Trying to extract state machine for register IS.
+Running optimization stage 2 on ODDRXE .......
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:46 2024
+
+###########################################################]
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Database state : \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\|impl1
+Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:17:43
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Jun 13 00:38:47 2024
+
+###########################################################]
+# Thu Jun 13 00:38:47 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
+
+@A: MF827 |No constraint file specified.
+@N: MF284 |Setting synthesis effort to medium for the design
+@L: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt 
+Printing clock  summary report in "\\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1_scck.rpt" file 
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@A: FX681 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":36:1:36:6|Initial value on register PS[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: MH105 |UMR3 is only supported for HAPS-80.
+@N: MH105 |UMR3 is only supported for HAPS-80.
+syn_allowed_resources : blockrams=7  set on top level netlist GR8RAM
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start           Requested     Requested     Clock        Clock                   Clock
+Level     Clock           Frequency     Period        Type         Group                   Load 
+------------------------------------------------------------------------------------------------
+0 -       GR8RAM|RCLK     100.0 MHz     10.000        inferred     Inferred_clkgroup_1     104  
+                                                                                                
+0 -       GR8RAM|PHI0     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     18   
+================================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+                Clock     Source         Clock Pin        Non-clock Pin       Non-clock Pin     
+Clock           Load      Pin            Seq Example      Seq Example         Comb Example      
+------------------------------------------------------------------------------------------------
+GR8RAM|RCLK     104       RCLK(port)     PHI0r[4:1].C     -                   un1_RCLK.I[0](inv)
+                                                                                                
+GR8RAM|PHI0     18        PHI0(port)     RAr[11:0].C      PHI0r[4:1].D[0]     nDoutOE.I[0](inv) 
+================================================================================================
+
+@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":67:1:67:6|Found inferred clock GR8RAM|PHI0 which controls 18 sequential elements including CXXXr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":20:16:20:21|Found inferred clock GR8RAM|RCLK which controls 104 sequential elements including nRESf. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+2 non-gated/non-generated clock tree(s) driving 118 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       RCLK                Unconstrained_port     104        nRESf          
+@KP:ckid0_1       PHI0                Unconstrained_port     14         CXXXr          
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Jun 13 00:38:48 2024
+
+###########################################################]
+# Thu Jun 13 00:38:48 2024
+
+
+Copyright (C) 1994-2018 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: N-2018.03L-SP1-1
+Install: C:\lscc\diamond\3.11_x64\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:51:54
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
+
+@N: MF284 |Setting synthesis effort to medium for the design
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nRAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nRAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
+@W: FA239 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|ROM nCAS_2 (in view: work.GR8RAM(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":348:2:348:5|Found ROM nCAS_2 (in view: work.GR8RAM(verilog)) with 12 words by 1 bit.
+@N: FX493 |Applying initial value "000" on instance IS[2:0].
+@N: FX493 |Applying initial value "0000" on instance PS[3:0].
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
+
+@N: MO231 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":44:1:44:6|Found counter in view:work.GR8RAM(verilog) instance LS[13:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:01s		     1.70ns		 247 /       118
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 166MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 166MB)
+
+Writing Analyst data base \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\synwork\GR8RAM_LCMXO2_1200HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 167MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\GR8RAM\cpld\LCMXO2-1200HC\impl1\GR8RAM_LCMXO2_1200HC_impl1.edi
+N-2018.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+@W: MT246 :"\\mac\icloud\repos\gr8ram\cpld\gr8ram.v":10:11:10:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@W: MT420 |Found inferred clock GR8RAM|PHI0 with period 10.00ns. Please declare a user-defined clock on port PHI0.
+@W: MT420 |Found inferred clock GR8RAM|RCLK with period 10.00ns. Please declare a user-defined clock on port RCLK.
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Thu Jun 13 00:38:51 2024
+#
+
+
+Top view:               GR8RAM
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 1.955
+
+                   Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group              
+---------------------------------------------------------------------------------------------------------------------
+GR8RAM|PHI0        100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_0
+GR8RAM|RCLK        100.0 MHz     134.3 MHz     10.000        7.448         1.955     inferred     Inferred_clkgroup_1
+System             100.0 MHz     NA            10.000        NA            NA        system       system_clkgroup    
+=====================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+----------------------------------------------------------------------------------------------------------------
+Starting     Ending       |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+----------------------------------------------------------------------------------------------------------------
+GR8RAM|PHI0  GR8RAM|RCLK  |  Diff grp    -      |  No paths    -      |  Diff grp    -      |  No paths    -    
+GR8RAM|RCLK  GR8RAM|RCLK  |  10.000      2.552  |  No paths    -      |  5.000       1.955  |  No paths    -    
+================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: GR8RAM|RCLK
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                  Starting                                           Arrival          
+Instance          Reference       Type         Pin     Net           Time        Slack
+                  Clock                                                               
+--------------------------------------------------------------------------------------
+PS[3]             GR8RAM|RCLK     FD1S3AX      Q       PS[3]         1.309       1.955
+PS[0]             GR8RAM|RCLK     FD1S3AX      Q       PS[0]         1.305       1.958
+PS[2]             GR8RAM|RCLK     FD1S3AX      Q       PS[2]         1.296       1.968
+PS[1]             GR8RAM|RCLK     FD1S3AX      Q       PS[1]         1.288       1.976
+Addr[1]           GR8RAM|RCLK     FD1S3DX      Q       Addr[1]       1.232       2.009
+SetFWr_0io[1]     GR8RAM|RCLK     IFS1P3DX     Q       SetFWr[1]     1.232       2.009
+Addr[2]           GR8RAM|RCLK     FD1S3DX      Q       Addr[2]       1.228       2.013
+Addr[3]           GR8RAM|RCLK     FD1S3DX      Q       Addr[3]       1.220       2.021
+Addr[10]          GR8RAM|RCLK     FD1S3DX      Q       Addr[10]      1.220       2.021
+Addr[4]           GR8RAM|RCLK     FD1S3DX      Q       Addr[4]       1.204       2.037
+======================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                          Required          
+Instance       Reference       Type         Pin     Net          Time         Slack
+               Clock                                                               
+-----------------------------------------------------------------------------------
+RDD[0]         GR8RAM|RCLK     FD1P3AX      SP      RDD37        4.528        1.955
+RDD_0io[1]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[2]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[3]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[4]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[5]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[6]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[7]     GR8RAM|RCLK     OFS1P3DX     SP      RDD37        4.528        1.955
+RDD_0io[1]     GR8RAM|RCLK     OFS1P3DX     D       RDD_8[1]     5.089        2.009
+RDD_0io[4]     GR8RAM|RCLK     OFS1P3DX     D       RDD_8[4]     5.089        2.009
+===================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      5.000
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         4.528
+
+    - Propagation time:                      2.573
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     1.955
+
+    Number of logic level(s):                1
+    Starting point:                          PS[3] / Q
+    Ending point:                            RDD[0] / SP
+    The start point is clocked by            GR8RAM|RCLK [rising] on pin CK
+    The end   point is clocked by            GR8RAM|RCLK [falling] on pin CK
+
+Instance / Net                  Pin      Pin               Arrival     No. of    
+Name               Type         Name     Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PS[3]              FD1S3AX      Q        Out     1.309     1.309       -         
+PS[3]              Net          -        -       -         -           28        
+RDD37_0_a2         ORCALUT4     D        In      0.000     1.309       -         
+RDD37_0_a2         ORCALUT4     Z        Out     1.265     2.573       -         
+RDD37              Net          -        -       -         -           8         
+RDD[0]             FD1P3AX      SP       In      0.000     2.573       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 171MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_1200hc-4
+
+Register bits: 118 of 1280 (9%)
+PIC Latch:       0
+I/O cells:       73
+
+
+Details:
+BB:             17
+CCU2D:          13
+FD1P3AX:        24
+FD1S3AX:        17
+FD1S3DX:        27
+GSR:            1
+IB:             26
+IFS1P3DX:       18
+INV:            7
+OB:             28
+OBZ:            2
+ODDRXE:         1
+OFS1P3BX:       7
+OFS1P3DX:       12
+OFS1P3IX:       10
+OFS1P3JX:       3
+ORCALUT4:       240
+PFUMX:          7
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 171MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Thu Jun 13 00:38:51 2024
+
+###########################################################]
+
+
+
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+<BR>
+</PRE></FONT>
+</BODY>
+</HTML>