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499 Commits 3 Branches 31 Tags 162 MiB
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499 Commits

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Author SHA1 Message Date
Steven Hugg
85b2241555 added Makefile back to tools; vcs.mame 2018-11-27 18:33:09 -05:00
Steven Hugg
b52f3c2271 added scr2floyd utils 2018-11-27 16:22:57 -05:00
Steven Hugg
13a6f92d7b updated coleco presets; #include finds files in the subfolder of main file 2018-11-27 15:07:39 -05:00
Steven Hugg
958e20c700 made replaydiv stretch properly; smaller verilog gutter 2018-11-26 18:02:53 -05:00
Steven Hugg
8deda746fa mobile device optimization 2018-11-26 10:26:51 -05:00
Steven Hugg
fb418daf3d faster, better C compile flags for SDCC 2018-11-26 10:07:51 -05:00
Steven Hugg
7b30bb74e6 added z-index for verilog scope 2018-11-26 07:24:49 -05:00
Steven Hugg
b5e3331323 Merge branch 'master' of github.com:sehugg/8bitworkshop 2018-11-26 07:10:52 -05:00
Steven Hugg
d2237a3e30 use flex for verilog scope layout 2018-11-26 06:17:20 -05:00
Steven Hugg
7c26b05602 nicer TMS9918 debug info 2018-11-25 14:25:50 -05:00
Steven Hugg
5d753892fa version 3.2.1 2018-11-25 08:01:42 -05:00
Steven Hugg
e51a49b18d took out verilog for now 2018-11-25 07:59:25 -05:00
Steven Hugg
637f53c8a7 more css tweaks 2018-11-25 07:44:20 -05:00
Steven Hugg
e90b60faa3 css tweaks 2018-11-25 07:18:32 -05:00
Steven Hugg
71b4e68a55 added silly 8bitworkshop logo 2018-11-24 19:51:31 -05:00
Steven Hugg
19e2e36fe7 checkRunReady() 2018-11-24 16:51:29 -05:00
Steven Hugg
a10559634f can't create a blank file; fixed .h gutter format; right align info links 2018-11-24 16:31:07 -05:00
Steven Hugg
a511d81c97 less padding on CRT style, overscan option 2018-11-24 15:43:39 -05:00
Steven Hugg
764fafa035 can add include/linked files to project 2018-11-24 15:43:08 -05:00
Steven Hugg
9bd8053dbd moved window list to sidebar; 3-way split 2018-11-24 13:06:13 -05:00
Steven Hugg
84c8c12092 added Split for main window 2018-11-24 07:33:34 -05:00
Steven Hugg
4034be10c4 skeleton for bb 2018-11-23 10:10:32 -05:00
Steven Hugg
149ee4a2eb python 2->3 for tools 2018-11-22 14:11:56 -05:00
Steven Hugg
6e50cbb20e made WorkerOutput/VerilogOutput type more specific; FILE__filename_ext define for mcpp 2018-11-22 13:31:18 -05:00
Steven Hugg
43e33f143c showHelp(), -f3 2018-11-22 12:18:26 -05:00
Steven Hugg
d5a89b0837 updated to jquery 3.3.1, except for w2ui; markdown tweaks 2018-11-22 07:41:56 -05:00
Steven Hugg
e51bd2a579 coleco updates 2018-11-22 07:41:56 -05:00
Steven Hugg
527660b121 isDebugging() instead of getDebugCallback() 2018-11-22 07:39:27 -05:00
Steven Hugg
a39bc2344e added markdown platform (using showdown.js) 2018-11-21 12:18:22 -05:00
Steven Hugg
a7b1fb4f57 try to get bbasic listings, fixed highlighting 2018-11-21 07:57:10 -05:00
Steven Hugg
eb01bdcea0 batari basic: more examples, more RAM, started syntax highlighting, online help 2018-11-20 20:41:12 -05:00
Steven Hugg
3018f27576 added batari basic preprocessor, more examples 2018-11-20 14:10:04 -05:00
Steven Hugg
f337b52be3 started integrating batariBASIC 2018-11-20 12:31:19 -05:00
Steven Hugg
97f69c2af1 converted tms9918a to typescript class 2018-11-19 18:59:56 -05:00
Steven Hugg
a1aa24f2e8 started msx1 2018-11-19 13:58:16 -05:00
Steven Hugg
43ac950a52 added js coleco platform 2018-11-19 09:11:50 -05:00
Steven Hugg
30ac9a3509 added tms9918a 2018-11-18 19:46:55 -05:00
Steven Hugg
ca0c7cf045 verilog.sim platform and verilog.html 2018-11-18 12:30:41 -05:00
Steven Hugg
a76a6c81b8 Merge branch 'master' of github.com:sehugg/8bitworkshop 2018-11-15 20:01:15 -05:00
Steven Hugg
8e1ddfe1ea can't resume before ROM build; added verilog to demo.html 2018-11-15 20:01:02 -05:00
Steven Hugg
bf2250310b moved fpga examples to https://github.com/sehugg/fpga-examples; new framebuffer.v 2018-11-12 14:13:17 -05:00
Steven Hugg
d5154a649a added platform verilog to menu; fixed for TS 3.1 2018-10-11 11:43:09 -04:00
Steven Hugg
b171def11a fixed some tests 2018-10-11 11:23:19 -04:00
Steven Hugg
3ff3789bf8 minor scope tweaks, need phantomjs for wavedrom 2018-10-11 11:08:19 -04:00
Steven Hugg
24d681cbb8 fixed ball_paddle.v 2018-10-09 19:37:38 -04:00
Steven Hugg
706a24c96a updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
Steven Hugg
c687006684 converted workermain to ts, needs loader.js 2018-10-05 10:08:19 -04:00
Steven Hugg
398103c3b9 minor fixes 2018-10-05 09:36:10 -04:00
Steven Hugg
aa9a829373 fix unit tests 2018-10-03 21:14:10 -04:00
Steven Hugg
190ea9fbda verilog tank example 2018-10-03 18:49:14 -04:00