12 Commits

Author	SHA1	Message	Date
Steven Hugg	85932132d1	verilog: fixed $time for tests (timescale == msec)	2021-07-08 16:47:27 -05:00
Steven Hugg	42920337ec	verilog: fix optimization for tick2(), removed > 64 bit tests, stop tracing when $stop/$finish, +SignExt	2021-07-08 15:50:16 -05:00
Steven Hugg	5ab0e397d3	verilog: fixed 64-bit casting, constant issues	2021-07-08 13:00:44 -05:00
Steven Hugg	6ac29d78dc	add binaryen.js to lib/	2021-07-07 20:37:46 -05:00
Steven Hugg	b9a0de6cac	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
Steven Hugg	e703c16dfe	verilog: worker re-uses memory	2021-07-06 23:56:01 -05:00
Steven Hugg	5cf56f9d04	verilog: sort var defs, fix video sync	2021-07-06 22:26:29 -05:00
Steven Hugg	9bb79c318f	(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm	2021-06-30 18:07:55 -05:00
Steven Hugg	80588fcb31	verilog: scope updates, show js code, simple cpu	2017-11-28 20:38:48 -05:00
Steven Hugg	1cace9d35c	more verilog unit tests; updated SDCC js/wasm	2017-11-23 19:16:54 -05:00
Steven Hugg	aad8efcfec	added more verilog test cases	2017-11-22 16:51:21 -05:00
Steven Hugg	73e908256e	started adding verilog regress tests	2017-11-22 09:44:57 -05:00