David Banks
3cc7789923
6502/65c02: Uncomment Rdy in .ucf file
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Change-Id: I6ef4f92dc4e0438c169d20ab5b05f8d4162478ff
2019-10-17 14:47:08 +01:00
David Banks
f4bff7757c
Use CPU_65C02 for defined as CPU == 65C02 doesn't work
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Change-Id: Ibedbac5941ab897f0d530dfa3d73cc516d62bd8f
2019-10-16 20:41:08 +01:00
David Banks
1c44718f91
Seperate 6502 and 65c02 builds
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Change-Id: I41af27c62e61a6490bda4da01da6e4f8740121fb
2019-10-16 20:40:15 +01:00
David Banks
cc1c8ba709
Multiboot: increase cclk to 26MHz
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Change-Id: I7bb6c17a582c7d283458bd7ed8a1bc2852bb73b3
2019-10-16 16:11:44 +01:00
David Banks
131312e0e9
Multiboot: initial impl
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Change-Id: I7efa2cf8079b4bfc1e89c5c26ecce30dfae34782
2019-10-16 15:49:58 +01:00
David Banks
9bcea56588
z80: CLK_n timing constraint now 8MHz
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Change-Id: Ia544905845a8b7996ff3e381a1e47184cc5dda82
2019-10-15 11:45:51 +01:00
David Banks
4c746994cb
z80: major rewrite of memory access state machine
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Change-Id: Icc5c7c991120ed155691c1e74517ac02f8ea2ada
2019-10-14 13:35:13 +01:00
David Banks
984ac1a2d3
z80: fixed an error in board.ucf in the previous commit
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Change-Id: Ib83916a7e1d1dcc163001ab342e65b80858d9c29
2019-10-03 18:26:15 +01:00
David Banks
dfeaff9488
6502: minor fixes to lx9_dave, boots in beeb
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Change-Id: I18c909f7586b439d52ecc938d4a9bb7a3e6d76e5
2019-10-03 13:17:18 +01:00
David Banks
c660ea87be
Updated lx9_dave/ice6502 for active level shifter design
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Change-Id: Ib2e98050d02c9c1e3dd7c9a9b63eea118b95a540
2019-09-20 15:34:44 +01:00
David Banks
a25a008ffc
Updated lx9_dave/icez80 for active level shifter design
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Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
David Banks
e9d4e98b96
LX9 6502: Move fakeTube input to p112 (next to a GND)
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Change-Id: Ib52362ed12ddc885025f1e098f864fdb313b795d
2018-12-21 17:45:22 +00:00
David Banks
1dcf9fa247
Updated lx9_dave/ice6502 with correct .ucf file and a new top-level design
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Change-Id: Ic67e37fb876322983a44c35e9db08b1b8371aea2
2018-11-20 17:32:02 +00:00
David Banks
b9d6359be4
Checked in initial work on lx9_dave target (see full comment)
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The .ucf files look like they are for a completely different board
(the lx9 starter board, not the epizza board). So these need to be
reworked completely.
Also, the following signals needs adding to the top level 6502 design:
- OEAH (output)
- OEAL (output)
- OED (output)
- ML (output)
- VP (output)
- BE (input)
The system will not work without some attention to these.
Minimally, in the FPGA design we can tie them as follows:
- OEAH (output) - set to 0 (address bus always enabled)
- OEAL (output) - set to 0 (ditto)
- OED (output) - set to !phi2 (data bus driven in second half of clock)
- ML (output) - set output to 1 (and fit P3 link between pins 2 and 3)
- VP (output) - set output to 1 (and don't fit P4 link)
- BE (input) - ignore input
The current adapter design does not fully support the implementation of BE
as it does not provide a way to tristate RNW. That would require the addition
of a seperate level shifter, e.g. a 74LVC1G125
Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:42:58 +00:00
David Banks
40cac3c401
Updated Makefile for 64-bit build
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Change-Id: Ieaa309d30463209cd0e9c1aa6e6b23cbec8e92b0
2018-02-15 13:05:49 +00:00
David Banks
e45e4423af
Added lx9_jason_flipped to build
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Change-Id: I6c0a140a1e5229dca8eddc770a232712de17cd4b
2017-09-22 22:57:54 +01:00
David Banks
7954f86e41
Added build for a flipped version of Jason's level shifter, so USB comes out at the pin 1 end (better for Beeb)
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Change-Id: Icd48522640507469b43ca3545fa1c46f88b0f0bb
2017-08-09 18:16:11 +01:00
David Banks
168e5637e9
Pinout change for LX9: DIP pins 37 and 38 needed swapping
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Change-Id: I3f96f2d7cd8a8640e4a6c60466067daccf1e0590
2017-08-09 16:37:41 +01:00
David Banks
6415a81a40
On LX9 board, updated Tx=51 and Rx=55
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Change-Id: I5bcd032eab29ef93d36e8011fee673028042483f
2017-07-29 19:55:27 +01:00
David Banks
7453cf4f9f
LX9 support: massive refactor of the build system
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Change-Id: I75ff141a0d3b2c30a37d8f0e497f4f923e302b8b
2017-07-26 14:59:20 +01:00
