2022-05-01 19:10:54 +00:00
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//
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// ExecutorImplementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 01/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_M68k_ExecutorImplementation_hpp
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#define InstructionSets_M68k_ExecutorImplementation_hpp
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2022-05-01 19:14:12 +00:00
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#include "../Perform.hpp"
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2022-05-01 19:10:54 +00:00
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#include <cassert>
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namespace InstructionSet {
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namespace M68k {
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template <Model model, typename BusHandler>
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Executor<model, BusHandler>::Executor(BusHandler &handler) : bus_handler_(handler) {
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reset();
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::reset() {
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// Establish: supervisor state, all interrupts blocked.
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status_.set_status(0b0010'0011'1000'0000);
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2022-05-03 01:27:58 +00:00
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did_update_status();
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2022-05-01 19:10:54 +00:00
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// Seed stack pointer and program counter.
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2022-05-02 00:40:57 +00:00
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data_[7].l = bus_handler_.template read<uint32_t>(0);
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2022-05-01 19:10:54 +00:00
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program_counter_.l = bus_handler_.template read<uint32_t>(4);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::read(DataSize size, uint32_t address, CPU::SlicedInt32 &value) {
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switch(size) {
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case DataSize::Byte:
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value.b = bus_handler_.template read<uint8_t>(address);
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break;
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case DataSize::Word:
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value.w = bus_handler_.template read<uint16_t>(address);
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break;
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case DataSize::LongWord:
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value.l = bus_handler_.template read<uint32_t>(address);
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break;
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}
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::write(DataSize size, uint32_t address, CPU::SlicedInt32 value) {
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switch(size) {
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case DataSize::Byte:
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bus_handler_.template write<uint8_t>(address, value.b);
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break;
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case DataSize::Word:
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bus_handler_.template write<uint16_t>(address, value.w);
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break;
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case DataSize::LongWord:
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bus_handler_.template write<uint32_t>(address, value.l);
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break;
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}
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}
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template <Model model, typename BusHandler>
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template <typename IntT> IntT Executor<model, BusHandler>::read_pc() {
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const IntT result = bus_handler_.template read<IntT>(program_counter_.l);
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if constexpr (sizeof(IntT) == 4) {
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program_counter_.l += 4;
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} else {
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program_counter_.l += 2;
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}
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return result;
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}
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template <Model model, typename BusHandler>
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uint32_t Executor<model, BusHandler>::index_8bitdisplacement() {
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// TODO: if not a 68000, check bit 8 for whether this should be a full extension word;
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// also include the scale field even if not.
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const auto extension = read_pc<uint16_t>();
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const auto offset = int8_t(extension);
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2022-05-02 19:09:59 +00:00
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const int register_index = (extension >> 12) & 7;
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2022-05-01 19:10:54 +00:00
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const uint32_t displacement = (extension & 0x8000) ? address_[register_index].l : data_[register_index].l;
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2022-05-02 19:09:59 +00:00
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const uint32_t sized_displacement = (extension & 0x800) ? displacement : int16_t(displacement);
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return offset + sized_displacement;
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2022-05-01 19:10:54 +00:00
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}
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template <Model model, typename BusHandler>
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typename Executor<model, BusHandler>::EffectiveAddress Executor<model, BusHandler>::calculate_effective_address(Preinstruction instruction, uint16_t opcode, int index) {
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EffectiveAddress ea;
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switch(instruction.mode(index)) {
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case AddressingMode::None:
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// Permit an uninitialised effective address to be returned;
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// this value shouldn't be used.
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break;
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//
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// Operands that don't have effective addresses, which are returned as values.
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//
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case AddressingMode::DataRegisterDirect:
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2022-05-01 19:21:58 +00:00
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ea.value = data_[instruction.reg(index)];
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = false;
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2022-05-01 19:10:54 +00:00
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break;
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case AddressingMode::AddressRegisterDirect:
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2022-05-01 19:21:58 +00:00
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ea.value = address_[instruction.reg(index)];
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ea.requires_fetch = false;
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break;
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case AddressingMode::Quick:
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2022-05-03 15:09:57 +00:00
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ea.value.l = quick(opcode, instruction.operation);
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ea.requires_fetch = false;
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break;
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case AddressingMode::ImmediateData:
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2022-05-03 00:17:44 +00:00
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switch(instruction.size()) {
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case DataSize::Byte:
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ea.value.l = read_pc<uint16_t>() & 0xff;
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break;
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case DataSize::Word:
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ea.value.l = read_pc<uint16_t>();
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break;
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case DataSize::LongWord:
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ea.value.l = read_pc<uint32_t>();
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break;
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}
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = false;
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2022-05-01 19:10:54 +00:00
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break;
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//
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// Absolute addresses.
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//
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case AddressingMode::AbsoluteShort:
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ea.value.l = int16_t(read_pc<uint16_t>());
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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2022-05-01 19:10:54 +00:00
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break;
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case AddressingMode::AbsoluteLong:
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ea.value.l = read_pc<uint32_t>();
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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2022-05-01 19:10:54 +00:00
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break;
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//
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// Address register indirects.
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//
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case AddressingMode::AddressRegisterIndirect:
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2022-05-02 00:40:57 +00:00
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ea.value = address_[instruction.reg(index)];
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ea.requires_fetch = true;
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2022-05-01 19:10:54 +00:00
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break;
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case AddressingMode::AddressRegisterIndirectWithPostincrement: {
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const auto reg = instruction.reg(index);
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2022-05-02 00:40:57 +00:00
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ea.value = address_[reg];
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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2022-05-01 19:10:54 +00:00
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switch(instruction.size()) {
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2022-05-01 19:18:06 +00:00
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case DataSize::Byte: address_[reg].l += byte_increments[reg]; break;
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case DataSize::Word: address_[reg].l += 2; break;
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case DataSize::LongWord: address_[reg].l += 4; break;
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2022-05-01 19:10:54 +00:00
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}
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} break;
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case AddressingMode::AddressRegisterIndirectWithPredecrement: {
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const auto reg = instruction.reg(index);
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switch(instruction.size()) {
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2022-05-01 19:18:06 +00:00
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case DataSize::Byte: address_[reg].l -= byte_increments[reg]; break;
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case DataSize::Word: address_[reg].l -= 2; break;
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case DataSize::LongWord: address_[reg].l -= 4; break;
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2022-05-01 19:10:54 +00:00
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}
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2022-05-02 00:40:57 +00:00
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ea.value = address_[reg];
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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2022-05-01 19:10:54 +00:00
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} break;
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case AddressingMode::AddressRegisterIndirectWithDisplacement:
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2022-05-01 19:21:58 +00:00
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ea.value.l = address_[instruction.reg(index)].l + int16_t(read_pc<uint16_t>());
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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break;
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case AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement:
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2022-05-01 19:21:58 +00:00
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ea.value.l = address_[instruction.reg(index)].l + index_8bitdisplacement();
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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break;
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//
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// PC-relative addresses.
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//
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// TODO: rephrase these in terms of instruction_address_. Just for security
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// against whatever mutations the PC has been through already to get to here.
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//
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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ea.value.l = program_counter_.l + int16_t(read_pc<uint16_t>());
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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2022-05-01 19:10:54 +00:00
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break;
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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ea.value.l = program_counter_.l + index_8bitdisplacement();
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2022-05-01 19:12:13 +00:00
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ea.requires_fetch = true;
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break;
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default:
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// TODO.
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assert(false);
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break;
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}
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return ea;
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::run_for_instructions(int count) {
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while(count--) {
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// TODO: check interrupt level, trace flag.
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// Read the next instruction.
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instruction_address_ = program_counter_.l;
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const auto opcode = read_pc<uint16_t>();
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const Preinstruction instruction = decoder_.decode(opcode);
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2022-05-03 01:27:58 +00:00
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if(!status_.is_supervisor_ && instruction.requires_supervisor()) {
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raise_exception(8);
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continue;
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}
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if(instruction.operation == Operation::Undefined) {
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switch(opcode & 0xf000) {
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default:
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raise_exception(4);
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continue;
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case 0xa000:
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raise_exception(10);
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continue;
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case 0xf000:
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raise_exception(11);
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continue;
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}
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}
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2022-05-01 19:10:54 +00:00
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// Temporary storage.
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CPU::SlicedInt32 operand_[2];
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EffectiveAddress effective_address_[2];
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// Calculate effective addresses; copy 'addresses' into the
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// operands by default both: (i) because they might be values,
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// rather than addresses; and (ii) then they'll be there for use
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// by LEA and PEA.
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//
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2022-05-01 19:30:03 +00:00
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// TODO: much of this work should be performed by a full Decoder,
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// so that it can be cached.
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effective_address_[0] = calculate_effective_address(instruction, opcode, 0);
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effective_address_[1] = calculate_effective_address(instruction, opcode, 1);
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operand_[0] = effective_address_[0].value;
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operand_[1] = effective_address_[1].value;
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// Obtain the appropriate sequence.
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//
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// TODO: make a decision about whether this goes into a fully-decoded Instruction.
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const auto flags = operand_flags<model>(instruction.operation);
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2022-05-03 13:04:54 +00:00
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// TODO: potential alignment exception, here and in store.
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#define fetch_operand(n) \
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if(effective_address_[n].requires_fetch) { \
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read(instruction.size(), effective_address_[n].value.l, operand_[n]); \
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}
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2022-05-03 13:04:54 +00:00
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if(flags & FetchOp1) { fetch_operand(0); }
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if(flags & FetchOp2) { fetch_operand(1); }
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2022-05-03 13:04:54 +00:00
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#undef fetch_operand
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perform<model>(instruction, operand_[0], operand_[1], status_, *this);
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2022-05-03 13:04:54 +00:00
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// TODO: is it worth holding registers as a single block to avoid conditional below?
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#define store_operand(n) \
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if(!effective_address_[n].requires_fetch) { \
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if(instruction.mode(n) == AddressingMode::DataRegisterDirect) { \
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data_[instruction.reg(n)] = operand_[n]; \
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} else { \
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address_[instruction.reg(n)] = operand_[n]; \
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} \
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} else { \
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write(instruction.size(), effective_address_[n].value.l, operand_[n]); \
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}
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2022-05-01 19:10:54 +00:00
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2022-05-03 13:04:54 +00:00
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if(flags & StoreOp1) { store_operand(0); }
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if(flags & StoreOp2) { store_operand(1); }
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2022-05-01 19:10:54 +00:00
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2022-05-03 13:04:54 +00:00
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#undef store_operand
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}
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}
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2022-05-02 16:57:45 +00:00
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// MARK: - State
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template <Model model, typename BusHandler>
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typename Executor<model, BusHandler>::Registers Executor<model, BusHandler>::get_state() {
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Registers result;
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for(int c = 0; c < 8; c++) {
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result.data[c] = data_[c].l;
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}
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for(int c = 0; c < 7; c++) {
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result.address[c] = address_[c].l;
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}
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result.status = status_.status();
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result.program_counter = program_counter_.l;
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stack_pointers_[status_.is_supervisor_] = address_[7];
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result.user_stack_pointer = stack_pointers_[0].l;
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result.supervisor_stack_pointer = stack_pointers_[1].l;
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return result;
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::set_state(const Registers &state) {
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for(int c = 0; c < 8; c++) {
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data_[c].l = state.data[c];
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}
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for(int c = 0; c < 7; c++) {
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address_[c].l = state.address[c];
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}
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status_.set_status(state.status);
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program_counter_.l = state.program_counter;
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stack_pointers_[0].l = state.user_stack_pointer;
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stack_pointers_[1].l = state.supervisor_stack_pointer;
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address_[7] = stack_pointers_[status_.is_supervisor_];
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}
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// MARK: - Flow Control.
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2022-05-02 11:45:07 +00:00
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// TODO: flow control, all below here.
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template <Model model, typename BusHandler>
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2022-05-03 01:27:58 +00:00
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void Executor<model, BusHandler>::raise_exception(int index) {
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const uint32_t address = index << 2;
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// Grab the status to store, then switch into supervisor mode.
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const uint16_t status = status_.status();
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status_.is_supervisor_ = 1;
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did_update_status();
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// Push status and the program counter at instruction start.
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bus_handler_.template write<uint32_t>(address_[7].l - 4, instruction_address_);
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bus_handler_.template write<uint16_t>(address_[7].l - 6, status);
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address_[7].l -= 6;
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// Fetch the new program counter.
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program_counter_.l = bus_handler_.template read<uint32_t>(address);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::did_update_status() {
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// Shuffle the stack pointers.
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stack_pointers_[active_stack_pointer_] = address_[7];
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address_[7] = stack_pointers_[status_.is_supervisor_];
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active_stack_pointer_ = status_.is_supervisor_;
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}
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2022-05-02 11:45:07 +00:00
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::stop() {}
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template <Model model, typename BusHandler>
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2022-05-03 18:40:51 +00:00
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void Executor<model, BusHandler>::set_pc(uint32_t address) {
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program_counter_.l = address;
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}
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2022-05-02 11:45:07 +00:00
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template <Model model, typename BusHandler>
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2022-05-03 18:40:51 +00:00
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void Executor<model, BusHandler>::add_pc(uint32_t offset) {
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2022-05-03 19:21:42 +00:00
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program_counter_.l = instruction_address_ + offset;
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2022-05-03 18:40:51 +00:00
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}
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2022-05-02 11:45:07 +00:00
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2022-05-03 19:32:54 +00:00
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::bsr(uint32_t offset) {
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address_[7].l -= 4;
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bus_handler_.template write<uint32_t>(address_[7].l, program_counter_.l);
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program_counter_.l = instruction_address_ + offset;
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}
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2022-05-01 19:10:54 +00:00
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}
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}
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#endif /* InstructionSets_M68k_ExecutorImplementation_hpp */
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