2017-11-26 13:28:26 -05:00
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//
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// 9918.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 25/11/2017.
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2018-05-13 15:19:52 -04:00
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// Copyright 2017 Thomas Harte. All rights reserved.
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2017-11-26 13:28:26 -05:00
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//
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2023-01-01 14:01:19 -05:00
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#include "../9918.hpp"
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2017-11-26 13:28:26 -05:00
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2017-12-06 20:24:29 -05:00
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#include <cassert>
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2017-12-05 22:39:03 -05:00
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#include <cstring>
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2018-10-26 21:02:56 -04:00
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#include <cstdlib>
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2023-01-01 14:01:19 -05:00
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#include "../../../Outputs/Log.hpp"
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2017-12-05 22:39:03 -05:00
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2018-09-17 22:59:16 -04:00
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using namespace TI::TMS;
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2017-11-26 13:28:26 -05:00
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2017-11-27 22:05:40 -05:00
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namespace {
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2018-10-19 21:36:13 -04:00
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// 342 internal cycles are 228/227.5ths of a line, so 341.25 cycles should be a whole
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// line. Therefore multiply everything by four, but set line length to 1365 rather than 342*4 = 1368.
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2019-12-22 00:22:17 -05:00
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constexpr unsigned int CRTCyclesPerLine = 1365;
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constexpr unsigned int CRTCyclesDivider = 4;
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2018-10-19 21:36:13 -04:00
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2017-11-27 22:05:40 -05:00
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}
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2022-12-31 21:47:05 -05:00
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template <Personality personality>
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2022-12-31 21:50:57 -05:00
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Base<personality>::Base() :
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2018-11-14 22:25:19 -05:00
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crt_(CRTCyclesPerLine, CRTCyclesDivider, Outputs::Display::Type::NTSC60, Outputs::Display::InputDataType::Red8Green8Blue8) {
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2018-11-22 22:47:29 -05:00
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// Unimaginatively, this class just passes RGB through to the shader. Investigation is needed
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// into whether there's a more natural form. It feels unlikely given the diversity of chips modelled.
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2018-09-17 22:59:16 -04:00
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2022-12-31 21:50:57 -05:00
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if constexpr (is_sega_vdp(personality)) {
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2018-10-21 13:58:34 -04:00
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mode_timing_.line_interrupt_position = 64;
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2018-10-12 18:57:07 -04:00
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2018-10-11 21:42:09 -04:00
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mode_timing_.end_of_frame_interrupt_position.column = 63;
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mode_timing_.end_of_frame_interrupt_position.row = 193;
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2018-10-04 22:50:35 -04:00
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}
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2018-10-14 16:23:45 -04:00
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2018-10-26 21:02:56 -04:00
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// Establish that output is delayed after reading by `output_lag` cycles; start
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// at a random position.
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read_pointer_.row = rand() % 262;
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2023-01-07 09:13:34 -05:00
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read_pointer_.column = rand() % (Timing<personality>::CyclesPerLine - output_lag);
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2018-10-26 21:02:56 -04:00
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write_pointer_.row = read_pointer_.row;
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write_pointer_.column = read_pointer_.column + output_lag;
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2018-09-17 22:59:16 -04:00
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}
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2017-12-14 20:27:26 -05:00
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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2022-12-31 21:50:57 -05:00
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TMS9918<personality>::TMS9918() {
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2022-12-31 21:47:05 -05:00
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this->crt_.set_display_type(Outputs::Display::DisplayType::RGB);
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this->crt_.set_visible_area(Outputs::Display::Rect(0.07f, 0.0375f, 0.875f, 0.875f));
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2018-03-03 13:53:00 -05:00
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// The TMS remains in-phase with the NTSC colour clock; this is an empirical measurement
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// intended to produce the correct relationship between the hard edges between pixels and
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// the colour clock. It was eyeballed rather than derived from any knowledge of the TMS
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// colour burst generator because I've yet to find any.
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2022-12-31 21:47:05 -05:00
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this->crt_.set_immediate_default_phase(0.85f);
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2017-11-26 13:28:26 -05:00
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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void TMS9918<personality>::set_tv_standard(TVStandard standard) {
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2022-12-31 21:47:05 -05:00
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this->tv_standard_ = standard;
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2018-10-19 21:36:13 -04:00
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switch(standard) {
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case TVStandard::PAL:
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2022-12-31 21:47:05 -05:00
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this->mode_timing_.total_lines = 313;
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this->mode_timing_.first_vsync_line = 253;
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this->crt_.set_new_display_type(CRTCyclesPerLine, Outputs::Display::Type::PAL50);
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2018-10-19 21:36:13 -04:00
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break;
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default:
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2022-12-31 21:47:05 -05:00
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this->mode_timing_.total_lines = 262;
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this->mode_timing_.first_vsync_line = 227;
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this->crt_.set_new_display_type(CRTCyclesPerLine, Outputs::Display::Type::NTSC60);
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2018-10-19 21:36:13 -04:00
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break;
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}
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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void TMS9918<personality>::set_scan_target(Outputs::Display::ScanTarget *scan_target) {
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2022-12-31 21:47:05 -05:00
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this->crt_.set_scan_target(scan_target);
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2017-11-26 13:28:26 -05:00
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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Outputs::Display::ScanStatus TMS9918<personality>::get_scaled_scan_status() const {
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2020-01-22 19:34:10 -05:00
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// The input was scaled by 3/4 to convert half cycles to internal ticks,
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// so undo that and also allow for: (i) the multiply by 4 that it takes
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// to reach the CRT; and (ii) the fact that the half-cycles value was scaled,
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// and this should really reply in whole cycles.
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2022-12-31 21:47:05 -05:00
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return this->crt_.get_scaled_scan_status() * (4.0f / (3.0f * 8.0f));
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2020-01-20 21:45:10 -05:00
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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void TMS9918<personality>::set_display_type(Outputs::Display::DisplayType display_type) {
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2022-12-31 21:47:05 -05:00
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this->crt_.set_display_type(display_type);
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2018-11-29 20:44:21 -08:00
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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Outputs::Display::DisplayType TMS9918<personality>::get_display_type() const {
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2022-12-31 21:47:05 -05:00
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return this->crt_.get_display_type();
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2020-03-18 00:06:52 -04:00
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}
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2022-12-31 21:47:05 -05:00
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void LineBuffer::reset_sprite_collection() {
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2018-10-14 16:23:45 -04:00
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sprites_stopped = false;
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active_sprite_slot = 0;
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2018-10-08 22:43:10 -04:00
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2018-10-14 16:23:45 -04:00
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for(int c = 0; c < 8; ++c) {
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active_sprites[c].shift_position = 0;
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2018-10-08 22:43:10 -04:00
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}
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2018-10-06 19:27:19 -04:00
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}
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2022-12-31 21:47:05 -05:00
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template <Personality personality>
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void Base<personality>::posit_sprite(LineBuffer &buffer, int sprite_number, int sprite_position, int screen_row) {
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2018-10-06 19:27:19 -04:00
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if(!(status_ & StatusSpriteOverflow)) {
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2020-05-09 23:00:39 -04:00
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status_ = uint8_t((status_ & ~0x1f) | (sprite_number & 0x1f));
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2017-12-05 22:39:03 -05:00
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}
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2022-12-29 22:09:14 -05:00
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if(buffer.sprites_stopped) return;
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2017-12-05 22:39:03 -05:00
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// A sprite Y of 208 means "don't scan the list any further".
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2018-10-23 20:01:47 -04:00
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if(mode_timing_.allow_sprite_terminator && sprite_position == mode_timing_.sprite_terminator) {
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2018-10-14 16:23:45 -04:00
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buffer.sprites_stopped = true;
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2017-12-05 22:39:03 -05:00
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return;
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}
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2018-10-18 21:48:57 -04:00
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const int sprite_row = (((screen_row + 1) % mode_timing_.total_lines) - ((sprite_position + 1) & 255)) & 255;
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2017-12-06 20:24:29 -05:00
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if(sprite_row < 0 || sprite_row >= sprite_height_) return;
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2017-12-08 22:12:39 -05:00
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2018-10-14 16:23:45 -04:00
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if(buffer.active_sprite_slot == mode_timing_.maximum_visible_sprites) {
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2018-10-06 19:27:19 -04:00
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status_ |= StatusSpriteOverflow;
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2017-12-05 22:39:03 -05:00
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return;
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}
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2018-10-14 16:23:45 -04:00
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LineBuffer::ActiveSprite &sprite = buffer.active_sprites[buffer.active_sprite_slot];
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2017-12-08 22:20:21 -05:00
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sprite.index = sprite_number;
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2017-12-09 20:30:12 -05:00
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sprite.row = sprite_row >> (sprites_magnified_ ? 1 : 0);
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2018-10-14 16:23:45 -04:00
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++buffer.active_sprite_slot;
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2017-12-05 22:39:03 -05:00
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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void TMS9918<personality>::run_for(const HalfCycles cycles) {
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2017-11-27 19:43:33 -05:00
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// As specific as I've been able to get:
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2017-12-09 20:30:12 -05:00
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// Scanline time is always 228 cycles.
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2017-11-27 19:43:33 -05:00
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// PAL output is 313 lines total. NTSC output is 262 lines total.
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// Interrupt is signalled upon entering the lower border.
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2017-12-13 22:37:27 -05:00
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// Convert 456 clocked half cycles per line to 342 internal cycles per line;
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// the internal clock is 1.5 times the nominal 3.579545 Mhz that I've advertised
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// for this part. So multiply by three quarters.
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2023-01-02 15:04:08 -05:00
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const int int_cycles = this->clock_converter_.to_internal(cycles.as<int>());
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2017-11-27 21:36:12 -05:00
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if(!int_cycles) return;
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2017-11-27 19:43:33 -05:00
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2018-10-14 16:23:45 -04:00
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// There are two intertwined processes here, 'writing' (which means writing to the
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// line buffers, i.e. it's everything to do with collecting a line) and 'reading'
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// (which means reading from the line buffers and generating video).
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int write_cycles_pool = int_cycles;
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int read_cycles_pool = int_cycles;
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while(write_cycles_pool || read_cycles_pool) {
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2020-09-16 18:15:57 -04:00
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#ifndef NDEBUG
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2022-12-31 21:47:05 -05:00
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LineBufferPointer backup = this->read_pointer_;
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2020-09-16 18:15:57 -04:00
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#endif
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2018-10-14 18:19:11 -04:00
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2018-10-14 16:23:45 -04:00
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if(write_cycles_pool) {
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// Determine how much writing to do.
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2023-01-01 14:20:45 -05:00
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const int write_cycles = std::min(
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2023-01-06 22:39:46 -05:00
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Timing<personality>::CyclesPerLine - this->write_pointer_.column,
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2023-01-01 14:20:45 -05:00
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write_cycles_pool
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);
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2022-12-31 21:47:05 -05:00
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const int end_column = this->write_pointer_.column + write_cycles;
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LineBuffer &line_buffer = this->line_buffers_[this->write_pointer_.row];
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2018-10-14 16:23:45 -04:00
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2018-10-26 20:19:08 -04:00
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// Determine what this does to any enqueued VRAM access.
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2022-12-31 21:47:05 -05:00
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this->minimum_access_column_ = this->write_pointer_.column + this->cycles_until_access_;
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this->cycles_until_access_ -= write_cycles;
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2018-10-01 23:03:17 -04:00
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2018-10-14 16:23:45 -04:00
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// ---------------------------------------
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// Latch scrolling position, if necessary.
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// ---------------------------------------
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2022-12-31 21:47:05 -05:00
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if constexpr (is_sega_vdp(personality)) {
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if(this->write_pointer_.column < 61 && end_column >= 61) {
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if(!this->write_pointer_.row) {
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this->master_system_.latched_vertical_scroll = this->master_system_.vertical_scroll;
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2018-10-23 21:20:44 -04:00
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2022-12-31 21:47:05 -05:00
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if(this->master_system_.mode4_enable) {
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this->mode_timing_.pixel_lines = 192;
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if(this->mode2_enable_ && this->mode1_enable_) this->mode_timing_.pixel_lines = 224;
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if(this->mode2_enable_ && this->mode3_enable_) this->mode_timing_.pixel_lines = 240;
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2018-10-23 21:20:44 -04:00
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2022-12-31 21:47:05 -05:00
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this->mode_timing_.allow_sprite_terminator = this->mode_timing_.pixel_lines == 192;
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this->mode_timing_.first_vsync_line = (this->mode_timing_.total_lines + this->mode_timing_.pixel_lines) >> 1;
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2018-10-23 21:20:44 -04:00
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2022-12-31 21:47:05 -05:00
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this->mode_timing_.end_of_frame_interrupt_position.row = this->mode_timing_.pixel_lines + 1;
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2018-10-23 21:20:44 -04:00
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}
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}
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2022-12-31 21:47:05 -05:00
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line_buffer.latched_horizontal_scroll = this->master_system_.horizontal_scroll;
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2018-10-14 16:23:45 -04:00
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}
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2018-10-11 22:36:27 -04:00
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}
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2018-10-14 16:23:45 -04:00
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// ------------------------
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// Perform memory accesses.
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// ------------------------
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2023-01-09 22:34:56 -05:00
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#define fetch(function, clock) \
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const int first_window = from_internal<personality, clock>(this->write_pointer_.column);\
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const int final_window = from_internal<personality, clock>(end_column); \
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2023-01-02 15:04:08 -05:00
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if(first_window == final_window) break; \
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2023-01-09 22:34:56 -05:00
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if(final_window != clock_rate<personality, clock>()) { \
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2023-01-02 14:59:36 -05:00
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function<true>(first_window, final_window); \
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} else { \
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function<false>(first_window, final_window); \
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2018-10-01 23:03:17 -04:00
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}
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2017-12-13 22:37:27 -05:00
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2023-01-02 14:59:36 -05:00
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switch(line_buffer.line_mode) {
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2023-01-09 22:34:56 -05:00
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case LineMode::Text: { fetch(this->template fetch_tms_text, Clock::TMSMemoryWindow); } break;
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case LineMode::Character: { fetch(this->template fetch_tms_character, Clock::TMSMemoryWindow); } break;
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case LineMode::SMS: { fetch(this->template fetch_sms, Clock::TMSMemoryWindow); } break;
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case LineMode::Refresh: { fetch(this->template fetch_tms_refresh, Clock::TMSMemoryWindow); } break;
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2018-10-02 21:05:30 -04:00
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}
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2017-12-13 22:37:27 -05:00
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2018-10-01 23:03:17 -04:00
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#undef fetch
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2017-12-13 22:37:27 -05:00
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|
|
|
2018-10-14 16:23:45 -04:00
|
|
|
|
|
|
|
|
|
// -------------------------------
|
|
|
|
|
// Check for interrupt conditions.
|
|
|
|
|
// -------------------------------
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if(this->write_pointer_.column < this->mode_timing_.line_interrupt_position && end_column >= this->mode_timing_.line_interrupt_position) {
|
2018-10-14 16:23:45 -04:00
|
|
|
|
// The Sega VDP offers a decrementing counter for triggering line interrupts;
|
|
|
|
|
// it is reloaded either when it overflows or upon every non-pixel line after the first.
|
|
|
|
|
// It is otherwise decremented.
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
|
|
|
|
if(this->write_pointer_.row >= 0 && this->write_pointer_.row <= this->mode_timing_.pixel_lines) {
|
|
|
|
|
--this->line_interrupt_counter;
|
|
|
|
|
if(this->line_interrupt_counter == 0xff) {
|
|
|
|
|
this->line_interrupt_pending_ = true;
|
|
|
|
|
this->line_interrupt_counter = this->line_interrupt_target;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
}
|
|
|
|
|
} else {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->line_interrupt_counter = this->line_interrupt_target;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// TODO: the V9938 provides line interrupts from direct specification of the target line.
|
|
|
|
|
// So life is easy.
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if(
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->write_pointer_.row == this->mode_timing_.end_of_frame_interrupt_position.row &&
|
|
|
|
|
this->write_pointer_.column < this->mode_timing_.end_of_frame_interrupt_position.column &&
|
|
|
|
|
end_column >= this->mode_timing_.end_of_frame_interrupt_position.column
|
2018-10-14 16:23:45 -04:00
|
|
|
|
) {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->status_ |= StatusInterrupt;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// -------------
|
|
|
|
|
// Advance time.
|
|
|
|
|
// -------------
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->write_pointer_.column = end_column;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
write_cycles_pool -= write_cycles;
|
|
|
|
|
|
2023-01-06 22:39:46 -05:00
|
|
|
|
if(this->write_pointer_.column == Timing<personality>::CyclesPerLine) {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->write_pointer_.column = 0;
|
|
|
|
|
this->write_pointer_.row = (this->write_pointer_.row + 1) % this->mode_timing_.total_lines;
|
|
|
|
|
LineBuffer &next_line_buffer = this->line_buffers_[this->write_pointer_.row];
|
2018-10-14 16:23:45 -04:00
|
|
|
|
|
2023-01-07 14:37:06 -05:00
|
|
|
|
// Establish the current screen output mode, which will be captured as a
|
|
|
|
|
// line mode momentarily.
|
2023-01-07 14:34:33 -05:00
|
|
|
|
this->screen_mode_ = this->current_screen_mode();
|
2018-10-14 16:23:45 -04:00
|
|
|
|
|
|
|
|
|
// Based on the output mode, pick a line mode.
|
2023-01-07 13:10:51 -05:00
|
|
|
|
next_line_buffer.first_pixel_output_column = Timing<personality>::FirstPixelCycle;
|
|
|
|
|
next_line_buffer.next_border_column = Timing<personality>::CyclesPerLine;
|
2023-01-08 21:31:00 -05:00
|
|
|
|
next_line_buffer.pixel_count = 256;
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->mode_timing_.maximum_visible_sprites = 4;
|
|
|
|
|
switch(this->screen_mode_) {
|
2018-10-14 16:23:45 -04:00
|
|
|
|
case ScreenMode::Text:
|
2023-01-08 13:58:12 -05:00
|
|
|
|
next_line_buffer.line_mode = LineMode::Text;
|
|
|
|
|
next_line_buffer.first_pixel_output_column = Timing<personality>::FirstTextCycle;
|
|
|
|
|
next_line_buffer.next_border_column = Timing<personality>::LastTextCycle;
|
2023-01-08 21:31:00 -05:00
|
|
|
|
next_line_buffer.pixel_count = 240;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
break;
|
|
|
|
|
case ScreenMode::SMSMode4:
|
2018-10-14 18:19:11 -04:00
|
|
|
|
next_line_buffer.line_mode = LineMode::SMS;
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->mode_timing_.maximum_visible_sprites = 8;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
break;
|
|
|
|
|
default:
|
2018-10-14 18:19:11 -04:00
|
|
|
|
next_line_buffer.line_mode = LineMode::Character;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if(
|
2022-12-31 21:47:05 -05:00
|
|
|
|
(this->screen_mode_ == ScreenMode::Blank) ||
|
|
|
|
|
(this->write_pointer_.row >= this->mode_timing_.pixel_lines && this->write_pointer_.row != this->mode_timing_.total_lines-1))
|
2018-10-14 18:19:11 -04:00
|
|
|
|
next_line_buffer.line_mode = LineMode::Refresh;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2020-09-16 18:15:57 -04:00
|
|
|
|
#ifndef NDEBUG
|
2022-12-31 21:47:05 -05:00
|
|
|
|
assert(backup.row == this->read_pointer_.row && backup.column == this->read_pointer_.column);
|
|
|
|
|
backup = this->write_pointer_;
|
2020-09-16 18:15:57 -04:00
|
|
|
|
#endif
|
2018-10-14 18:19:11 -04:00
|
|
|
|
|
|
|
|
|
|
2018-10-14 16:23:45 -04:00
|
|
|
|
if(read_cycles_pool) {
|
|
|
|
|
// Determine how much time has passed in the remainder of this line, and proceed.
|
2023-01-01 14:20:45 -05:00
|
|
|
|
const int target_read_cycles = std::min(
|
2023-01-06 22:39:46 -05:00
|
|
|
|
Timing<personality>::CyclesPerLine - this->read_pointer_.column,
|
2023-01-01 14:20:45 -05:00
|
|
|
|
read_cycles_pool
|
|
|
|
|
);
|
2018-10-26 19:26:46 -04:00
|
|
|
|
int read_cycles_performed = 0;
|
|
|
|
|
uint32_t next_cram_value = 0;
|
|
|
|
|
|
|
|
|
|
while(read_cycles_performed < target_read_cycles) {
|
2023-01-01 14:20:45 -05:00
|
|
|
|
int read_cycles = target_read_cycles - read_cycles_performed;
|
|
|
|
|
if(!read_cycles) continue;
|
|
|
|
|
|
2023-01-07 14:57:32 -05:00
|
|
|
|
// Grab the next CRAM dot value and schedule a break in output if applicable.
|
2018-10-26 19:26:46 -04:00
|
|
|
|
const uint32_t cram_value = next_cram_value;
|
2023-01-01 14:20:45 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
2023-01-07 14:57:32 -05:00
|
|
|
|
next_cram_value = 0;
|
|
|
|
|
|
2023-01-01 14:20:45 -05:00
|
|
|
|
if(!this->upcoming_cram_dots_.empty() && this->upcoming_cram_dots_.front().location.row == this->read_pointer_.row) {
|
|
|
|
|
int time_until_dot = this->upcoming_cram_dots_.front().location.column - this->read_pointer_.column;
|
2018-10-26 19:26:46 -04:00
|
|
|
|
|
2023-01-01 14:20:45 -05:00
|
|
|
|
if(time_until_dot < read_cycles) {
|
|
|
|
|
read_cycles = time_until_dot;
|
|
|
|
|
next_cram_value = this->upcoming_cram_dots_.front().value;
|
|
|
|
|
this->upcoming_cram_dots_.erase(this->upcoming_cram_dots_.begin());
|
|
|
|
|
}
|
2018-10-26 19:26:46 -04:00
|
|
|
|
}
|
|
|
|
|
}
|
2018-10-14 16:23:45 -04:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
read_cycles_performed += read_cycles;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
const int end_column = this->read_pointer_.column + read_cycles;
|
|
|
|
|
LineBuffer &line_buffer = this->line_buffers_[this->read_pointer_.row];
|
2018-10-25 23:12:03 -04:00
|
|
|
|
|
2018-10-14 16:23:45 -04:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// --------------------
|
|
|
|
|
// Output video stream.
|
|
|
|
|
// --------------------
|
2017-12-02 22:13:43 -05:00
|
|
|
|
|
2023-01-09 22:34:56 -05:00
|
|
|
|
#define crt_convert(action, time) this->crt_.action(from_internal<personality, Clock::CRT>(time))
|
2023-01-08 14:10:06 -05:00
|
|
|
|
#define output_sync(x) crt_convert(output_sync, x)
|
|
|
|
|
#define output_blank(x) crt_convert(output_blank, x)
|
|
|
|
|
#define output_default_colour_burst(x) crt_convert(output_default_colour_burst, x)
|
|
|
|
|
|
2019-12-22 00:00:23 -05:00
|
|
|
|
#define intersect(left, right, code) { \
|
2022-12-31 21:47:05 -05:00
|
|
|
|
const int start = std::max(this->read_pointer_.column, left); \
|
2018-10-02 21:18:28 -04:00
|
|
|
|
const int end = std::min(end_column, right); \
|
|
|
|
|
if(end > start) {\
|
|
|
|
|
code;\
|
|
|
|
|
}\
|
|
|
|
|
}
|
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
#define border(left, right) intersect(left, right, this->output_border(end - start, cram_value))
|
2018-10-26 19:26:46 -04:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if(line_buffer.line_mode == LineMode::Refresh || this->read_pointer_.row > this->mode_timing_.pixel_lines) {
|
2023-01-07 14:57:32 -05:00
|
|
|
|
if(
|
|
|
|
|
this->read_pointer_.row >= this->mode_timing_.first_vsync_line &&
|
|
|
|
|
this->read_pointer_.row < this->mode_timing_.first_vsync_line + 4
|
|
|
|
|
) {
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// Vertical sync.
|
2023-01-07 14:57:32 -05:00
|
|
|
|
// TODO: the Mega Drive supports interlaced video, I think?
|
|
|
|
|
if(end_column == Timing<personality>::CyclesPerLine) {
|
2023-01-08 14:10:06 -05:00
|
|
|
|
output_sync(Timing<personality>::CyclesPerLine);
|
2018-10-26 19:26:46 -04:00
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
// Right border.
|
2023-01-07 14:57:32 -05:00
|
|
|
|
border(0, Timing<personality>::EndOfRightBorder);
|
2018-10-26 19:26:46 -04:00
|
|
|
|
|
2023-01-08 14:10:06 -05:00
|
|
|
|
// Blanking region: output the entire sequence when the cursor
|
|
|
|
|
// crosses the start-of-border point.
|
|
|
|
|
if(
|
|
|
|
|
this->read_pointer_.column < Timing<personality>::StartOfLeftBorder &&
|
|
|
|
|
end_column >= Timing<personality>::StartOfLeftBorder
|
|
|
|
|
) {
|
|
|
|
|
output_blank(Timing<personality>::StartOfSync - Timing<personality>::EndOfRightBorder);
|
|
|
|
|
output_sync(Timing<personality>::EndOfSync - Timing<personality>::StartOfSync);
|
|
|
|
|
output_blank(Timing<personality>::StartOfColourBurst - Timing<personality>::EndOfSync);
|
|
|
|
|
output_default_colour_burst(Timing<personality>::EndOfColourBurst - Timing<personality>::StartOfColourBurst);
|
|
|
|
|
output_blank(Timing<personality>::StartOfLeftBorder - Timing<personality>::EndOfColourBurst);
|
2018-10-26 19:26:46 -04:00
|
|
|
|
}
|
2018-10-25 23:12:03 -04:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// Border colour for the rest of the line.
|
2023-01-08 14:10:06 -05:00
|
|
|
|
border(Timing<personality>::StartOfLeftBorder, Timing<personality>::CyclesPerLine);
|
2018-10-14 16:23:45 -04:00
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
// Right border.
|
2023-01-08 14:10:06 -05:00
|
|
|
|
border(0, Timing<personality>::EndOfRightBorder);
|
2018-10-14 16:23:45 -04:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// Blanking region.
|
2023-01-08 14:10:06 -05:00
|
|
|
|
if(
|
|
|
|
|
this->read_pointer_.column < Timing<personality>::StartOfLeftBorder &&
|
|
|
|
|
end_column >= Timing<personality>::StartOfLeftBorder
|
|
|
|
|
) {
|
|
|
|
|
output_blank(Timing<personality>::StartOfSync - Timing<personality>::EndOfRightBorder);
|
|
|
|
|
output_sync(Timing<personality>::EndOfSync - Timing<personality>::StartOfSync);
|
|
|
|
|
output_blank(Timing<personality>::StartOfColourBurst - Timing<personality>::EndOfSync);
|
|
|
|
|
output_default_colour_burst(Timing<personality>::EndOfColourBurst - Timing<personality>::StartOfColourBurst);
|
|
|
|
|
output_blank(Timing<personality>::StartOfLeftBorder - Timing<personality>::EndOfColourBurst);
|
2018-10-14 16:23:45 -04:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// Left border.
|
2023-01-08 14:10:06 -05:00
|
|
|
|
border(Timing<personality>::StartOfLeftBorder, line_buffer.first_pixel_output_column);
|
2018-10-26 19:26:46 -04:00
|
|
|
|
|
2023-01-09 22:34:56 -05:00
|
|
|
|
#define draw(function, clock) { \
|
|
|
|
|
const int relative_start = from_internal<personality, clock>(start - line_buffer.first_pixel_output_column); \
|
|
|
|
|
const int relative_end = from_internal<personality, clock>(end - line_buffer.first_pixel_output_column); \
|
2023-01-08 17:31:08 -05:00
|
|
|
|
if(relative_start == relative_end) break; \
|
|
|
|
|
this->function; }
|
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// Pixel region.
|
|
|
|
|
intersect(
|
|
|
|
|
line_buffer.first_pixel_output_column,
|
|
|
|
|
line_buffer.next_border_column,
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if(!this->asked_for_write_area_) {
|
|
|
|
|
this->asked_for_write_area_ = true;
|
2023-01-08 21:25:22 -05:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->pixel_origin_ = this->pixel_target_ = reinterpret_cast<uint32_t *>(
|
2023-01-08 21:31:00 -05:00
|
|
|
|
this->crt_.begin_data(line_buffer.pixel_count)
|
2018-10-26 19:26:46 -04:00
|
|
|
|
);
|
|
|
|
|
}
|
2018-03-02 23:08:01 -05:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if(this->pixel_target_) {
|
2018-10-26 19:26:46 -04:00
|
|
|
|
switch(line_buffer.line_mode) {
|
2023-01-09 22:34:56 -05:00
|
|
|
|
case LineMode::SMS: draw(draw_sms(relative_start, relative_end, cram_value), Clock::TMSPixel); break;
|
|
|
|
|
case LineMode::Character: draw(draw_tms_character(relative_start, relative_end), Clock::TMSPixel); break;
|
|
|
|
|
case LineMode::Text: draw(draw_tms_text(relative_start, relative_end), Clock::TMSPixel); break;
|
2017-12-02 17:48:31 -05:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
case LineMode::Refresh: break; /* Dealt with elsewhere. */
|
|
|
|
|
}
|
|
|
|
|
}
|
2017-11-30 22:19:53 -05:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
if(end == line_buffer.next_border_column) {
|
2023-01-08 21:31:00 -05:00
|
|
|
|
const int length = line_buffer.next_border_column - line_buffer.first_pixel_output_column;
|
2023-01-09 22:34:56 -05:00
|
|
|
|
this->crt_.output_data(from_internal<personality, Clock::CRT>(length), line_buffer.pixel_count);
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->pixel_origin_ = this->pixel_target_ = nullptr;
|
|
|
|
|
this->asked_for_write_area_ = false;
|
2018-10-14 16:23:45 -04:00
|
|
|
|
}
|
2018-10-26 19:26:46 -04:00
|
|
|
|
);
|
2017-12-02 17:48:31 -05:00
|
|
|
|
|
2023-01-08 17:31:08 -05:00
|
|
|
|
#undef draw
|
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// Additional right border, if called for.
|
2023-01-08 14:10:06 -05:00
|
|
|
|
if(line_buffer.next_border_column != Timing<personality>::CyclesPerLine) {
|
|
|
|
|
border(line_buffer.next_border_column, Timing<personality>::CyclesPerLine);
|
2018-10-09 20:51:09 -04:00
|
|
|
|
}
|
2018-10-04 22:50:35 -04:00
|
|
|
|
}
|
2018-10-09 20:51:09 -04:00
|
|
|
|
|
2018-10-25 23:12:03 -04:00
|
|
|
|
#undef border
|
|
|
|
|
#undef intersect
|
2018-10-04 22:50:35 -04:00
|
|
|
|
|
2023-01-08 14:10:06 -05:00
|
|
|
|
#undef crt_convert
|
|
|
|
|
#undef output_sync
|
|
|
|
|
#undef output_blank
|
|
|
|
|
#undef output_default_colour_burst
|
|
|
|
|
|
2018-10-10 21:07:39 -04:00
|
|
|
|
|
2018-10-04 22:50:35 -04:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
// -------------
|
|
|
|
|
// Advance time.
|
|
|
|
|
// -------------
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->read_pointer_.column = end_column;
|
2018-10-26 19:26:46 -04:00
|
|
|
|
}
|
2018-10-04 22:50:35 -04:00
|
|
|
|
|
2018-10-26 19:26:46 -04:00
|
|
|
|
read_cycles_pool -= target_read_cycles;
|
2023-01-06 22:39:46 -05:00
|
|
|
|
if(this->read_pointer_.column == Timing<personality>::CyclesPerLine) {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->read_pointer_.column = 0;
|
|
|
|
|
this->read_pointer_.row = (this->read_pointer_.row + 1) % this->mode_timing_.total_lines;
|
2017-11-28 21:10:30 -05:00
|
|
|
|
}
|
2017-11-27 19:43:33 -05:00
|
|
|
|
}
|
2018-10-14 18:19:11 -04:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
assert(backup.row == this->write_pointer_.row && backup.column == this->write_pointer_.column);
|
2017-11-27 19:43:33 -05:00
|
|
|
|
}
|
2017-11-26 13:28:26 -05:00
|
|
|
|
}
|
2017-11-26 16:47:59 -05:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
template <Personality personality>
|
2023-01-08 17:04:19 -05:00
|
|
|
|
void Base<personality>::output_border(int cycles, [[maybe_unused]] uint32_t cram_dot) {
|
2023-01-09 22:34:56 -05:00
|
|
|
|
cycles = from_internal<personality, Clock::CRT>(cycles);
|
2022-12-29 11:29:19 -05:00
|
|
|
|
const uint32_t border_colour =
|
2022-12-31 21:50:57 -05:00
|
|
|
|
is_sega_vdp(personality) ?
|
2018-10-26 19:26:46 -04:00
|
|
|
|
master_system_.colour_ram[16 + background_colour_] :
|
|
|
|
|
palette[background_colour_];
|
|
|
|
|
|
2023-01-08 17:04:19 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
|
|
|
|
if(cram_dot) {
|
2018-11-17 18:23:42 -05:00
|
|
|
|
uint32_t *const pixel_target = reinterpret_cast<uint32_t *>(crt_.begin_data(1));
|
|
|
|
|
if(pixel_target) {
|
2023-01-08 17:04:19 -05:00
|
|
|
|
*pixel_target = border_colour | cram_dot;
|
2018-11-17 18:23:42 -05:00
|
|
|
|
}
|
2023-01-08 17:04:19 -05:00
|
|
|
|
|
|
|
|
|
// Four CRT cycles is one pixel width, so this doesn't need clock conversion.
|
|
|
|
|
// TODO: on the Mega Drive it may be only 3 colour cycles, depending on mode.
|
|
|
|
|
crt_.output_level(4);
|
|
|
|
|
cycles -= 4;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if(!cycles) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// If the border colour is 0, that can be communicated
|
|
|
|
|
// more efficiently as an explicit blank.
|
|
|
|
|
if(border_colour) {
|
|
|
|
|
uint32_t *const pixel_target = reinterpret_cast<uint32_t *>(crt_.begin_data(1));
|
|
|
|
|
if(pixel_target) {
|
|
|
|
|
*pixel_target = border_colour;
|
2018-11-14 22:32:33 -05:00
|
|
|
|
}
|
2023-01-08 17:04:19 -05:00
|
|
|
|
crt_.output_level(cycles);
|
|
|
|
|
} else {
|
|
|
|
|
crt_.output_blank(cycles);
|
2018-10-01 23:03:17 -04:00
|
|
|
|
}
|
2017-11-27 22:05:40 -05:00
|
|
|
|
}
|
|
|
|
|
|
2022-12-31 15:08:33 -05:00
|
|
|
|
template <Personality personality>
|
|
|
|
|
void TMS9918<personality>::write(int address, uint8_t value) {
|
2017-11-26 20:01:11 -05:00
|
|
|
|
// Writes to address 0 are writes to the video RAM. Store
|
|
|
|
|
// the value and return.
|
|
|
|
|
if(!(address & 1)) {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->write_phase_ = false;
|
2017-12-13 22:37:27 -05:00
|
|
|
|
|
2018-10-01 23:03:17 -04:00
|
|
|
|
// Enqueue the write to occur at the next available slot.
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->read_ahead_buffer_ = value;
|
|
|
|
|
this->queued_access_ = MemoryAccess::Write;
|
2023-01-07 12:48:43 -05:00
|
|
|
|
this->cycles_until_access_ = Timing<personality>::VRAMAccessDelay;
|
2017-12-13 22:37:27 -05:00
|
|
|
|
|
2017-11-26 20:01:11 -05:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Writes to address 1 are performed in pairs; if this is the
|
|
|
|
|
// low byte of a value, store it and wait for the high byte.
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if(!this->write_phase_) {
|
|
|
|
|
this->low_write_ = value;
|
|
|
|
|
this->write_phase_ = true;
|
2018-10-10 21:59:08 -04:00
|
|
|
|
|
|
|
|
|
// The initial write should half update the access pointer.
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->ram_pointer_ = (this->ram_pointer_ & 0xff00) | this->low_write_;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2018-10-10 21:47:48 -04:00
|
|
|
|
// The RAM pointer is always set on a second write, regardless of
|
|
|
|
|
// whether the caller is intending to enqueue a VDP operation.
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->ram_pointer_ = (this->ram_pointer_ & 0x00ff) | uint16_t(value << 8);
|
2018-10-10 21:47:48 -04:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->write_phase_ = false;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
if(value & 0x80) {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
2018-10-26 20:19:08 -04:00
|
|
|
|
if(value & 0x40) {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->master_system_.cram_is_selected = true;
|
2018-10-26 20:19:08 -04:00
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
value &= 0xf;
|
2018-10-23 22:19:45 -04:00
|
|
|
|
} else {
|
|
|
|
|
value &= 0x7;
|
2018-09-23 15:58:23 -04:00
|
|
|
|
}
|
|
|
|
|
|
2017-11-26 20:01:11 -05:00
|
|
|
|
// This is a write to a register.
|
2018-09-23 15:58:23 -04:00
|
|
|
|
switch(value) {
|
2017-11-26 20:01:11 -05:00
|
|
|
|
case 0:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
|
|
|
|
this->master_system_.vertical_scroll_lock = this->low_write_ & 0x80;
|
|
|
|
|
this->master_system_.horizontal_scroll_lock = this->low_write_ & 0x40;
|
|
|
|
|
this->master_system_.hide_left_column = this->low_write_ & 0x20;
|
|
|
|
|
this->enable_line_interrupts_ = this->low_write_ & 0x10;
|
|
|
|
|
this->master_system_.shift_sprites_8px_left = this->low_write_ & 0x08;
|
|
|
|
|
this->master_system_.mode4_enable = this->low_write_ & 0x04;
|
2018-09-27 21:22:57 -04:00
|
|
|
|
}
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->mode2_enable_ = this->low_write_ & 0x02;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 1:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->blank_display_ = !(this->low_write_ & 0x40);
|
|
|
|
|
this->generate_interrupts_ = this->low_write_ & 0x20;
|
|
|
|
|
this->mode1_enable_ = this->low_write_ & 0x10;
|
|
|
|
|
this->mode3_enable_ = this->low_write_ & 0x08;
|
|
|
|
|
this->sprites_16x16_ = this->low_write_ & 0x02;
|
|
|
|
|
this->sprites_magnified_ = this->low_write_ & 0x01;
|
|
|
|
|
|
|
|
|
|
this->sprite_height_ = 8;
|
|
|
|
|
if(this->sprites_16x16_) this->sprite_height_ <<= 1;
|
|
|
|
|
if(this->sprites_magnified_) this->sprite_height_ <<= 1;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 2:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->pattern_name_address_ = size_t((this->low_write_ & 0xf) << 10) | 0x3ff;
|
|
|
|
|
this->master_system_.pattern_name_address = this->pattern_name_address_ | ((personality == TMS::SMSVDP) ? 0x000 : 0x400);
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 3:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->colour_table_address_ = size_t(this->low_write_ << 6) | 0x3f;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 4:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->pattern_generator_table_address_ = size_t((this->low_write_ & 0x07) << 11) | 0x7ff;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 5:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->sprite_attribute_table_address_ = size_t((this->low_write_ & 0x7f) << 7) | 0x7f;
|
|
|
|
|
this->master_system_.sprite_attribute_table_address = this->sprite_attribute_table_address_ | ((personality == TMS::SMSVDP) ? 0x00 : 0x80);
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 6:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->sprite_generator_table_address_ = size_t((this->low_write_ & 0x07) << 11) | 0x7ff;
|
|
|
|
|
this->master_system_.sprite_generator_table_address = this->sprite_generator_table_address_ | ((personality == TMS::SMSVDP) ? 0x0000 : 0x1800);
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 7:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->text_colour_ = this->low_write_ >> 4;
|
|
|
|
|
this->background_colour_ = this->low_write_ & 0xf;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
break;
|
2018-09-28 22:37:10 -04:00
|
|
|
|
|
|
|
|
|
case 8:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
|
|
|
|
this->master_system_.horizontal_scroll = this->low_write_;
|
2018-09-28 22:37:10 -04:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 9:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
|
|
|
|
this->master_system_.vertical_scroll = this->low_write_;
|
2018-09-28 22:37:10 -04:00
|
|
|
|
}
|
|
|
|
|
break;
|
2018-10-04 22:50:35 -04:00
|
|
|
|
|
|
|
|
|
case 10:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if constexpr (is_sega_vdp(personality)) {
|
|
|
|
|
this->line_interrupt_target = this->low_write_;
|
2018-10-04 22:50:35 -04:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2022-12-31 21:47:05 -05:00
|
|
|
|
LOG("Unknown TMS write: " << int(this->low_write_) << " to " << int(value));
|
2018-10-04 22:50:35 -04:00
|
|
|
|
break;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
}
|
|
|
|
|
} else {
|
2018-10-07 18:55:35 -04:00
|
|
|
|
// This is an access via the RAM pointer.
|
2017-11-26 20:01:11 -05:00
|
|
|
|
if(!(value & 0x40)) {
|
2018-10-07 18:55:35 -04:00
|
|
|
|
// A read request is enqueued upon setting the address; conversely a write
|
|
|
|
|
// won't be enqueued unless and until some actual data is supplied.
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->queued_access_ = MemoryAccess::Read;
|
2023-01-07 12:48:43 -05:00
|
|
|
|
this->cycles_until_access_ = Timing<personality>::VRAMAccessDelay;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
}
|
2022-12-31 21:47:05 -05:00
|
|
|
|
this->master_system_.cram_is_selected = false;
|
2017-11-26 20:01:11 -05:00
|
|
|
|
}
|
2017-11-26 16:47:59 -05:00
|
|
|
|
}
|
|
|
|
|
|
2022-12-31 15:08:33 -05:00
|
|
|
|
template <Personality personality>
|
2023-01-01 13:49:11 -05:00
|
|
|
|
uint8_t TMS9918<personality>::get_current_line() const {
|
2018-10-11 21:42:09 -04:00
|
|
|
|
// Determine the row to return.
|
2019-12-22 00:22:17 -05:00
|
|
|
|
constexpr int row_change_position = 63; // This is the proper Master System value; substitute if any other VDPs turn out to have this functionality.
|
2018-10-14 16:23:45 -04:00
|
|
|
|
int source_row =
|
2022-12-31 21:47:05 -05:00
|
|
|
|
(this->write_pointer_.column < row_change_position)
|
|
|
|
|
? (this->write_pointer_.row + this->mode_timing_.total_lines - 1) % this->mode_timing_.total_lines
|
|
|
|
|
: this->write_pointer_.row;
|
2018-10-11 21:42:09 -04:00
|
|
|
|
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if(this->tv_standard_ == TVStandard::NTSC) {
|
|
|
|
|
if(this->mode_timing_.pixel_lines == 240) {
|
2018-10-19 22:37:56 -04:00
|
|
|
|
// NTSC 256x240: 00-FF, 00-06
|
2022-12-31 21:47:05 -05:00
|
|
|
|
} else if(this->mode_timing_.pixel_lines == 224) {
|
2018-10-19 22:37:56 -04:00
|
|
|
|
// NTSC 256x224: 00-EA, E5-FF
|
|
|
|
|
if(source_row >= 0xeb) source_row -= 6;
|
|
|
|
|
} else {
|
|
|
|
|
// NTSC 256x192: 00-DA, D5-FF
|
|
|
|
|
if(source_row >= 0xdb) source_row -= 6;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2022-12-31 21:47:05 -05:00
|
|
|
|
if(this->mode_timing_.pixel_lines == 240) {
|
2018-10-19 22:37:56 -04:00
|
|
|
|
// PAL 256x240: 00-FF, 00-0A, D2-FF
|
|
|
|
|
if(source_row >= 267) source_row -= 0x39;
|
2022-12-31 21:47:05 -05:00
|
|
|
|
} else if(this->mode_timing_.pixel_lines == 224) {
|
2018-10-19 22:37:56 -04:00
|
|
|
|
// PAL 256x224: 00-FF, 00-02, CA-FF
|
|
|
|
|
if(source_row >= 259) source_row -= 0x39;
|
|
|
|
|
} else {
|
|
|
|
|
// PAL 256x192: 00-F2, BA-FF
|
|
|
|
|
if(source_row >= 0xf3) source_row -= 0x39;
|
|
|
|
|
}
|
|
|
|
|
}
|
2018-10-11 21:42:09 -04:00
|
|
|
|
|
2020-05-09 23:00:39 -04:00
|
|
|
|
return uint8_t(source_row);
|
2018-10-11 19:56:32 -04:00
|
|
|
|
}
|
|
|
|
|
|
2022-12-31 15:08:33 -05:00
|
|
|
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template <Personality personality>
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uint8_t TMS9918<personality>::read(int address) {
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2022-12-31 21:47:05 -05:00
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this->write_phase_ = false;
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2017-11-26 20:01:11 -05:00
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// Reads from address 0 read video RAM, via the read-ahead buffer.
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if(!(address & 1)) {
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2017-12-13 22:37:27 -05:00
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// Enqueue the write to occur at the next available slot.
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2022-12-31 21:47:05 -05:00
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const uint8_t result = this->read_ahead_buffer_;
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this->queued_access_ = MemoryAccess::Read;
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2017-11-26 20:01:11 -05:00
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return result;
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}
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2017-12-02 22:13:43 -05:00
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// Reads from address 1 get the status register.
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2022-12-31 21:47:05 -05:00
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const uint8_t result = this->status_;
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this->status_ &= ~(StatusInterrupt | StatusSpriteOverflow | StatusSpriteCollision);
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this->line_interrupt_pending_ = false;
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2017-11-26 20:01:11 -05:00
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return result;
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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2023-01-01 13:49:11 -05:00
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HalfCycles TMS9918<personality>::get_next_sequence_point() const {
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2022-12-31 21:47:05 -05:00
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if(!this->generate_interrupts_ && !this->enable_line_interrupts_) return HalfCycles::max();
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2021-04-05 21:02:37 -04:00
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if(get_interrupt_line()) return HalfCycles::max();
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2017-11-29 20:31:55 -05:00
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2018-10-04 22:50:35 -04:00
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// Calculate the amount of time until the next end-of-frame interrupt.
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2023-01-07 09:13:34 -05:00
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const int frame_length = Timing<personality>::CyclesPerLine * this->mode_timing_.total_lines;
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2018-10-21 18:42:49 -04:00
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int time_until_frame_interrupt =
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2018-10-10 21:07:39 -04:00
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(
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2023-01-07 09:13:34 -05:00
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((this->mode_timing_.end_of_frame_interrupt_position.row * Timing<personality>::CyclesPerLine) + this->mode_timing_.end_of_frame_interrupt_position.column + frame_length) -
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((this->write_pointer_.row * Timing<personality>::CyclesPerLine) + this->write_pointer_.column)
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2018-10-10 21:07:39 -04:00
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) % frame_length;
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2018-10-21 18:42:49 -04:00
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if(!time_until_frame_interrupt) time_until_frame_interrupt = frame_length;
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2018-10-10 21:07:39 -04:00
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2023-01-08 21:25:22 -05:00
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if(!this->enable_line_interrupts_) {
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return this->clock_converter_.half_cycles_before_internal_cycles(time_until_frame_interrupt);
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}
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2018-10-09 20:51:09 -04:00
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2018-10-21 18:42:49 -04:00
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// Calculate when the next line interrupt will occur.
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2018-10-09 20:51:09 -04:00
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int next_line_interrupt_row = -1;
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2018-10-04 22:50:35 -04:00
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2022-12-31 21:47:05 -05:00
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int cycles_to_next_interrupt_threshold = this->mode_timing_.line_interrupt_position - this->write_pointer_.column;
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int line_of_next_interrupt_threshold = this->write_pointer_.row;
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2018-10-21 18:42:49 -04:00
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if(cycles_to_next_interrupt_threshold <= 0) {
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2023-01-07 09:13:34 -05:00
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cycles_to_next_interrupt_threshold += Timing<personality>::CyclesPerLine;
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2018-10-21 18:42:49 -04:00
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++line_of_next_interrupt_threshold;
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}
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2022-12-31 21:47:05 -05:00
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if constexpr (is_sega_vdp(personality)) {
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2018-10-09 20:51:09 -04:00
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// If there is still time for a line interrupt this frame, that'll be it;
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// otherwise it'll be on the next frame, supposing there's ever time for
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// it at all.
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2022-12-31 21:47:05 -05:00
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if(line_of_next_interrupt_threshold + this->line_interrupt_counter <= this->mode_timing_.pixel_lines) {
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next_line_interrupt_row = line_of_next_interrupt_threshold + this->line_interrupt_counter;
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2018-10-09 20:51:09 -04:00
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} else {
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2022-12-31 21:47:05 -05:00
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if(this->line_interrupt_target <= this->mode_timing_.pixel_lines)
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next_line_interrupt_row = this->mode_timing_.total_lines + this->line_interrupt_target;
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2018-10-09 20:51:09 -04:00
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}
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2018-10-04 22:50:35 -04:00
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}
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2018-10-09 20:51:09 -04:00
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// If there's actually no interrupt upcoming, despite being enabled, either return
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// the frame end interrupt or no interrupt pending as appropriate.
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if(next_line_interrupt_row == -1) {
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2022-12-31 21:47:05 -05:00
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return this->generate_interrupts_ ?
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2023-01-01 14:20:45 -05:00
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this->clock_converter_.half_cycles_before_internal_cycles(time_until_frame_interrupt) :
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2021-06-04 22:38:07 -04:00
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HalfCycles::max();
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2018-10-04 22:50:35 -04:00
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}
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2018-10-09 22:14:35 -04:00
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// Figure out the number of internal cycles until the next line interrupt, which is the amount
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// of time to the next tick over and then next_line_interrupt_row - row_ lines further.
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2023-01-07 09:13:34 -05:00
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const int local_cycles_until_line_interrupt = cycles_to_next_interrupt_threshold + (next_line_interrupt_row - line_of_next_interrupt_threshold) * Timing<personality>::CyclesPerLine;
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2023-01-01 14:20:45 -05:00
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if(!this->generate_interrupts_) return this->clock_converter_.half_cycles_before_internal_cycles(local_cycles_until_line_interrupt);
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2018-10-04 22:50:35 -04:00
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2018-10-09 20:51:09 -04:00
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// Return whichever interrupt is closer.
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2023-01-01 14:20:45 -05:00
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return this->clock_converter_.half_cycles_before_internal_cycles(std::min(local_cycles_until_line_interrupt, time_until_frame_interrupt));
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2017-11-29 20:31:55 -05:00
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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HalfCycles TMS9918<personality>::get_time_until_line(int line) {
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2022-12-31 21:47:05 -05:00
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if(line < 0) line += this->mode_timing_.total_lines;
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2018-10-24 21:59:30 -04:00
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2022-12-31 21:47:05 -05:00
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int cycles_to_next_interrupt_threshold = this->mode_timing_.line_interrupt_position - this->write_pointer_.column;
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int line_of_next_interrupt_threshold = this->write_pointer_.row;
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2018-10-24 21:59:30 -04:00
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if(cycles_to_next_interrupt_threshold <= 0) {
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2023-01-07 09:13:34 -05:00
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cycles_to_next_interrupt_threshold += Timing<personality>::CyclesPerLine;
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2018-10-24 21:59:30 -04:00
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++line_of_next_interrupt_threshold;
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}
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if(line_of_next_interrupt_threshold > line) {
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2022-12-31 21:47:05 -05:00
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line += this->mode_timing_.total_lines;
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2018-10-24 21:59:30 -04:00
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}
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2023-01-07 09:13:34 -05:00
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return this->clock_converter_.half_cycles_before_internal_cycles(cycles_to_next_interrupt_threshold + (line - line_of_next_interrupt_threshold)*Timing<personality>::CyclesPerLine);
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2018-10-24 21:59:30 -04:00
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}
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2022-12-31 15:08:33 -05:00
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template <Personality personality>
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2023-01-01 13:49:11 -05:00
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bool TMS9918<personality>::get_interrupt_line() const {
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2022-12-31 21:47:05 -05:00
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return
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((this->status_ & StatusInterrupt) && this->generate_interrupts_) ||
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(this->enable_line_interrupts_ && this->line_interrupt_pending_);
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2017-11-29 20:31:55 -05:00
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}
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2018-10-02 21:05:30 -04:00
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2023-01-05 13:18:10 -05:00
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// TODO: [potentially] remove Master System timing assumptions in latch and get_latched below.
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2023-01-07 09:10:41 -05:00
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template <Personality personality>uint8_t TMS9918<personality>::get_latched_horizontal_counter() const {
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2023-01-05 13:18:10 -05:00
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// Translate from internal numbering, which puts pixel output
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// in the final 256 pixels of 342, to the public numbering,
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2023-01-07 09:10:41 -05:00
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// which counts the 256 pixels as items 0–255, starts
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2023-01-05 13:18:10 -05:00
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// counting at -48, and returns only the top 8 bits of the number.
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2023-01-07 09:10:41 -05:00
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int public_counter = this->latched_column_ - (342 - 256);
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2023-01-05 13:18:10 -05:00
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if(public_counter < -46) public_counter += 342;
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return uint8_t(public_counter >> 1);
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2018-10-02 21:05:30 -04:00
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}
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2022-12-31 21:47:05 -05:00
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template <Personality personality>
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2023-01-05 13:18:10 -05:00
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void TMS9918<personality>::latch_horizontal_counter() {
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this->latched_column_ = this->write_pointer_.column;
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2018-10-02 21:05:30 -04:00
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}
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2022-12-31 15:08:33 -05:00
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template class TI::TMS::TMS9918<Personality::TMS9918A>;
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template class TI::TMS::TMS9918<Personality::V9938>;
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template class TI::TMS::TMS9918<Personality::V9958>;
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template class TI::TMS::TMS9918<Personality::SMSVDP>;
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template class TI::TMS::TMS9918<Personality::SMS2VDP>;
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template class TI::TMS::TMS9918<Personality::GGVDP>;
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template class TI::TMS::TMS9918<Personality::MDVDP>;
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