2019-03-10 21:27:34 +00:00
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//
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// 68000Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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2019-03-10 22:40:12 +00:00
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template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::run_for(HalfCycles duration) {
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2019-03-10 21:42:13 +00:00
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// TODO: obey the 'cycles' count.
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while(true) {
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2019-03-17 02:36:09 +00:00
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/*
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PERFORM THE CURRENT BUS STEP'S MICROCYCLE.
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*/
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// Check for DTack if this isn't being treated implicitly.
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if(!dtack_is_implicit) {
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if(active_step_->microcycle.data_select_active() && !dtack_) {
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// TODO: perform wait state.
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continue;
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}
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}
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// TODO: synchronous bus.
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2019-03-17 02:50:26 +00:00
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// TODO: check for bus error.
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2019-03-17 02:36:09 +00:00
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// Perform the microcycle.
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bus_handler_.perform_bus_operation(active_step_->microcycle, is_supervisor_);
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/*
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PERFORM THE BUS STEP'S ACTION.
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*/
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2019-03-17 03:01:56 +00:00
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if(!active_step_->is_terminal()) {
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switch(active_step_->action) {
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default:
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std::cerr << "Unimplemented 68000 bus step action: " << int(active_step_->action) << std::endl;
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return;
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break;
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case BusStep::Action::None: break;
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2019-03-19 02:51:32 +00:00
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case BusStep::Action::IncrementEffectiveAddress0: effective_address_[0] += 2; break;
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case BusStep::Action::IncrementEffectiveAddress1: effective_address_[1] += 2; break;
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2019-03-17 03:01:56 +00:00
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case BusStep::Action::IncrementProgramCounter: program_counter_.full += 2; break;
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case BusStep::Action::AdvancePrefetch:
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2019-03-20 01:33:52 +00:00
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prefetch_queue_.halves.high = prefetch_queue_.halves.low;
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2019-03-17 03:01:56 +00:00
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break;
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2019-03-17 02:50:26 +00:00
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}
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2019-03-17 03:01:56 +00:00
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// Move to the next bus step.
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++ active_step_;
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// Skip the micro-op renavigation below.
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continue;
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}
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/*
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FIND THE NEXT MICRO-OP.
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*/
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while(true) {
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// If there are any more micro-operations available, just move onwards.
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if(active_micro_op_ && !active_micro_op_->is_terminal()) {
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++active_micro_op_;
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} else {
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2019-03-17 02:36:09 +00:00
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// Either the micro-operations for this instruction have been exhausted, or
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// no instruction was ongoing. Either way, do a standard instruction operation.
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// TODO: unless an interrupt is pending, or the trap flag is set.
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2019-03-20 01:33:52 +00:00
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const uint16_t next_instruction = prefetch_queue_.halves.high;
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2019-03-17 02:36:09 +00:00
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if(!instructions[next_instruction].micro_operations) {
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2019-03-17 03:05:12 +00:00
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// TODO: once all instructions are implemnted, this should be an instruction error.
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std::cerr << "68000 Abilities exhausted; can't manage instruction " << std::hex << next_instruction << std::endl;
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2019-03-17 02:36:09 +00:00
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return;
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}
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active_program_ = &instructions[next_instruction];
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active_micro_op_ = active_program_->micro_operations;
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}
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2019-03-13 02:46:31 +00:00
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switch(active_micro_op_->action) {
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2019-03-19 02:51:32 +00:00
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default:
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std::cerr << "Unhandled 68000 micro op action " << std::hex << active_micro_op_->action << std::endl;
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break;
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2019-03-13 02:46:31 +00:00
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case MicroOp::Action::None: break;
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case MicroOp::Action::PerformOperation:
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2019-03-14 23:32:15 +00:00
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switch(active_program_->operation) {
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case Operation::ABCD: {
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// Pull out the two halves, for simplicity.
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const uint8_t source = active_program_->source->halves.low.halves.low;
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const uint8_t destination = active_program_->destination->halves.low.halves.low;
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// Perform the BCD add by evaluating the two nibbles separately.
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2019-03-15 01:22:02 +00:00
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int result = (destination & 0xf) + (source & 0xf) + (extend_flag_ ? 1 : 0);
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2019-03-18 02:04:32 +00:00
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if(result > 0x09) result += 0x06;
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2019-03-15 01:22:02 +00:00
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result += (destination & 0xf0) + (source & 0xf0);
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2019-03-18 02:04:32 +00:00
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if(result > 0x99) result += 0x60;
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2019-03-14 23:32:15 +00:00
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// Set all flags essentially as if this were normal addition.
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zero_flag_ |= result & 0xff;
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extend_flag_ = carry_flag_ = result & ~0xff;
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negative_flag_ = result & 0x80;
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2019-03-15 01:22:02 +00:00
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overflow_flag_ = ~(source ^ destination) & (destination ^ result) & 0x80;
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// Store the result.
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active_program_->destination->halves.low.halves.low = uint8_t(result);
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} break;
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case Operation::SBCD: {
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// Pull out the two halves, for simplicity.
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const uint8_t source = active_program_->source->halves.low.halves.low;
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const uint8_t destination = active_program_->destination->halves.low.halves.low;
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// Perform the BCD add by evaluating the two nibbles separately.
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int result = (destination & 0xf) - (source & 0xf) - (extend_flag_ ? 1 : 0);
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2019-03-18 02:04:32 +00:00
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if(result > 0x09) result -= 0x06;
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2019-03-15 01:22:02 +00:00
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result += (destination & 0xf0) - (source & 0xf0);
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2019-03-18 02:04:32 +00:00
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if(result > 0x99) result -= 0x60;
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2019-03-15 01:22:02 +00:00
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2019-03-16 21:54:58 +00:00
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// Set all flags essentially as if this were normal subtraction.
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2019-03-15 01:22:02 +00:00
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zero_flag_ |= result & 0xff;
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extend_flag_ = carry_flag_ = result & ~0xff;
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negative_flag_ = result & 0x80;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80;
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2019-03-14 23:32:15 +00:00
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// Store the result.
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active_program_->destination->halves.low.halves.low = uint8_t(result);
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} break;
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2019-03-16 21:54:58 +00:00
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case Operation::MOVEb:
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zero_flag_ = active_program_->destination->halves.low.halves.low = active_program_->source->halves.low.halves.low;
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negative_flag_ = zero_flag_ & 0x80;
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break;
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case Operation::MOVEw:
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zero_flag_ = active_program_->destination->halves.low.full = active_program_->source->halves.low.full;
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negative_flag_ = zero_flag_ & 0x8000;
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break;
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case Operation::MOVEl:
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zero_flag_ = active_program_->destination->full = active_program_->source->full;
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negative_flag_ = zero_flag_ & 0x80000000;
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break;
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2019-03-14 23:32:15 +00:00
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default:
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std::cerr << "Should do something with program operation " << int(active_program_->operation) << std::endl;
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break;
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}
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2019-03-13 02:46:31 +00:00
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break;
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2019-03-14 01:08:13 +00:00
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2019-03-19 02:51:32 +00:00
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case MicroOp::Action::Decrement1:
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if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full -= 1;
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if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full -= 1;
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break;
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case MicroOp::Action::Decrement2:
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if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full -= 2;
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if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full -= 2;
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break;
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case MicroOp::Action::Decrement4:
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if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full -= 4;
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if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full -= 4;
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break;
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case MicroOp::Action::Increment1:
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if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full += 1;
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if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full += 1;
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break;
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case MicroOp::Action::Increment2:
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if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full += 2;
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if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full += 2;
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break;
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case MicroOp::Action::Increment4:
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if(active_micro_op_->action & MicroOp::SourceMask) active_program_->source->full += 4;
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if(active_micro_op_->action & MicroOp::DestinationMask) active_program_->destination->full += 4;
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break;
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case MicroOp::Action::SignExtendWord:
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if(active_micro_op_->action & MicroOp::SourceMask) {
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active_program_->source->halves.high.full =
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(active_program_->source->halves.low.full & 0x8000) ? 0xffff : 0x0000;
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}
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if(active_micro_op_->action & MicroOp::DestinationMask) {
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active_program_->destination->halves.high.full =
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(active_program_->destination->halves.low.full & 0x8000) ? 0xffff : 0x0000;
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}
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break;
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case MicroOp::Action::SignExtendByte:
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if(active_micro_op_->action & MicroOp::SourceMask) {
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active_program_->source->full = (active_program_->source->full & 0xff) |
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(active_program_->source->full & 0x80) ? 0xffffff : 0x000000;
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}
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if(active_micro_op_->action & MicroOp::DestinationMask) {
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active_program_->destination->full = (active_program_->destination->full & 0xff) |
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(active_program_->destination->full & 0x80) ? 0xffffff : 0x000000;
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}
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2019-03-14 01:08:13 +00:00
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break;
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2019-03-19 02:51:32 +00:00
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case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask:
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2019-03-20 01:33:52 +00:00
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effective_address_[0] = int16_t(prefetch_queue_.halves.high) + active_program_->source->full;
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2019-03-14 01:08:13 +00:00
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break;
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2019-03-19 02:51:32 +00:00
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case int(MicroOp::Action::CalcD16An) | MicroOp::DestinationMask:
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2019-03-20 01:33:52 +00:00
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effective_address_[1] = int16_t(prefetch_queue_.halves.high) + active_program_->destination->full;
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2019-03-14 01:08:13 +00:00
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break;
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2019-03-17 18:34:16 +00:00
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2019-03-19 02:51:32 +00:00
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case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask | MicroOp::DestinationMask:
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2019-03-20 01:33:52 +00:00
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effective_address_[0] = int16_t(prefetch_queue_.halves.high) + active_program_->source->full;
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effective_address_[1] = int16_t(prefetch_queue_.halves.low) + active_program_->destination->full;
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2019-03-17 18:34:16 +00:00
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break;
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2019-03-19 02:51:32 +00:00
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// TODO: permit as below for DestinationMask and SourceMask|DestinationMask; would prefer to test first.
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#define CalculateD8AnXn(data, source, target) {\
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const auto register_index = (data.full >> 12) & 7; \
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const RegisterPair32 &displacement = (data.full & 0x8000) ? address_[register_index] : data_[register_index]; \
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target = int8_t(data.halves.low) + source->full; \
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\
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if(data.full & 0x800) { \
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effective_address_[0] += displacement.halves.low; \
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} else { \
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effective_address_[0] += displacement.full; \
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} \
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}
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case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask: {
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2019-03-20 01:33:52 +00:00
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CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->source, effective_address_[0]);
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2019-03-19 02:51:32 +00:00
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} break;
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case int(MicroOp::Action::CalcD8AnXn) | MicroOp::DestinationMask: {
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2019-03-20 01:33:52 +00:00
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CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->destination, effective_address_[1]);
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2019-03-19 02:51:32 +00:00
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} break;
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case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
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2019-03-20 01:33:52 +00:00
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CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->source, effective_address_[0]);
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CalculateD8AnXn(prefetch_queue_.halves.low, active_program_->destination, effective_address_[1]);
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2019-03-19 02:51:32 +00:00
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} break;
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#undef CalculateD8AnXn
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2019-03-19 15:53:37 +00:00
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case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask:
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2019-03-20 01:33:52 +00:00
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bus_data_[0] = prefetch_queue_.full;
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2019-03-19 15:53:37 +00:00
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break;
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case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::DestinationMask:
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2019-03-20 01:33:52 +00:00
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bus_data_[1] = prefetch_queue_.full;
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2019-03-19 15:53:37 +00:00
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break;
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2019-03-13 02:46:31 +00:00
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}
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2019-03-17 03:01:56 +00:00
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// If we've got to a micro-op that includes bus steps, break out of this loop.
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if(!active_micro_op_->is_terminal()) {
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active_step_ = active_micro_op_->bus_program;
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2019-03-17 02:36:09 +00:00
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break;
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}
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2019-03-10 21:42:13 +00:00
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}
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}
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2019-03-10 21:27:34 +00:00
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}
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2019-03-18 01:57:00 +00:00
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template <class T, bool dtack_is_implicit> ProcessorState Processor<T, dtack_is_implicit>::get_state() {
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write_back_stack_pointer();
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State state;
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memcpy(state.data, data_, sizeof(state.data));
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memcpy(state.address, address_, sizeof(state.address));
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state.user_stack_pointer = stack_pointers_[0].full;
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state.supervisor_stack_pointer = stack_pointers_[1].full;
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// TODO: status word.
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return state;
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}
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template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::set_state(const ProcessorState &state) {
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memcpy(data_, state.data, sizeof(state.data));
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memcpy(address_, state.address, sizeof(state.address));
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stack_pointers_[0].full = state.user_stack_pointer;
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stack_pointers_[1].full = state.supervisor_stack_pointer;
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// TODO: update address[7], once there's a status word to discern the mode this processor should now be in.
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}
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