Thomas Harte
ec0018df79
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 16:59:49 -05:00
Thomas Harte
12784a71e2
A stab in the dark: does the IOLC inhibit also affect vector fetches?
2020-12-29 20:53:56 -05:00
Thomas Harte
114d48b076
This register appears to be read/write.
2020-12-11 21:43:34 -05:00
Thomas Harte
049a78c667
Slightly restricts video flushing test.
2020-12-08 18:47:15 -05:00
Thomas Harte
65ca931e83
Throws in a new assert, against the unimplemented bit 0 of new video.
2020-12-06 20:26:24 -05:00
Thomas Harte
6273ef8ba2
Adds means to force specific ROM 03 self tests.
2020-12-02 20:48:19 -05:00
Thomas Harte
24fcb0c24b
Corrects video counter values.
...
The built-in speed test now passes.
2020-12-01 18:35:55 -05:00
Thomas Harte
03e2b6a265
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 17:46:30 -05:00
Thomas Harte
ee22cf7ca1
Ensures that PAGE2 propagates from the state register to video.
2020-11-30 22:56:19 -05:00
Thomas Harte
187f507532
The soft switch is LCBANK2, not LCBANK1.
...
[This also jimmys the IIgs into always entering its extended self test, for now]
2020-11-30 22:35:51 -05:00
Thomas Harte
6000bd3a5e
Adds a bonus debugging assert. Let's see.
2020-11-30 18:15:02 -05:00
Thomas Harte
35aa7612bb
Ensures that auxiliary/language-card soft switches don't trigger my assert.
2020-11-29 21:32:24 -05:00
Thomas Harte
acaa841822
Adds guaranteed trip to ROM for vector pulls.
2020-11-29 21:29:15 -05:00
Thomas Harte
4bdbca64b2
Takes a shot at the Mega II-style video interrupts.
2020-11-29 21:21:46 -05:00
Thomas Harte
11fe8ab6db
Corrects counter scales, adds a read for $c032.
...
Albeit that I have no idea what that's supposed to read as.
2020-11-29 20:08:59 -05:00
Thomas Harte
a9ce43d244
Takes a shot at the two video counter registers.
2020-11-29 19:57:35 -05:00
Thomas Harte
af667c718e
Gets a bit more rigorous in remaining missing parts.
2020-11-26 22:36:32 -05:00
Thomas Harte
f4d13d1f6f
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 17:14:46 -05:00
Thomas Harte
8093f67173
Ensures video interrupts can't be missed by a suitably-timed access.
2020-11-26 16:11:03 -05:00
Thomas Harte
fdd102df52
Resolves border colour resets.
2020-11-26 13:13:48 -05:00
Thomas Harte
03a893dc74
Quick refactor: this clearly isn't a VideoBase, it's the full implementation.
2020-11-26 12:54:20 -05:00
Thomas Harte
cdc2311045
Enables fuzzing, adds a definite no-op write.
2020-11-25 23:33:55 -05:00
Thomas Harte
3cba3a5ac0
Corrects card mask test outside of bank $00.
2020-11-21 22:22:27 -05:00
Thomas Harte
4a42de4f18
Attempts to add 5.25" drive support to the IIgs.
...
I want to try some classic software.
2020-11-20 21:37:17 -05:00
Thomas Harte
1d288b08b6
Attempts the two most basic forms of DOC output.
...
Sans interrupts. Or register reads of any variety.
2020-11-19 21:19:27 -05:00
Thomas Harte
34794223b4
For now, at least, c800–cfff is always built-in ROM.
...
Otherwise I probably need to extend my c3 logic to cover the other built-in cards (?)
2020-11-18 19:49:45 -05:00
Thomas Harte
98347cb1c3
Starts in the direction of audio support.
2020-11-18 18:39:11 -05:00
Thomas Harte
bb80e53021
Reduces frequency of video flushes.
2020-11-16 21:55:41 -05:00
Thomas Harte
6dfad6a44b
Slightly reduces logging.
...
Hopefully soon I can tear the whole lot out.
2020-11-16 21:46:19 -05:00
Thomas Harte
9206ab5dc3
Adds notes to self; implements get_next_sequence_point for video, allowing per-line interrupts.
2020-11-16 14:42:50 -05:00
Thomas Harte
7e39550fc0
Attempts to make JustInTimeActor sequence-point aware.
...
With the objective of chopping out a lot of future boilerplate.
2020-11-15 21:58:18 -05:00
Thomas Harte
cdacf280e1
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 16:08:29 -05:00
Thomas Harte
1538a02e18
Better explains concern.
2020-11-14 19:27:20 -05:00
Thomas Harte
f9cec9a102
Attempts also to implement 1Mhz access costs.
...
Subject to TODO, and same observation as before: this is as to my current understanding only.
2020-11-14 19:23:01 -05:00
Thomas Harte
adda3d8f42
Attempts a 'full' model of 2.8Mhz access timing.
...
i.e. full to my current understanding.
2020-11-14 19:10:41 -05:00
Thomas Harte
ec3ff0da12
Steps towards proper calculation of time.
2020-11-14 18:39:16 -05:00
Thomas Harte
73c38b3b0d
Collapses nested conditionals.
2020-11-14 18:23:31 -05:00
Thomas Harte
edc8050b36
Adds activity indicators.
2020-11-14 18:00:06 -05:00
Thomas Harte
715a1b9cd6
Ensures safe shutdown.
2020-11-12 21:44:51 -05:00
Thomas Harte
86310849eb
Corrects IWM clocking.
2020-11-12 18:09:31 -05:00
Thomas Harte
a2a928e262
Takes a guess at the format of IIgs .po files; wires them through to the actual machine.
...
... which still declines to boot.
2020-11-12 18:01:26 -05:00
Thomas Harte
3813e00ca3
Adds the Apple II toggle speaker.
2020-11-11 21:04:38 -05:00
Thomas Harte
a15af1df5e
Attempts to use the other bit of disk drive control, the 5.25"/3.5" select.
...
For the record, the ROM thinks it finds some Smartport devices and then attempts to talk to them. Since none is present, it blocks forever.
2020-11-11 17:55:50 -05:00
Thomas Harte
8024bbd721
Provides minor extra detail.
2020-11-11 17:08:56 -05:00
Thomas Harte
ece9382a4e
Also attaches IWM select line.
2020-11-10 18:59:23 -05:00
Thomas Harte
20fd5adb24
Makes a first effort at attaching an IWM.
2020-11-10 18:38:23 -05:00
Thomas Harte
abb350ff5b
Stubs in audio toggle and disk control.
...
It appears that ROM 01 now fails because reading the disk interface register doesn't do as expected. ROM 03 starts hitting what should be the IWM and dies in a surplus of logging.
2020-11-09 22:21:52 -05:00
Thomas Harte
54352cb1cb
Stubs in a couple more registers.
...
PC now hits $0000. Likely a bug.
2020-11-09 21:54:25 -05:00
Thomas Harte
0ae49b356a
Seems to do enough padding out to get me to my second failing ADB command.
...
That's better than failing at the first.
2020-11-09 19:05:48 -05:00
Thomas Harte
287bfeb924
Hacks in 40-column text.
...
Hot gossip: my IIgs is reporting a system error. A clue!
2020-11-08 17:01:23 -05:00
