95 Commits

Author	SHA1	Message	Date
Thomas Harte	0e17f382a1	Capture further detail.	2024-03-27 22:36:03 -04:00
Thomas Harte	72a645ec1e	Fix trans; take further crack at MEMC permissions.	2024-03-25 15:50:59 -04:00
Thomas Harte	521fca6089	Expose full bus to IOC dependents; add notes.	2024-03-25 11:07:44 -04:00
Thomas Harte	55f92e2411	Adjust data abort address.	2024-03-23 20:31:47 -04:00
Thomas Harte	9ea3e547ee	Fix IRQ/FIQ return addresses.	2024-03-22 21:42:34 -04:00
Thomas Harte	ae6cf69449	Move responsibility for clock division; reinstate vsync interrupt.	2024-03-22 10:01:34 -04:00
Thomas Harte	85a738acff	Get rigorous on exception addresses.	2024-03-19 15:03:31 -04:00
Thomas Harte	9d084782ae	Document.	2024-03-19 12:22:19 -04:00
Thomas Harte	106937b679	Run into the shifts wall with LDR/STR.	2024-03-19 12:19:49 -04:00
Thomas Harte	623eda7162	Output branches and nops correctly.	2024-03-19 11:42:41 -04:00
Thomas Harte	2ad6bb099b	Begin foray into disassembly.	2024-03-19 11:34:10 -04:00
Thomas Harte	9d858bc61b	IRQ and FIQ should also store PC+4.	2024-03-18 14:08:08 -04:00
Thomas Harte	1c1d2891c7	Adjust IRQ/FIQ return addresses.	2024-03-15 21:59:38 -04:00
Thomas Harte	1979d2e5ba	Don't set interrupt flags before capture.	2024-03-15 21:34:39 -04:00
Thomas Harte	c25d0e8843	Correctly capture mode upon exception.	2024-03-15 18:39:56 -04:00
Thomas Harte	bc27e3998d	Fix downward block data transfers.	2024-03-14 21:09:51 -04:00
Thomas Harte	4987bdfec9	Throw less.	2024-03-14 10:43:51 -04:00
Thomas Harte	5d6bb11eb7	Add return.	2024-03-12 11:37:15 -04:00
Thomas Harte	c6b91559e1	Attempt to wire up timer interrupts.	2024-03-12 11:34:31 -04:00
Thomas Harte	6efc41ded7	Come to conclusion on R15; fix link values.	2024-03-12 10:42:09 -04:00
Thomas Harte	e9c5582fe1	Add note on ambiguity to be resolved.	2024-03-12 10:04:02 -04:00
Thomas Harte	8b3c0abe93	Take another swing at R15 as a destination.	2024-03-12 09:13:05 -04:00
Thomas Harte	971bfb2ecb	Unify subtractions.	2024-03-11 14:52:48 -04:00
Thomas Harte	e8c1e8fd3f	Fix RSB carry; unify set_pc.	2024-03-11 14:48:43 -04:00
Thomas Harte	830d70d3aa	Trust tests on immediate-opcode ROR 0; limit shift by register.	2024-03-10 23:38:31 -04:00
Thomas Harte	336292bc49	Further correct R15 as a destination.	2024-03-10 22:56:02 -04:00
Thomas Harte	bd62228cc6	The test set doesn't seem to do word rotation.	2024-03-10 22:40:37 -04:00
Thomas Harte	e9e1db7a05	Change LDR writeback to destination.	2024-03-10 22:29:19 -04:00
Thomas Harte	fbc273f114	Add invented model for tests.	2024-03-10 21:45:56 -04:00
Thomas Harte	a4cf86268e	Provide full access to stored registers.	2024-03-09 15:11:04 -05:00
Thomas Harte	d059e7c5d8	Disallow copying.	2024-03-09 15:10:55 -05:00
Thomas Harte	fdef8901ab	Double down on uint32_t.	2024-03-08 14:13:34 -05:00
Thomas Harte	ca1c3dc005	Add extra comments. ... To persuade myself in the future.	2024-03-08 11:36:17 -05:00
Thomas Harte	fa8fcd2218	Take another swing at popcount.	2024-03-07 14:28:31 -05:00
Thomas Harte	2a36d0fcbc	Adjust user-mode test.	2024-03-07 14:00:38 -05:00
Thomas Harte	0e92885ed5	Fix ad hoc popcount; ARM does carry 'backwards'.	2024-03-07 13:27:41 -05:00
Thomas Harte	f5225b69e5	Add note to self.	2024-03-07 11:48:44 -05:00
Thomas Harte	15ee84b2eb	Fix MUL ambiguity.	2024-03-07 11:45:39 -05:00
Thomas Harte	a0f0f73bde	Fix MOV as unconditional branch.	2024-03-07 10:31:26 -05:00
Thomas Harte	108a056f1c	Execution now runs into a prefetch abort loop.	2024-03-06 15:05:24 -05:00
Thomas Harte	fe467be124	Further stick to existing type.	2024-03-05 10:56:09 -05:00
Thomas Harte	ba5f142515	Take further stab at TEQ PC, etc.	2024-03-05 10:55:44 -05:00
Thomas Harte	ed586e80bc	Don't write to the PC with logical operations.	2024-03-05 09:32:35 -05:00
Thomas Harte	871c5467d7	Avoid sign change.	2024-03-05 09:31:42 -05:00
Thomas Harte	1b7c3644f4	Eliinate meaningless 'const'.	2024-03-04 14:09:27 -05:00
Thomas Harte	0cdca12e06	Resolve type mismatches.	2024-03-04 13:53:46 -05:00
Thomas Harte	61d4c69e45	Fix template parameter reference.	2024-03-04 13:25:40 -05:00
Thomas Harte	79865e295b	Avoid ambiguous template parameter; use standard type.	2024-03-04 12:20:40 -05:00
Thomas Harte	230e9c6327	Obscure active.	2024-03-03 21:43:30 -05:00
Thomas Harte	11c4d2f09e	Add further exposition.	2024-03-03 21:38:27 -05:00