Thomas Harte
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63ee8c9d58
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Uses file containers' type distinguishers where available, and supplies potential insight to the ZX80/81 analyser as now required.
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2017-08-27 15:20:58 -04:00 |
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Thomas Harte
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437023bff6
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Expands to take an already-accrued list of potential platforms, as that may indicate that one or the other of the ZX80 and ZX81 is already out of contention and therefore save the need to attempt analysis.
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2017-08-27 15:20:22 -04:00 |
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Thomas Harte
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4465098157
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Since it has descendants, gives Storage::Cartridge a virtual destructor.
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2017-08-27 15:19:30 -04:00 |
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Thomas Harte
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56dd677e9c
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Creates a virtual interface that can be adopted by classes that are able to provide some insight as to target machine.
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2017-08-27 15:19:03 -04:00 |
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Thomas Harte
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9aa150c338
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Abstracts the target platform type out from the static analyser's ownership.
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2017-08-27 15:02:13 -04:00 |
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Thomas Harte
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fab6908129
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Corrects the all-RAM Z80 to declare that it needs the wait line to be implemented.
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2017-08-26 23:18:11 -04:00 |
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Thomas Harte
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e34d4ce903
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Merge pull request #224 from TomHarte/OptionalWait
Makes the Z80's support for WAIT input optional
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2017-08-26 23:16:22 -04:00 |
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Thomas Harte
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d411827733
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Merge branch 'master' into OptionalWait
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2017-08-26 23:11:23 -04:00 |
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Thomas Harte
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f1ba7755dd
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Merge pull request #223 from TomHarte/cpctest
Moves test for 6845 horizontal sync timing into the time after phase 1 and before phase 2
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2017-08-26 23:11:03 -04:00 |
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Thomas Harte
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57bfec285f
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Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
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2017-08-26 23:08:57 -04:00 |
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Thomas Harte
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bdda701207
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Reverts previous unevidenced change.
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2017-08-26 22:58:16 -04:00 |
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Thomas Harte
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487fe83dca
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Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
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2017-08-26 17:54:54 -04:00 |
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Thomas Harte
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6c5a03187b
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Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
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2017-08-26 17:22:48 -04:00 |
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Thomas Harte
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97f57a3948
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Merge pull request #222 from TomHarte/6845GetState
Refines observable 6845 behaviour
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2017-08-26 14:46:29 -04:00 |
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Thomas Harte
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7d7aa2f5d5
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Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
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2017-08-26 14:37:03 -04:00 |
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Thomas Harte
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e7ad79c79a
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Breaks apart the CPC's 6845 bus handler to obey phase 1 and phase 2, and now back-dates interrupts when appropriate.
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2017-08-26 14:07:51 -04:00 |
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Thomas Harte
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28550c0227
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Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
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2017-08-26 13:56:23 -04:00 |
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Thomas Harte
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6e99169348
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Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
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2017-08-26 12:59:59 -04:00 |
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Thomas Harte
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1017bb9f6b
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Merge pull request #221 from TomHarte/6845UpCount
Regularises the 6845 sync counters
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2017-08-26 12:51:39 -04:00 |
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Thomas Harte
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3caa4705ca
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Limits sync counter size.
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2017-08-26 12:31:19 -04:00 |
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Thomas Harte
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039aed1bd1
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Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
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2017-08-25 21:26:01 -04:00 |
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Thomas Harte
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d77d7fdd78
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Merge pull request #220 from TomHarte/Analysis
Resolves all current analyser warnings.
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2017-08-24 22:19:51 -04:00 |
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Thomas Harte
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c6e6c3fcfb
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Resolves all current analyser warnings.
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2017-08-24 22:18:44 -04:00 |
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Thomas Harte
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ecd3350a6f
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Merge pull request #219 from TomHarte/ConstSafety
Makes all of PartialMachineCycle const
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2017-08-24 22:04:06 -04:00 |
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Thomas Harte
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fa19e2d9c2
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Removes some detritus.
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2017-08-24 22:00:21 -04:00 |
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Thomas Harte
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95d360251d
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Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
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2017-08-24 21:32:33 -04:00 |
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Thomas Harte
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7af3de010e
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Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
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2017-08-23 22:25:31 -04:00 |
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Thomas Harte
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cefd421992
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Merge pull request #218 from TomHarte/6845Factored
Refactors the 6845 to make end-of-line and end-of-frame conditions more explicit and to reduce repetition
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2017-08-22 22:21:17 -04:00 |
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Thomas Harte
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a914eadc85
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Ensured that register 6 is checked on every loop.
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2017-08-22 22:17:45 -04:00 |
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Thomas Harte
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131b340d75
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Dodges a lambda copy.
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2017-08-22 21:55:10 -04:00 |
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Thomas Harte
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e956740c56
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Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
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2017-08-22 21:54:48 -04:00 |
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Thomas Harte
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8afd83b91f
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Merge pull request #217 from TomHarte/CompiletimeOptions
Introduces compile-time selection of minor CPU core features and applies forceinline when appropriate
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2017-08-21 22:29:24 -04:00 |
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Thomas Harte
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40d7a603db
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Ensured that forceinline does nothing in debug builds.
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2017-08-21 22:04:15 -04:00 |
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Thomas Harte
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ee71be0e7e
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Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
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2017-08-21 21:56:42 -04:00 |
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Thomas Harte
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cde29c4bf4
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Added forceinlines and properly declared finals and overrides.
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2017-08-21 21:07:10 -04:00 |
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Thomas Harte
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e1aded0d95
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Allows Z80 users to opt out of support for the bus request line. Which both now do.
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2017-08-21 20:43:12 -04:00 |
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Thomas Harte
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1237f174fe
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Merge pull request #216 from TomHarte/NoiseReduciton
Cleans up issues affecting the sleeper mechanism and the CPC
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2017-08-20 13:26:56 -04:00 |
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Thomas Harte
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0cbc1753b9
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Quick fixes: the binary tape player now considers talk to the sleep observer only if motor control changes. The Amstrad CPC no longer attempts to use the component argument to identify the caller, since this will often be that of the superclass and not that of the derived class known to the CPC.
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2017-08-20 13:18:46 -04:00 |
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Thomas Harte
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5cf0395936
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Merge pull request #215 from TomHarte/Z80BusReq
Removes repeated checking of bus_request_line_ by the Z80.
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2017-08-20 12:40:37 -04:00 |
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Thomas Harte
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6315c22b80
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Removed repeated checking of bus_request_line_. It's now checked only after each outward perform_machine_cycle.
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2017-08-20 12:39:45 -04:00 |
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Thomas Harte
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4614a56843
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Merge pull request #214 from TomHarte/Sleeper
Experimentally introduces the concept of a 'sleeper' — a component that will volunteer to be unclocked for a period
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2017-08-20 12:29:32 -04:00 |
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Thomas Harte
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8f5ae4a326
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The CPC now responds to tape-originating sleeper observations.
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2017-08-20 12:21:02 -04:00 |
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Thomas Harte
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8fdc5012e4
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Updated TapePlayer and BinaryTapePlayer to be sleepers.
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2017-08-20 12:18:36 -04:00 |
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Thomas Harte
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e88a51e75e
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Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80.
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2017-08-20 12:05:00 -04:00 |
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Thomas Harte
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49285e9caa
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Attempted to implement Sleeper in Drive and therefore in DiskController. Also corrected a couple of nonconformant file names.
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2017-08-20 11:54:54 -04:00 |
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Thomas Harte
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e3f2118757
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Merge branch 'master' into Sleeper
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2017-08-20 10:58:03 -04:00 |
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Thomas Harte
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daeaa4752f
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Merge pull request #213 from TomHarte/MinorPalette
Makes a variety of minor performance improvements to the CPC
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2017-08-20 10:57:41 -04:00 |
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Thomas Harte
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5344e3098b
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Minor: made has_disk something that is decided on insertion/deletion.
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2017-08-20 10:55:08 -04:00 |
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Thomas Harte
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cedb809c21
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Sketched out a protocol designed to save processing time on anything that may sleep — probably just disk controllers for now but one can easily imagine it being applicable to printers, and possibly sound chips with suitable changes in guarantee for sound packet receivers.
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2017-08-20 10:53:25 -04:00 |
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Thomas Harte
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2d9efccc98
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Introduced a master 'is sleeping' flag. I'm starting to think there's a pattern forming here.
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2017-08-20 10:43:53 -04:00 |
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