6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-11 14:05:21 +00:00
Code Issues Projects Releases Wiki Activity
5,031 Commits 8 Branches 121 Tags 496 MiB
241d29ff7c
Commit Graph

193 Commits

Author SHA1 Message Date
Thomas Harte
85d25068a8 Attempts a full implementation of memory shifts. 2019-04-09 22:04:25 -04:00
Thomas Harte
eda88cc462 Implements MOVE to CCR. 2019-04-07 22:24:17 -04:00
Thomas Harte
652f4ebfed Implements CLR, NEG, NEGX and NOT. 2019-04-07 22:07:39 -04:00
Thomas Harte
06a2f59bd0 Implements DBcc. 2019-04-06 23:21:01 -04:00
Thomas Harte
af02ce9c6e Attempts to correct various instances of PC-relative addressing. 2019-04-05 23:49:13 -04:00
Thomas Harte
56e42859ab Ensures the supervisor flag is updated properly on MOVE to SR. 2019-04-05 23:21:50 -04:00
Thomas Harte
2d153359f8 Adds BTST. 2019-04-04 21:43:22 -04:00
Thomas Harte
bfd405613c Reuse of addresses is also no longer implicit. 2019-04-03 21:27:11 -04:00
Thomas Harte
689ba1d4a2 Effective address adjustments now have to be explicit. 2019-04-03 19:13:10 -04:00
Thomas Harte
39b9d00550 Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification. 2019-04-02 21:50:58 -04:00
Thomas Harte
64f99d83a4 Takes a stab at offering ADD, ADDA, SUB and SUBA operations. 
Not yet decoded.
 2019-04-01 21:21:26 -04:00
Thomas Harte
a9ceef5c37 Improves communication slightly. 2019-03-31 22:27:33 -04:00
Thomas Harte
c6f977ed4b Corrects CMPI and documentation; implements JMP. 2019-03-31 21:13:26 -04:00
Thomas Harte
bc6349f823 Adds RESET, fixes branches and attempts to fix CMPI. 2019-03-29 23:40:54 -04:00
Thomas Harte
a93a1ae40f Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq. 2019-03-29 23:13:41 -04:00
Thomas Harte
42634b500c Implements LEA. 2019-03-26 22:07:28 -04:00
Thomas Harte
be4b38c76a Adds BRA and Bcc. 2019-03-25 22:54:49 -04:00
Thomas Harte
7163b1132c Takes a run at CMPI. 
Also factors out a couple of mode things, clarifies on where things from the
prefetch are assembled to, and switches to ordering implemented instructions
alphabetically.
 2019-03-24 23:05:57 -04:00
Thomas Harte
3ccec1c996 Implements MOVE to SR, fleshing out the final bits of storage for the status word. 2019-03-24 18:20:54 -04:00
Thomas Harte
d7c3d4ce52 Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof. 2019-03-22 23:27:48 -04:00
Thomas Harte
ed7060a105 Made an initial stab at completing MOVEA.w. 
I think I'm probably peeking into the prefetch queue incorrectly.
 2019-03-22 21:43:51 -04:00
Thomas Harte
db0da4b741 Improves get/set state. 2019-03-22 19:34:17 -04:00
Thomas Harte
c9c16968bb Implements MOVEA as distinct from MOVE. 
At least as far as MOVE is implemented, that is.
 2019-03-22 19:25:53 -04:00
Thomas Harte
fdc598f2e1 Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths. 2019-03-21 22:30:41 -04:00
Thomas Harte
eeb161ec51 Converts the prefetch queue into a 32-bit quantity. 2019-03-19 21:33:52 -04:00
Thomas Harte
21cb7307d0 Adds MOVE #, Dn and MOVEA An, An. 
As well as the scheduling for `(d16,PC), Dd` and `MOVE (d8,As,Xn), Dd` other than the .ls.
 2019-03-19 11:53:37 -04:00
Thomas Harte
412a1eb7ee Takes an initial run at (An)+, -(An), (d16,An) and (d8,An,Xn) addressing modes. 
With only MOVEs from those to a data register implemented so far.
 2019-03-18 22:51:32 -04:00
Thomas Harte
1d801acf72 Switched to a better ABCD fix. 2019-03-17 22:04:32 -04:00
Thomas Harte
0d7bbdad54 Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix. 2019-03-17 21:57:00 -04:00
Thomas Harte
53b3d9cf9d Implements a few more MOVE variants, plus MOVEA. 2019-03-17 14:34:16 -04:00
Thomas Harte
58f035e31a Makes error more communicative. 2019-03-16 23:05:12 -04:00
Thomas Harte
a8f1d98d40 Small further adjustments; seems likely to be correct now. 2019-03-16 23:01:56 -04:00
Thomas Harte
cf6fa98433 Corrects detection of terminal micro-ops. 2019-03-16 22:50:44 -04:00
Thomas Harte
937b3ca81d Attempts properly to honour the bus-op and microcycle contract. 2019-03-16 22:36:09 -04:00
Thomas Harte
388d808536 Switches to providing UDS and LDS implicitly via address. 
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
 2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d Adds an implementation of SBCD and slightly neatens syntax for building programs. 2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956 This might very well be the 68000's first real gasp: performing an ABCD. 2019-03-14 19:32:15 -04:00
Thomas Harte
bb04981280 I'm still dithering on address management, but this seeks fully to implement ABCD and SUBD bus programs. 2019-03-13 21:08:13 -04:00
Thomas Harte
57898ed6dd This is where my thinking now resides. Two levels of indirection, and consolidated collections. 2019-03-12 22:46:31 -04:00
Thomas Harte
33b53e7605 Settles upon disassembly as the route in, and begins work in that direction. 2019-03-11 22:47:58 -04:00
Thomas Harte
89c71f9119 Introduces EmuTOS, and starts constructing test cases around it. 2019-03-10 18:40:12 -04:00
Thomas Harte
98aa597510 A theoretical 68000 could now perform its /RESET. That's all though. 2019-03-10 17:42:13 -04:00
Thomas Harte
de56d48b2f Embraces a more communicative 68000 bus. 2019-03-10 17:27:34 -04:00