Thomas Harte
26de5be07c
Corrects memptr behaviour of LDIR/LDDR and CPIR/CPDR.
2020-02-27 20:44:53 -05:00
Thomas Harte
87474d5916
Corrects memptr behaviour of OUT (C), 0.
2020-02-27 20:38:27 -05:00
Thomas Harte
06163165d9
Corrects memptr effect of LD rr, (nn).
2020-02-26 22:22:54 -05:00
Thomas Harte
ec82c075be
Fixes memptr for IN C, (C).
2020-02-26 22:19:37 -05:00
Thomas Harte
3b0df172a7
Corrects memptr behaviour of JP nn.
2020-02-26 22:02:15 -05:00
Thomas Harte
7058dbc3cc
Corrects memptr for LD HL, (nn).
2020-02-26 21:54:49 -05:00
Thomas Harte
b64de89d2d
Corrects JR memptrs.
2020-02-26 21:47:34 -05:00
Thomas Harte
8878396339
Corrects DJNZ memptr behaviour.
2020-02-26 21:42:31 -05:00
Thomas Harte
3097c4ccae
Improves MEMPTR testing and some results.
2020-02-24 23:32:18 -05:00
Thomas Harte
7959d243f6
Adds single-stepping. Of a kind.
2020-02-24 23:31:42 -05:00
Thomas Harte
79dd402bc8
Consolidates different test port input selection.
2020-02-23 16:12:28 -05:00
Thomas Harte
3f3229851b
Implements MEMPTR for IN.
2020-02-23 00:32:33 -05:00
Thomas Harte
1c154131f9
Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
2019-10-29 22:36:29 -04:00
Thomas Harte
8a14f5d814
Updates to Xcode11 recommended project settings.
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The updated compiler also flagged a potential issue with CPU::Z80::Register not being a namespace re: 'Refresh' versus CPU::Z80::PartialMachineCycle. I don't entirely see it, but this fixes the problem.
I also finally figured out what the compiler was trying to tell me about ROMRequester.xib.
2019-09-22 12:13:56 -04:00
Thomas Harte
fa226bb1b9
Seeks to reduce enquiry costs.
2019-07-17 15:09:26 -04:00
Thomas Harte
40b2fe7339
Merge branch 'master' into 68000
2019-04-26 00:02:35 -04:00
Raphaël Zumer
71ac26944d
Correct typos in Z80.hpp
2019-04-19 17:44:52 -04:00
Thomas Harte
4aeb9a7c56
Genericises RegisterPair.
2019-03-09 21:16:11 -05:00
Thomas Harte
d97348dd38
Eliminates dangling uses of printf.
2019-03-02 18:07:05 -05:00
Thomas Harte
0b14850467
Corrects some comments.
2018-06-24 23:02:36 -04:00
Thomas Harte
9a91ae38c1
Differentiates reasons for a read to be four cycles.
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Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
2018-06-20 21:34:21 -04:00
Thomas Harte
ad9b0cd4e3
Eliminates all endashes.
2018-05-13 15:43:03 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
45be1c19df
Resolves undefined behaviour of a signed shift left.
2018-03-22 21:59:39 -04:00
Thomas Harte
0e73ba4b3e
Introduces proper 5/3 SCF/CCF behaviour for the Z80.
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While also `const`ing a bunch of things.
2018-03-09 09:47:00 -05:00
Thomas Harte
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
Thomas Harte
74dfe56d2b
Expands documentation of NMI setting.
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Given that it was previously incorrect, explains logic behind request_status_ and last_request_status_ setting. Also takes the opportunity to ensure that NMI is 'sampled' at the same time as IRQ; whether the next thing should be the NMI routine now occurs one cycle before the end of any instruction. That's an assumption for now. Testing to come.
2018-03-02 11:10:02 -05:00
Thomas Harte
b02e4fbbf6
Corrects NMI receipt to be genuinely edge triggered.
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Previously a caller that signalled NMI set multiple times would trigger multiple NMIs.
2018-03-01 22:04:56 -05:00
Thomas Harte
23c47e21de
Proceeds the ColecoVision to booting.
2018-02-24 18:14:38 -05:00
Thomas Harte
7dfbe4bb93
Ensures proper Boolean startup values for IFF1 and IFF2.
2017-11-29 20:32:55 -05:00
Thomas Harte
5aef81cf24
Commutes cross-platform #pragma marks to //MARK:s.
2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
Thomas Harte
cb0f58ab7a
Corrects order-of-initialisation errors in the CPC (again), TextureBuilder, TextureTarget, Z80, MFM parser and binary tape player.
2017-11-10 22:57:03 -05:00
Thomas Harte
c0055a5a5f
Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code.
2017-11-09 22:04:49 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
ad9df4bb90
Commutes uint8_t *, uint16_t *, uint32_t *, size_t, off_t and long to functional-style casts.
2017-10-21 22:30:15 -04:00
Thomas Harte
e983854e71
Converts all uint8_t and uint16_t casts to the functional style.
2017-10-21 21:50:53 -04:00
Thomas Harte
45499050b6
Separates Z80Base.cpp into its component classes.
2017-09-04 11:04:01 -04:00
Thomas Harte
a1e200cc65
Further strips back the amount exposed in Z80-related headers.
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Almost all opcode table generation macros and code now resides neatly in the world of .CPP.
2017-09-01 22:19:16 -04:00
Thomas Harte
e6ac939ae0
Reintroduces missing noexcept specifier.
2017-09-01 20:51:31 -04:00
Thomas Harte
b034d4e6f8
Refactors the Z80 to separate out interface and implementation.
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Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way.
2017-09-01 20:50:24 -04:00
Thomas Harte
fab6908129
Corrects the all-RAM Z80 to declare that it needs the wait line to be implemented.
2017-08-26 23:18:11 -04:00
Thomas Harte
57bfec285f
Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
2017-08-26 23:08:57 -04:00
Thomas Harte
fa19e2d9c2
Removes some detritus.
2017-08-24 22:00:21 -04:00
Thomas Harte
95d360251d
Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
2017-08-24 21:32:33 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
e1aded0d95
Allows Z80 users to opt out of support for the bus request line. Which both now do.
2017-08-21 20:43:12 -04:00
Thomas Harte
6315c22b80
Removed repeated checking of bus_request_line_. It's now checked only after each outward perform_machine_cycle.
2017-08-20 12:39:45 -04:00
Thomas Harte
039811ce6a
Switched the Z80 to being something a machine has, not something a machine is.
2017-08-02 22:09:59 -04:00
