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11,386 Commits 8 Branches 121 Tags 496 MiB
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Author SHA1 Message Date
Thomas Harte
2a36d0fcbc Adjust user-mode test. 2024-03-07 14:00:38 -05:00
Thomas Harte
0e92885ed5 Fix ad hoc popcount; ARM does carry 'backwards'. 2024-03-07 13:27:41 -05:00
Thomas Harte
f5225b69e5 Add note to self. 2024-03-07 11:48:44 -05:00
Thomas Harte
15ee84b2eb Fix MUL ambiguity. 2024-03-07 11:45:39 -05:00
Thomas Harte
d380cecdb7 Add timers that count. 2024-03-07 11:39:26 -05:00
Thomas Harte
ae3cd924e8 Add a 2Mhz tick for timers. 2024-03-07 11:12:40 -05:00
Thomas Harte
a0f0f73bde Fix MOV as unconditional branch. 2024-03-07 10:31:26 -05:00
Thomas Harte
7cdceb7b4f Add a specific shout-out on prefetch abort, for debugging. 2024-03-07 10:23:46 -05:00
Thomas Harte
38b5624639 Add a little more VIDC detail. 2024-03-07 10:05:22 -05:00
Thomas Harte
3405b3b287 Add power-on bit, moving problems forward. 2024-03-06 22:14:56 -05:00
Thomas Harte
173fc9329a Add a little protection logic. 2024-03-06 22:00:34 -05:00
Thomas Harte
691a42d81e Attempt some logical mapping. 2024-03-06 21:51:19 -05:00
Thomas Harte
4059905f85 Slightly reorder messaging. 2024-03-06 16:45:17 -05:00
Thomas Harte
bbb520fd12 Transcribe some notes. 2024-03-06 15:31:07 -05:00
Thomas Harte
108a056f1c Execution now runs into a prefetch abort loop. 2024-03-06 15:05:24 -05:00
Thomas Harte
ed92e98ca2 Start looking at address translation. 2024-03-06 14:56:06 -05:00
Thomas Harte
0d666f9935 Get a bit more rigorous about reporting. 2024-03-06 09:54:39 -05:00
Thomas Harte
fe467be124 Further stick to existing type. 2024-03-05 10:56:09 -05:00
Thomas Harte
ba5f142515 Take further stab at TEQ PC, etc. 2024-03-05 10:55:44 -05:00
Thomas Harte
ed586e80bc Don't write to the PC with logical operations. 2024-03-05 09:32:35 -05:00
Thomas Harte
871c5467d7 Avoid sign change. 2024-03-05 09:31:42 -05:00
Thomas Harte
387791635e Start to establish a memory map. 2024-03-04 21:43:06 -05:00
Thomas Harte
b7a1363add Add an incorrect execution loop. 2024-03-04 21:09:24 -05:00
Thomas Harte
341b705bef Remove pointless check. 2024-03-04 14:11:44 -05:00
Thomas Harte
0b65aa39cd Add explicit assignment operator. 2024-03-04 14:09:53 -05:00
Thomas Harte
1b7c3644f4 Eliinate meaningless 'const'. 2024-03-04 14:09:27 -05:00
Thomas Harte
0cdca12e06 Resolve type mismatches. 2024-03-04 13:53:46 -05:00
Thomas Harte
61d4c69e45 Fix template parameter reference. 2024-03-04 13:25:40 -05:00
Thomas Harte
79865e295b Avoid ambiguous template parameter; use standard type. 2024-03-04 12:20:40 -05:00
Thomas Harte
1f43047de8 Loop the ARM executor into the build. 2024-03-04 12:08:46 -05:00
Thomas Harte
6f0ad0ab71 Add an empty Archimedes shell. 2024-03-04 12:06:43 -05:00
Thomas Harte
447734b1e9
Merge pull request #1354 from TomHarte/Acorn 
Reorganise 'Electron' under 'Acorn'.
 2024-03-04 11:55:56 -05:00
Thomas Harte
3e80651a0e Collect 'Electron' under 'Acorn'. 2024-03-04 11:31:25 -05:00
Thomas Harte
692a9da2e4
Merge pull request #1353 from TomHarte/ArchmidesAnalysis 
Add a through path for Archimedes disk images.
 2024-03-04 10:57:19 -05:00
Thomas Harte
e27312c980 Add to machine lists. 2024-03-04 10:19:06 -05:00
Thomas Harte
eae92a0cdb Add a through path for Archimedes disk images. 2024-03-04 10:13:57 -05:00
Thomas Harte
95cc34ba23
Merge pull request #1352 from TomHarte/ByeByeActive 
Obscure storage for active registers.
 2024-03-03 22:09:34 -05:00
Thomas Harte
7532b461cd
Merge pull request #1351 from TomHarte/PositiveExpression 
Express offset test as positive logic.
 2024-03-03 22:03:37 -05:00
Thomas Harte
230e9c6327 Obscure active. 2024-03-03 21:43:30 -05:00
Thomas Harte
11c4d2f09e Add further exposition. 2024-03-03 21:38:27 -05:00
Thomas Harte
f2db1b4aae Merge branch 'TiedDown' into PositiveExpression 2024-03-03 21:31:26 -05:00
Thomas Harte
b42a6e447d Tie down more corners. 2024-03-03 21:29:53 -05:00
Thomas Harte
8a83d71560 Fix condition. 2024-03-03 14:40:05 -05:00
Thomas Harte
9fd7d5c10f Switch test and meaning. 2024-03-03 14:34:21 -05:00
Thomas Harte
7a5ed6c427
Merge pull request #1350 from TomHarte/ArchimedesROM 
Add RISC OS catalogue entry; do some basic ARM debugging.
 2024-03-03 14:32:25 -05:00
Thomas Harte
4e7963ee81 Clarify PC semantics; remove faulty underscore. 2024-03-03 14:11:02 -05:00
Thomas Harte
945b7e90da Add just enough to persuade self that execution is broadly sane. 2024-03-03 14:03:08 -05:00
Thomas Harte
99f0233b76 Fix immediate offset and data processing operation. 2024-03-02 23:27:37 -05:00
Thomas Harte
62da0dee7f Unify reads. 2024-03-02 23:15:17 -05:00
Thomas Harte
1663d3d9d1 Introduce disaster of an attempted test run. 2024-03-02 22:40:12 -05:00