36 Commits

Author	SHA1	Message	Date
Thomas Harte	47f36f08fb	Switches to a synchronous audio state machine; renames advance -> advance_dma. ... I can worry about how to just-in-time things once I better understand the hardware in general.	2021-11-13 15:53:41 -05:00
Thomas Harte	8ef9a932aa	Adds inclusive fill test; fixes inclusive fills.	2021-11-07 14:26:13 -08:00
Thomas Harte	299d517449	Performs a first implementation of fill mode.	2021-10-31 14:36:31 -07:00
Thomas Harte	edb75e69cb	Implement bitplane modulos.	2021-10-29 11:29:22 -07:00
Thomas Harte	f3e895f17c	Tag intended unused parameters.	2021-10-29 06:21:02 -07:00
Thomas Harte	07facc0636	Takes a stab at BZERO.	2021-10-28 18:12:46 -07:00
Thomas Harte	b10f5ab110	Apply A mask when loading into barrel shifter.	2021-10-26 20:02:28 -07:00
Thomas Harte	b4286bb42b	Modulos are subtracted in descending mode.	2021-10-26 07:21:51 -07:00
Thomas Harte	7118a515e0	Reduce logging in trustworthy areas.	2021-10-23 20:36:41 -07:00
Thomas Harte	4917556a99	The shift goes the other way in descending mode.	2021-10-16 11:09:40 -07:00
Thomas Harte	aa6b0f07b7	Correct filename.	2021-10-16 05:37:46 -07:00
Thomas Harte	9be23ecc34	Add end-of-Blit interrupt. ... Along with a slightly easier path for posting interrupts, in C++ compilation unit terms.	2021-10-13 15:09:19 -07:00
Thomas Harte	a282a51673	Remove last of the direct printf'ing.	2021-09-30 02:42:59 -04:00
Thomas Harte	b7b13e20d1	Single column blits should use both masks.	2021-09-29 22:49:35 -04:00
Thomas Harte	402fa41bc0	Corrects initial error value.	2021-09-29 22:19:17 -04:00
Thomas Harte	140e24ef15	Grab further copy flags.	2021-09-28 22:11:58 -04:00
Thomas Harte	ffcd2ea10c	Attempts more properly to implement line mode.	2021-09-28 21:39:09 -04:00
Thomas Harte	cb460de94d	Makes bad first attempt at a Bresenham inner loop.	2021-09-27 22:06:00 -04:00
Thomas Harte	f6624bf776	Edges mildly closer to line output.	2021-09-26 19:18:12 -04:00
Thomas Harte	b4b6c4d86f	Attempts to support left and right masks.	2021-09-26 18:42:08 -04:00
Thomas Harte	759689ff31	Fix line mode flag, add busy status.	2021-09-26 18:16:00 -04:00
Thomas Harte	42ef459e20	Resolve resting values.	2021-09-23 22:05:59 -04:00
Thomas Harte	cad1a9e0f1	Correct bit test.	2021-09-23 20:42:31 -04:00
Thomas Harte	9a7a54f22f	Take alternative guess as to meaning of 'use' bits.	2021-09-23 18:42:12 -04:00
Thomas Harte	137d1c61bd	Allow for channel enables and blitting direction.	2021-09-23 18:38:37 -04:00
Thomas Harte	adc071ed7a	Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.	2021-09-23 18:30:35 -04:00
Thomas Harte	ab69fe56c9	Take a first shot at magical instant blitting.	2021-09-23 18:13:51 -04:00
Thomas Harte	7092429f7c	Added some notes to self on line mode.	2021-09-20 23:08:26 -04:00
Thomas Harte	0eeaaa150a	Correct Copper start address.	2021-09-16 21:01:37 -04:00
Thomas Harte	692d87f446	Attempts to restrict blitter slot allocation.	2021-09-16 19:56:28 -04:00
Thomas Harte	6572efe2a7	Clarifies word addressing.	2021-09-16 08:24:52 -04:00
Thomas Harte	add11db369	Factors out DMADevice, which is now a parent of Blitter.	2021-09-14 20:51:32 -04:00
Thomas Harte	fd70f7ad43	Attempts to make pixel content observeable.	2021-09-08 20:57:26 -04:00
Thomas Harte	e412927415	Logs a bit more from the Blitter, gives it access to slots.	2021-08-10 07:17:01 -04:00
Thomas Harte	2bc9af09e1	Factors out the chipset.	2021-07-22 21:16:23 -04:00
Thomas Harte	e85db40b0f	Sketches out a blitter class.	2021-07-22 18:43:07 -04:00