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8,768 Commits 8 Branches 122 Tags
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999 Commits

Author SHA1 Message Date
Thomas Harte
3a42b0ac3d Correct BSR test. 2022-04-21 16:31:25 -04:00
Thomas Harte
14ff3162cf Correct MOVEM syntax, output of BSR. 2022-04-21 16:28:32 -04:00
Thomas Harte
768f47198f Add proper arguments for Bcc, BRA, BSR. 2022-04-21 16:10:21 -04:00
Thomas Harte
b4bb7cdaf9 Map three-bit Q to 8, not 0. 2022-04-21 09:57:23 -04:00
Thomas Harte
3673f931b8 Correct ASL/ASR/etc output. 2022-04-21 09:48:49 -04:00
Thomas Harte
3dce673b37 Add second operand to DBcc. 2022-04-20 20:04:56 -04:00
Thomas Harte
f7932d8583 Correct JSR and DBcc output. 2022-04-20 19:27:20 -04:00
Thomas Harte
b6c91035f4 Merge branch 'OpDumper' of github.com:TomHarte/CLK into OpDumper 2022-04-20 16:41:01 -04:00
Thomas Harte
7f030bc282 Preserve An at start of CMPAs. 2022-04-20 16:37:12 -04:00
Thomas Harte
32f946b3f0 Fix CMPA output. 2022-04-20 16:31:59 -04:00
Thomas Harte
939f015007 Remove suffixes from BTST/BCHG/etc. 2022-04-20 09:00:48 -04:00
Thomas Harte
20d54c0397 Tighten test. 2022-04-20 08:32:11 -04:00
Thomas Harte
950fddebf9 Preserve MOVE USP. 2022-04-20 08:30:16 -04:00
Thomas Harte
47d5d65633 Attempt to resolve all missing register numbers. 2022-04-19 20:38:08 -04:00
Thomas Harte
be1cec8f55 Ensure LEA appears as LEA. 2022-04-19 20:20:28 -04:00
Thomas Harte
6207f2ab41 Correct MOVEA output. 2022-04-19 17:15:36 -04:00
Thomas Harte
e30a02a0c0 Better log MOVEs. 2022-04-19 16:57:46 -04:00
Thomas Harte
c7097274c9 Add register numbers to MOVEs. 2022-04-19 16:33:18 -04:00
Thomas Harte
e82f2a3810 Correct ADDX/SUBX mode and register. 2022-04-19 16:20:01 -04:00
Thomas Harte
cbf6ae81d0 Output NOP, include register number in NBCD. 2022-04-19 08:05:37 -04:00
Thomas Harte
7a6fab72fe Include register numbers and Q values. 2022-04-17 19:42:45 -04:00
Thomas Harte
4005506e42 Output all existing decodings. 2022-04-17 07:55:13 -04:00
Thomas Harte
ee625cb8a8 Minor style improvements; especially: don't assume value of NoBusProgram. 2021-12-25 14:05:38 -05:00
Thomas Harte
f20940a37b Give Program full ownership of the sentinel value. 
In case I want to reduce the size of this field later.
 2021-12-23 16:32:21 -05:00
Thomas Harte
32e0a66610 Trust the compiler with this bit field. 2021-12-23 16:28:55 -05:00
Thomas Harte
d9598b35c2 Add some additional metrics. 2021-12-23 16:27:54 -05:00
Thomas Harte
0df8173536 Merge branch 'master' into Amiga 2021-11-24 08:58:03 -05:00
Thomas Harte
7e31658932 Remove accidental commit. 2021-10-26 21:49:32 -07:00
Thomas Harte
76767da300 Undo accidental change. 2021-10-25 21:48:19 -07:00
Thomas Harte
dc8701a929 Introduce some additional Blitter test cases. 2021-10-25 21:40:20 -07:00
Thomas Harte
313dbe05e0 Switch to more consistent inlining. 2021-09-23 22:36:15 -04:00
Thomas Harte
adf7124e2c Eliminate 6502Base.cpp. 2021-09-23 22:33:33 -04:00
Thomas Harte
863971f944 68000: fix E alignment, expand Microcycle::apply. 2021-09-08 21:03:37 -04:00
Thomas Harte
fd70f7ad43 Attempts to make pixel content observeable. 2021-09-08 20:57:26 -04:00
Thomas Harte
5cc25d0846 Adds a further sanity assert. 2021-08-08 21:52:52 -04:00
Thomas Harte
e402e690b0 Assume and test that divide-by-zero posts the PC of the offending instruction. 2021-08-07 17:51:00 -04:00
Thomas Harte
dcbc9847a3 Attempts to get E synchronisation correct. 2021-08-05 20:08:34 -04:00
Thomas Harte
60b09d9bb0 Increases compile-time logging options. 2021-08-01 21:22:33 -04:00
Thomas Harte
f576baf214 I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests. 2021-07-30 21:21:16 -04:00
Thomas Harte
8d2d4c850f Revoke temporary debugging. 2021-07-25 19:59:10 -04:00
Thomas Harte
b7bed027d7 Ensures the value initially loaded to A7 is aligned. 
This is a bit of a guess; it's likely to be true though per the rule that A7 is always kept aligned.
 2021-07-25 19:55:23 -04:00
Thomas Harte
956a6dbd64 Improve commentary. 2021-07-23 19:23:54 -04:00
Thomas Harte
68fe19818e Expose more information about the E clock state. 2021-07-23 19:22:00 -04:00
Thomas Harte
69d62560b4 Adds comment to avoid potential future error. 2021-07-22 22:00:33 -04:00
Thomas Harte
26f4758523 Makes a further accommodation for PermitRead/Write. 2021-07-22 21:11:25 -04:00
Thomas Harte
5401744dc0 Add additional asserts. 2021-07-21 21:47:44 -04:00
Thomas Harte
fe10a10ac2 Correct address on stack upon priviliege exception. 2021-07-21 21:46:55 -04:00
Thomas Harte
b2ae8e7a4a Adds a type for the operation bitfield. 2021-07-18 20:54:54 -04:00
Thomas Harte
50b9d0e86d Logically, I think this should be unsigned. 2021-07-18 20:25:22 -04:00
Thomas Harte
0cfc7f732c Extends to support read/write permissions in apply. 2021-07-17 21:09:52 -04:00