Thomas Harte
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4197c6f149
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Attempts to make some further semantic sense of the various IWM controls.
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2019-05-30 22:17:49 -04:00 |
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Thomas Harte
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035f07877c
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Reduces conversions to vector.
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2019-05-30 12:08:35 -04:00 |
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Thomas Harte
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4632be4fe5
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Wires up the final IWM signal, SEL, preparatory to an implementation.
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2019-05-30 12:08:00 -04:00 |
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Thomas Harte
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b3d2b4cd37
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Fixes the interrupt return address.
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2019-05-29 20:27:46 -04:00 |
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Thomas Harte
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c86fe9ada9
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Ensures replace_write_values works in release builds.
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2019-05-29 19:00:53 -04:00 |
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Thomas Harte
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ecf93b7822
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Eliminates some type conversion warnings.
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2019-05-29 14:56:50 -04:00 |
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Thomas Harte
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541b75ee6e
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Further fixes PEA, and OR/AND/EOR Dn, (An).
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2019-05-29 14:37:15 -04:00 |
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Thomas Harte
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77b08febdb
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Corrects PEA and adds an additional debugging aid.
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2019-05-29 12:47:17 -04:00 |
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Thomas Harte
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fcda376f33
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Removes three further type conversion warnings.
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2019-05-28 21:56:49 -04:00 |
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Thomas Harte
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0848fc7e03
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Ensures the Mac uses auto vectored interrupts.
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2019-05-28 16:24:41 -04:00 |
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Thomas Harte
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3bb8d6717f
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Ensures A7 is correct at end of an UNLINK.
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2019-05-28 16:02:42 -04:00 |
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Thomas Harte
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5e2496d59c
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Simplifies and corrects MOVE logic.
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2019-05-28 15:17:03 -04:00 |
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Thomas Harte
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c52da9d802
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Adds some logging preparatory to a MOVE change.
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2019-05-28 15:05:42 -04:00 |
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Thomas Harte
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1d3dde32f2
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Ensures final byte of data can be accessed.
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2019-05-09 07:24:26 -04:00 |
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Thomas Harte
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0b999ce0e4
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Attempts to fix register-relative JSRs.
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2019-05-09 06:43:07 -04:00 |
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Thomas Harte
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b04bd7069d
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Corrects Scc and DBcc (xxx).l and (xxx).w.
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2019-05-09 06:28:55 -04:00 |
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Thomas Harte
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249b0fbb32
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Corrects PC on stack after an illegal instruction.
Also fixed LOG_TRACE functionality.
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2019-05-08 22:36:25 -04:00 |
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Thomas Harte
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41740fb45e
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Implements video position feedback.
At a substantial performance cost for now, but I'll worry about that once things are working.
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2019-05-08 16:54:19 -04:00 |
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Thomas Harte
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0ad88508f7
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Removes ROM mirroring above $600000.
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2019-05-08 15:07:03 -04:00 |
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Thomas Harte
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8293b18278
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Adds a TODO on what I think might be an incorrect implementation?
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2019-05-08 15:06:40 -04:00 |
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Thomas Harte
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2ba0364850
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Adds the shift register interrupt.
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2019-05-08 15:02:07 -04:00 |
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Thomas Harte
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8b72043f33
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Ensures no uninitialised variables.
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2019-05-08 14:54:54 -04:00 |
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Thomas Harte
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2e7bc0b98a
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Attempts the shift register.
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2019-05-08 14:54:40 -04:00 |
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Thomas Harte
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f0f9722ca6
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Takes a first crack at the keyboard's serial protocol.
Albeit that without a working shift register in the VIA, this shouldn't really work yet.
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2019-05-08 14:20:28 -04:00 |
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Thomas Harte
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b5ef88902b
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Edges further towards a functioning keyboard.
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2019-05-08 13:58:52 -04:00 |
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Thomas Harte
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8278809383
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Attempts to get more rigorous on communicating outward control line changes.
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2019-05-08 13:33:22 -04:00 |
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Thomas Harte
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4367459cf2
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Takes a first go at handshake and pulse modes.
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2019-05-08 12:48:29 -04:00 |
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Thomas Harte
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254132b83d
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Eliminates 6522Base in pursuit of working handshake modes.
Specifically: this means that the places from which the BusHandler may be called are more numerous.
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2019-05-08 12:35:17 -04:00 |
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Thomas Harte
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7b466e6d0a
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Begins work on a functioning keyboard.
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2019-05-08 12:34:26 -04:00 |
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Thomas Harte
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7e6d4f5a3e
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Adds emulation of the real-time clock.
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2019-05-08 00:12:19 -04:00 |
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Thomas Harte
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ce099a297a
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Eliminates RAM writes in ROM area.
I no longer think that logic is correct.
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2019-05-07 17:16:22 -04:00 |
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Thomas Harte
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949c848815
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Broadens address decoding.
To no obvious change in output.
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2019-05-06 22:57:29 -04:00 |
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Thomas Harte
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9bf9b9ea8c
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Ensures unmapped peripherals return a consistent value.
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2019-05-06 21:32:10 -04:00 |
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Thomas Harte
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d8ed8b66f3
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Improves carry/extend for ROXL and ROXR.
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2019-05-06 21:14:16 -04:00 |
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Thomas Harte
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a131d39451
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I now believe only the 6522 is on the synchronous bus.
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2019-05-06 14:10:13 -04:00 |
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Thomas Harte
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b540f58457
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Sets a more appropriate display type.
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2019-05-05 23:22:05 -04:00 |
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Thomas Harte
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4f5a38b5c5
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Adds support for the alternate video buffer.
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2019-05-05 23:05:24 -04:00 |
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Thomas Harte
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cefc3af08b
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Corrects RAM read decoding when the ROM overlay is enabled.
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2019-05-05 22:48:40 -04:00 |
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Thomas Harte
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e6ed50383c
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Corrects PEA and MOVE.l (An)[+], (xxx).L; also adds an extra test that caught the latter.
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2019-05-05 22:47:54 -04:00 |
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Thomas Harte
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96facc103a
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Adds an IWM shim and corrects graphics output.
... now that there is some.
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2019-05-05 21:55:34 -04:00 |
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Thomas Harte
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407bbfb379
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Pretending the Disk II is an IWM doesn't seem to achieve much.
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2019-05-05 18:12:25 -04:00 |
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Thomas Harte
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a99ebda513
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Takes a first shot at (inverted) Mac video output.
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2019-05-04 22:27:58 -04:00 |
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Thomas Harte
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537b604fc9
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It looks like writes should always go to RAM.
Now I see the screen buffer being filled with `0xffff`s, along with what is probably disk motor control data.
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2019-05-04 17:29:30 -04:00 |
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Thomas Harte
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98bc570bf7
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Adds further boilerplate around VIA and IWM decoding.
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2019-05-04 17:12:26 -04:00 |
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Thomas Harte
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181b77c490
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Adds decoding of IWM accesses and respect for the ROM overlay bit.
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2019-05-04 16:38:01 -04:00 |
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Thomas Harte
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bc9eb82e6f
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Adds in VIA access decoding, and a note to self on video.
The Mac now proceeds to try to talk to the IWM.
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2019-05-04 14:23:37 -04:00 |
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Thomas Harte
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29fc024ecd
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Starts negotiating the Macintosh memory map.
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2019-05-04 12:33:27 -04:00 |
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Thomas Harte
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c1695d0910
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Adds various notes to self.
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2019-05-03 23:55:28 -04:00 |
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Thomas Harte
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6d6a4e79c9
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Adds the absolute basics to include a 6522 in the Macintosh.
Not yet wired to anything.
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2019-05-03 23:40:22 -04:00 |
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Thomas Harte
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417a3e1540
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Adds missing call to flush.
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2019-05-03 23:31:12 -04:00 |
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