465 Commits

Author	SHA1	Message	Date
Thomas Harte	463fbb07f9	Adapt remaining 68000 tests to use Mk2.	2022-05-25 10:55:17 -04:00
Thomas Harte	9e3c2b68d7	Eliminate potential future implicit conversion warnings.	2022-05-24 11:05:24 -04:00
Thomas Harte	3349bcaaed	Attempt interrupt support.	2022-05-24 10:53:59 -04:00
Thomas Harte	6a442e0136	MOVEM has an immediate first operand.	2022-05-20 20:34:51 -04:00
Thomas Harte	cb77519af8	Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.	2022-05-20 12:40:09 -04:00
Thomas Harte	ba8592ceae	At least on the 68000, Scc is read-modify-write.	2022-05-20 11:43:26 -04:00
Thomas Harte	452dd3ccfd	Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.	2022-05-20 11:20:23 -04:00
Thomas Harte	eeb6a088b8	Add a tag to avoid duplication.	2022-05-19 15:49:42 -04:00
Thomas Harte	e4c0a89889	Just use the four-bit register number directly.	2022-05-19 15:01:09 -04:00
Thomas Harte	c6c6213460	Bifurcate the fetch-operand flow. ... Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.	2022-05-19 10:27:51 -04:00
Thomas Harte	3db2de7478	Works 68000 mk2 into the comparative tests. ... ... revealing that I've leant a little too hard on __LINE__.	2022-05-16 20:04:13 -04:00
Thomas Harte	acb63a1307	Pull generalised DIVU/DIVS into a macro.	2022-05-15 20:01:51 -04:00
Thomas Harte	341bf2e480	Repattern DIVS after DIVU.	2022-05-15 16:54:58 -04:00
Thomas Harte	ff8e4754d7	Ensure STOP exits the run loop.	2022-05-14 19:17:32 -04:00
Thomas Harte	27c4d19455	Support STOP.	2022-05-14 11:35:35 -04:00
Thomas Harte	f83954f5b7	Switch to common bit-selection logic.	2022-05-13 15:08:15 -04:00
Thomas Harte	77b56c50e6	Ensure you can't trace into divide-by-zero, etc.	2022-05-13 14:02:56 -04:00
Thomas Harte	002a8c061f	Trim the public interface of Executor.	2022-05-13 13:55:37 -04:00
Thomas Harte	4299334e24	Clean up some TODOs, eliminate one further conditional.	2022-05-13 11:17:57 -04:00
Thomas Harte	4d03c73222	Ensure that the first instruction of privilege/line1010/etc exceptions isn't traced.	2022-05-13 11:08:22 -04:00
Thomas Harte	7a2fd93d08	Document BusHandler interface.	2022-05-13 10:59:36 -04:00
Thomas Harte	5b67c9bf4a	MOVE to SR requires supervisor privileges.	2022-05-13 09:01:03 -04:00
Thomas Harte	6c854e8ecc	Simplify is_supervisor semantics.	2022-05-13 07:53:40 -04:00
Thomas Harte	2e796f31d4	Support interrupts; documentation to come.	2022-05-12 20:52:24 -04:00
Thomas Harte	2fa6b2301b	Move string logic into Preinstruction.	2022-05-12 19:46:08 -04:00
Thomas Harte	a6e4d23c29	Tidy up primarily as per PatickvL's comments. ... ... though pulling the flag values out of an enum and into a namespace is entirely my own contribution, to keep them in their own namespace but having them overtly be ints.	2022-05-12 16:23:07 -04:00
Thomas Harte	6d43576db7	Remove errant semicolon.	2022-05-12 16:21:36 -04:00
Thomas Harte	b7d1bff0c7	Eliminate branches from ABCD.	2022-05-12 15:25:01 -04:00
Thomas Harte	79c5af755f	Eliminate branches from SBCD.	2022-05-12 15:18:03 -04:00
Thomas Harte	c6d84e7e60	Use Status::FlagT pervasively.	2022-05-12 11:42:33 -04:00
Thomas Harte	192513656a	After much guesswork, fix SBCD and thereby pass flamewing tests.	2022-05-12 11:39:01 -04:00
Thomas Harte	f3c1b1f052	Name flags, remove closing underscores on exposed data fields.	2022-05-12 08:19:41 -04:00
Thomas Harte	bd61c72007	Mutate SBCD to correct values, though not yet statuses.	2022-05-12 07:22:26 -04:00
Thomas Harte	0efeea1294	Slightly improve SBCD. Not there yet though.	2022-05-12 07:07:21 -04:00
Thomas Harte	a9902fc817	Fix ABCD when the result has an invalid lower digit.	2022-05-11 16:31:27 -04:00
Thomas Harte	d492156453	Add noreturn attribute as a warning.	2022-05-11 10:51:48 -04:00
Thomas Harte	96af3d5ec5	Fix infinite inner/outer loop.	2022-05-11 10:26:12 -04:00
Thomas Harte	69ba14e34e	Support the trace flag.	2022-05-11 09:39:15 -04:00
Thomas Harte	943c924382	Add missing: MOVE to/from USP, RESET.	2022-05-11 07:52:23 -04:00
Thomas Harte	4b97427937	Remove further magic constants.	2022-05-11 07:00:35 -04:00
Thomas Harte	ab8e1fdcbf	Take a swing at access faults and address errors.	2022-05-10 16:20:30 -04:00
Thomas Harte	477979c275	Fully formulate and document the flow controller.	2022-05-10 10:34:07 -04:00
Thomas Harte	c635720a09	Tidy up; provide a notification for bit-change operations.	2022-05-10 08:23:25 -04:00
Thomas Harte	f2a6a12f79	Remove further vestiges of timing.	2022-05-09 20:58:51 -04:00
Thomas Harte	7445c617bc	Start removing 68000-specific timing calculations.	2022-05-09 20:32:02 -04:00
Thomas Harte	8e7340860e	Minor thematic rearrangement.	2022-05-09 16:35:17 -04:00
Thomas Harte	2ca1eb4cf8	Move set_pc into the operation-specific group.	2022-05-09 16:20:15 -04:00
Thomas Harte	0af8660181	Remove add_pc and decline_branch in favour of operation-specific signals.	2022-05-09 16:19:25 -04:00
Thomas Harte	2f7cff84d9	Enable missing rotates and shifts.	2022-05-09 11:26:01 -04:00
Thomas Harte	8e5650fde9	Clean up Instruction.hpp.	2022-05-09 10:13:42 -04:00