124 Commits

Author	SHA1	Message	Date
Thomas Harte	47e8f3c0f1	Collapse [A/L]S[L/R].[bwl] into a template.	2022-10-16 22:21:20 -04:00
Thomas Harte	d5ceb934d2	Fix overflow flags, avoid bigger-word usage.	2022-10-16 21:52:00 -04:00
Thomas Harte	17c1e51231	Commute ROL/ROR to templates.	2022-10-16 12:19:09 -04:00
Thomas Harte	fee072b404	Commute ROXL and ROXR into a template.	2022-10-16 12:06:28 -04:00
Thomas Harte	0a9c392371	Remove unused bit_count.	2022-10-13 15:01:06 -04:00
Thomas Harte	06dbb7167b	Unify TST.	2022-10-11 21:31:14 -04:00
Thomas Harte	eff9a09b9f	Collapse MOVE and NEG[X] similarities.	2022-10-11 21:27:18 -04:00
Thomas Harte	1f19141746	Eliminate BiggerInt.	2022-10-11 16:19:47 -04:00
Thomas Harte	28093196b9	Convert DIVU/DIVS logic to a template.	2022-10-11 16:16:53 -04:00
Thomas Harte	eb206a08d9	Templatise MULU/MULS.	2022-10-11 16:02:20 -04:00
Thomas Harte	b2f005da1b	Collapse SR/CCR bitwise operations into a template.	2022-10-11 15:53:11 -04:00
Thomas Harte	8305a3b46a	Consolidate compare logic.	2022-10-11 12:57:02 -04:00
Thomas Harte	f3f23f90a3	Consolidate repetition in CLR.	2022-10-11 11:22:34 -04:00
Thomas Harte	77bc60bf86	Consolidate BCLR, BCHG and BSET into a macro.	2022-10-11 10:47:55 -04:00
Thomas Harte	ec5d57fefe	Eliminate 64-bit work.	2022-10-11 10:33:28 -04:00
Thomas Harte	58396f0c52	Perform a prima facie conversion of ADD/SUB[/X] from macros to templates.	2022-10-10 22:21:13 -04:00
Thomas Harte	02b6ea6c46	Factor out would-accept-interrupt test, per uncertainty re: level 7.	2022-06-03 08:31:56 -04:00
Thomas Harte	c3b436fe96	Use int64_t as an intermediary to avoid x86 exception on INT_MIN/-1.	2022-06-02 21:39:52 -04:00
Thomas Harte	659e4f6987	Include fixed cost of rolls. Which includes providing slightly more information to did_shift.	2022-06-01 20:30:51 -04:00
Thomas Harte	8ffaf1a8e4	Ensure did_divu/s are performed even upon divide by zero.	2022-05-29 21:18:19 -04:00
Thomas Harte	7788a109b0	Tweak more overtly to avoid divide by zero.	2022-05-29 20:51:50 -04:00
Thomas Harte	c97245e626	Fix CalcEA timing; make MOVEfromSR a read-modify-write.	2022-05-27 10:32:28 -04:00
Thomas Harte	9e3c2b68d7	Eliminate potential future implicit conversion warnings.	2022-05-24 11:05:24 -04:00
Thomas Harte	6a442e0136	MOVEM has an immediate first operand.	2022-05-20 20:34:51 -04:00
Thomas Harte	cb77519af8	Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.	2022-05-20 12:40:09 -04:00
Thomas Harte	ba8592ceae	At least on the 68000, Scc is read-modify-write.	2022-05-20 11:43:26 -04:00
Thomas Harte	452dd3ccfd	Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.	2022-05-20 11:20:23 -04:00
Thomas Harte	eeb6a088b8	Add a tag to avoid duplication.	2022-05-19 15:49:42 -04:00
Thomas Harte	e4c0a89889	Just use the four-bit register number directly.	2022-05-19 15:01:09 -04:00
Thomas Harte	c6c6213460	Bifurcate the fetch-operand flow. ... Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.	2022-05-19 10:27:51 -04:00
Thomas Harte	3db2de7478	Works 68000 mk2 into the comparative tests. ... ... revealing that I've leant a little too hard on __LINE__.	2022-05-16 20:04:13 -04:00
Thomas Harte	acb63a1307	Pull generalised DIVU/DIVS into a macro.	2022-05-15 20:01:51 -04:00
Thomas Harte	341bf2e480	Repattern DIVS after DIVU.	2022-05-15 16:54:58 -04:00
Thomas Harte	ff8e4754d7	Ensure STOP exits the run loop.	2022-05-14 19:17:32 -04:00
Thomas Harte	27c4d19455	Support STOP.	2022-05-14 11:35:35 -04:00
Thomas Harte	f83954f5b7	Switch to common bit-selection logic.	2022-05-13 15:08:15 -04:00
Thomas Harte	77b56c50e6	Ensure you can't trace into divide-by-zero, etc.	2022-05-13 14:02:56 -04:00
Thomas Harte	002a8c061f	Trim the public interface of Executor.	2022-05-13 13:55:37 -04:00
Thomas Harte	4299334e24	Clean up some TODOs, eliminate one further conditional.	2022-05-13 11:17:57 -04:00
Thomas Harte	4d03c73222	Ensure that the first instruction of privilege/line1010/etc exceptions isn't traced.	2022-05-13 11:08:22 -04:00
Thomas Harte	6c854e8ecc	Simplify is_supervisor semantics.	2022-05-13 07:53:40 -04:00
Thomas Harte	2e796f31d4	Support interrupts; documentation to come.	2022-05-12 20:52:24 -04:00
Thomas Harte	6d43576db7	Remove errant semicolon.	2022-05-12 16:21:36 -04:00
Thomas Harte	b7d1bff0c7	Eliminate branches from ABCD.	2022-05-12 15:25:01 -04:00
Thomas Harte	79c5af755f	Eliminate branches from SBCD.	2022-05-12 15:18:03 -04:00
Thomas Harte	c6d84e7e60	Use Status::FlagT pervasively.	2022-05-12 11:42:33 -04:00
Thomas Harte	192513656a	After much guesswork, fix SBCD and thereby pass flamewing tests.	2022-05-12 11:39:01 -04:00
Thomas Harte	f3c1b1f052	Name flags, remove closing underscores on exposed data fields.	2022-05-12 08:19:41 -04:00
Thomas Harte	bd61c72007	Mutate SBCD to correct values, though not yet statuses.	2022-05-12 07:22:26 -04:00
Thomas Harte	0efeea1294	Slightly improve SBCD. Not there yet though.	2022-05-12 07:07:21 -04:00