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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-02 17:51:12 +00:00
Commit Graph

225 Commits

Author SHA1 Message Date
Thomas Harte
e55db0cfe8 Made an attempt to eliminate creeping tape processing accuracy misses, which implied factoring out the GCM and LCD functions, which I then felt didn't really amount to signal processing. 2016-07-29 05:19:01 -04:00
Thomas Harte
5c1614ce7b Attempted to simplify, very slightly. 2016-07-28 14:35:39 -04:00
Thomas Harte
015cea494d Switched to a much-more straightforward PLL. I think I'm just fiddling now rather than moving forwards. Probably time to move on? 2016-07-28 11:32:14 -04:00
Thomas Harte
e061e849d4 Had a second bash at the PLL. Probably I should read some of the literature. 2016-07-27 16:24:24 -04:00
Thomas Harte
63f39608a6 Added just enough to get back to a working build. 2016-07-15 20:35:19 -04:00
Thomas Harte
165dbd9651 Started fleshing this out a bit. Hopefully. 2016-07-15 08:28:34 -04:00
Thomas Harte
0aa90b943b Switched to specifying bit length as a quotient for the purposes of a PCMSegment and verified that I had the logic for picking a Commodore time zone backwards: bigger numbers are faster, not slower.
Started sketching out a DiskDrive class.
2016-07-15 06:51:11 -04:00
Thomas Harte
6afd619791 Eliminated floating point arithmetic. 2016-07-14 19:47:00 -04:00
Thomas Harte
6b4fec37ff Moved down to a single divide. 2016-07-14 19:45:08 -04:00
Thomas Harte
481475a0f4 Switched to a full-on linear regression. Which causes the current tests to pass. 2016-07-14 19:42:01 -04:00
Thomas Harte
6d6b26b99f Actually made things worse. 2016-07-14 07:32:27 -04:00
Thomas Harte
d8d3464c56 Made a quick-hack attempt at PLL synchronisation. Which doesn't work. 2016-07-14 07:31:23 -04:00
Thomas Harte
d1fe07f14d Added test of perfect DPLL input timing. 2016-07-12 21:42:23 -04:00
Thomas Harte
94db45456e Started sketching out the basic form here, albeit that it doesn't yet do _the only thing it advertises itself as useful for_. 2016-07-12 20:23:56 -04:00
Thomas Harte
75d95c0bc0 Sketched out an interface for a digial PLL. Not persuaded yet. Baby steps. 2016-07-11 22:12:58 -04:00
Thomas Harte
1e9eedc314 Factored out the PCM track since it's going to be a useful construct for almost every file format. Documented it a little better. 2016-07-10 18:36:52 -04:00
Thomas Harte
66895d3ac7 Actually, I think this is the correct conversion from received speed to clock rate. It'll become obvious if it's not when I get back to working on the 1541 itself. 2016-07-10 18:24:12 -04:00
Thomas Harte
19ee430d4a Made an effort to support zoned tracks, at least. 2016-07-10 18:07:53 -04:00
Thomas Harte
6593caca93 Switched to a probably more helpful way around of expecting bits in bytes. 2016-07-10 16:21:52 -04:00
Thomas Harte
845a00ccef Attempted via linear search to implement PCMTrack::get_next_event. 2016-07-10 16:17:25 -04:00
Thomas Harte
f9510c1b67 Put sufficiently much of PCMTrack into place to get to a stored list of segments, having determined a common clock rate between them and therefore a complete track length. 2016-07-10 16:10:05 -04:00
Thomas Harte
4ae9f5ad5d Added preliminaries of reading the speed zone information. 2016-07-10 13:42:45 -04:00
Thomas Harte
8ae78ba4e0 Fixed signature check and fseek parameter order. 2016-07-10 13:32:59 -04:00
Thomas Harte
ff49857f5c Started sketching out support for the G64 file format. 2016-07-10 10:17:53 -04:00
Thomas Harte
9e3d6b762b Sketched out the generic interface for a disk, documenting it and the tape interface while I'm here. 2016-07-10 08:54:39 -04:00