53eae873d8
Merge pull request #913 from TomHarte/LowerModelTiming
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Brings timings into line with WoS specs.
2021-04-16 22:45:54 -04:00
93422f4b1c
Brings timings into line with WoS specs.
2021-04-16 22:40:51 -04:00
06cedb2e50
Merge pull request #912 from TomHarte/128kDecoding
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Corrects Spectrum 128kb partial decoding.
2021-04-16 22:02:25 -04:00
7fdb1d848b
Corrects Spectrum 128kb partial decoding.
2021-04-16 21:54:52 -04:00
246fd9442f
Merge pull request #911 from TomHarte/48kbSpectrum
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Adds the 48kb and 128kb Spectrums.
2021-04-15 22:25:07 -04:00
eb99a64b29
Adds new Spectrum models to Qt UI.
2021-04-15 22:20:34 -04:00
d7954a4cb1
Tweaks timing a little.
2021-04-15 21:51:49 -04:00
ef636da866
Attempts 48/128kb floating bus behaviour.
2021-04-15 21:19:21 -04:00
fa18b06dbf
Correct get_floating_value to be consistent in out-of-bounds behaviour.
2021-04-15 21:13:36 -04:00
349b9ce502
Don't post contended accesses other than on the +2a/+3.
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Those machines have an actual latch for this stuff, the others don't.
2021-04-15 21:13:06 -04:00
b2cf121410
Regresses default to the more-compatible +2.
2021-04-15 19:31:45 -04:00
71cf63bd35
Corrects internal cycle contention.
2021-04-15 19:17:11 -04:00
d1bb3aada4
Attempts to complete the in-machine application of contention.
2021-04-15 18:57:34 -04:00
b4214c6e08
Blocks off the AY from inputs in 48kb mode.
2021-04-15 18:04:16 -04:00
f5c7746493
Extends fast loading support to the just-introduced models.
2021-04-15 17:31:42 -04:00
f10ec80153
Gets started on different video timings.
2021-04-14 22:23:27 -04:00
0af405aa46
Starts working in the 48kb and 128kb Spectrums.
2021-04-14 21:37:10 -04:00
cf481effa6
Merge pull request #910 from TomHarte/FastContention
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Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
2021-04-14 20:21:52 -04:00
a1511f9600
Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
2021-04-14 20:15:40 -04:00
325e2b3941
Merge pull request #902 from TomHarte/Z80Lines
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Spell out, test and correct Z80 bus activity.
2021-04-13 22:22:26 -04:00
7017324d60
r_step is obsolete now that I know that [DD/FD]CB don't have a refresh cycle.
2021-04-13 22:17:30 -04:00
deb5d69ac7
Consolidates macros.
2021-04-13 22:11:28 -04:00
68a04f4e6a
Adds IN/OUT I/D [R] to complete tests.
2021-04-13 22:00:24 -04:00
0d61902b10
Adds CP[I/D/IR/DR] tests.
2021-04-13 20:03:11 -04:00
3eec210b30
Adds LDI/LDD/LDIR/LDDR tests.
2021-04-13 20:00:29 -04:00
5998f3b35b
Corrects LD[I/D/IR/DR] timing.
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Macro cleanup to come.
2021-04-13 20:00:18 -04:00
869567fdd9
Corrects EX (SP), HL breakdown.
2021-04-13 19:45:48 -04:00
2e70b5eb9f
Advances to EX (SP), HL, leaving only [LD/CP/IN/OT][I/D]{R}.
2021-04-13 19:45:29 -04:00
8a3bfb8672
Adds an IN/OUT test.
2021-04-13 17:55:51 -04:00
06f1e64177
Advances to IO.
2021-04-12 21:41:20 -04:00
b42780173a
Establishes that there really is no Read4 and Read4Pre distinction.
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Will finish these unit tests, then clean up.
2021-04-12 20:54:10 -04:00
36c8821c4c
Reaches the halfway point in tests.
2021-04-12 17:29:03 -04:00
947de2d54a
Switches five-cycle read to a post hoc pause.
2021-04-12 17:17:08 -04:00
9347fe5f44
Advances to next failing test: LD (ii+n), n.
2021-04-12 17:11:58 -04:00
e82367def3
Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.
2021-04-11 23:01:00 -04:00
9cde7c12ba
Shifts responsibility for refresh into the fetch-decode-execute sequence.
2021-04-11 22:50:24 -04:00
015556cc91
Switch (ii+n) to Read4Pre.
2021-04-11 10:26:14 -04:00
47c5a243aa
Restructures, the better to explore errors.
2021-04-10 21:32:42 -04:00
070e359d82
Introduces failing test for BIT b, (ii+n).
2021-04-10 18:00:23 -04:00
b397059d5e
Moves read time in Read4Pre.
2021-04-10 17:54:20 -04:00
400f54e508
Introduces failing test for bit b, (hl).
2021-04-10 12:04:48 -04:00
e0736435f8
Makes assumption that the address bus just holds its value during an internal operation.
2021-04-10 12:00:53 -04:00
b09c5538c6
Adds failing test for simple (ii+n) tests.
2021-04-09 21:28:35 -04:00
ce3d2913bf
Advances to 9 source table rows tested out of 37.
2021-04-09 20:38:17 -04:00
87202a2a27
Add two further tests, add checking of collected data size for all tests.
2021-04-09 18:32:03 -04:00
818a4dff25
Corrects ADD HL, dd test.
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Or, at least, likely corrects. The bus cycle breakdown in the Z80 data sheet implies these accesses should come after completion of the refresh cycle, not during its long tail, so I think +1 is correct.
2021-04-08 22:23:15 -04:00
eacffa49f5
Exposes IR during 'internal' operations.
2021-04-08 22:22:26 -04:00
9e506c3206
Adds failing ADD hl, dd test.
2021-04-08 22:19:22 -04:00
29cf80339a
Corrects too-short buffer.
2021-04-08 22:15:03 -04:00
50f53f7d97
Adds INC/DEC rr and LD SP, HL tests.
2021-04-08 22:14:53 -04:00
Thomas Harte
Thomas Harte