13 Commits

Author	SHA1	Message	Date
Thomas Harte	75d67ee770	Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.	2017-07-25 20:20:55 -04:00
Thomas Harte	a1e9a54765	Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.	2017-07-25 20:09:13 -04:00
Thomas Harte	b3ae920746	Converted the DPLL and disk controller classes to be ClockReceivers.	2017-07-24 21:04:47 -04:00
Thomas Harte	e5188a60dc	Settled on the new average-of-length approach to a PLL window sizing, eliminating the old errors-of-phase approach. Since it anchors automatically to the original target clocks per bit, killed the explicit mention of a tolerance.	2017-07-16 19:03:50 -04:00
Thomas Harte	51177e4e1f	Attempted a different implementation of the PLL, that responds to changes only once.	2017-07-16 16:49:04 -04:00
Thomas Harte	4489f120f9	Eliminated foolish double indirection on phase history.	2017-07-15 22:40:38 -04:00
Thomas Harte	e01f3f06c8	Completed curly bracket movement.	2017-03-26 14:34:47 -04:00
Thomas Harte	0dc2aa6454	Commuted all of 'Storage' other than 'Tape' to postfix underscores.	2016-12-03 11:59:28 -05:00
Thomas Harte	015cea494d	Switched to a much-more straightforward PLL. I think I'm just fiddling now rather than moving forwards. Probably time to move on?	2016-07-28 11:32:14 -04:00
Thomas Harte	481475a0f4	Switched to a full-on linear regression. Which causes the current tests to pass.	2016-07-14 19:42:01 -04:00
Thomas Harte	d1fe07f14d	Added test of perfect DPLL input timing.	2016-07-12 21:42:23 -04:00
Thomas Harte	94db45456e	Started sketching out the basic form here, albeit that it doesn't yet do _the only thing it advertises itself as useful for_.	2016-07-12 20:23:56 -04:00
Thomas Harte	75d95c0bc0	Sketched out an interface for a digial PLL. Not persuaded yet. Baby steps.	2016-07-11 22:12:58 -04:00