2368 Commits

Author	SHA1	Message	Date
Thomas Harte	7aeaa4a485	Tweak paging semantics, to allow simple multiple dependencies.	2022-06-27 21:38:45 -04:00
Thomas Harte	5cb0aebdf4	For the sake of poor Xcode, stop after a single failure.	2022-06-27 11:10:51 -04:00
Thomas Harte	686dccb48d	Correct comparison.	2022-06-26 21:49:58 -04:00
Thomas Harte	1f7700edac	Ensure proper register hits.	2022-06-26 21:20:57 -04:00
Thomas Harte	5adc656066	Make some attempt to use the JSON tests.	2022-06-25 21:41:37 -04:00
Thomas Harte	9cf64ea643	Import generated tests.	2022-06-25 16:46:57 -04:00
Thomas Harte	f2c2027a8c	Disable test generation for commit.	2022-06-24 16:50:23 -04:00
Thomas Harte	ef5ac1442f	Don't invent an address for STP and WAI.	2022-06-24 13:05:32 -04:00
Thomas Harte	1c1ce625a7	Vector reads signal VDA.	2022-06-24 10:37:39 -04:00
Thomas Harte	a442077eac	Allow repetition for MVN and MVP only.	2022-06-24 10:34:43 -04:00
Thomas Harte	6c638712f3	Attempt to capture MVP and MVN in their entirety.	2022-06-24 07:39:58 -04:00
Thomas Harte	2e7afb13c7	Exit gracefully upon a STP or WAI.	2022-06-23 21:03:40 -04:00
Thomas Harte	65140b341d	Simplify slightly, per new S reporting rule.	2022-06-22 16:43:00 -04:00
Thomas Harte	2f684ee66d	Use null for values that were never loaded.	2022-06-21 21:47:18 -04:00
Thomas Harte	ab0c290489	Use 'x' instead of 'i'.	2022-06-19 06:58:23 -04:00
Thomas Harte	15ac2c3e5a	Output to files, at volume, with extended bus flags.	2022-06-18 22:00:50 -04:00
Thomas Harte	0c24a27ba6	Completely prints tests.	2022-06-18 21:32:50 -04:00
Thomas Harte	eb82e06fab	Add randomised initial state, fix PC.	2022-06-18 19:21:56 -04:00
Thomas Harte	f8e6954739	Ensure complete runs of each tested opcode.	2022-06-18 16:26:40 -04:00
Thomas Harte	b62f484d93	Start scaffolding a 65816 test generator.	2022-06-18 13:28:15 -04:00
Thomas Harte	6cc41d6dda	Restore 1000 test count.	2022-06-14 22:02:53 -04:00
Thomas Harte	d91f8a264e	Flip presumption, reenabling most tests.	2022-06-14 21:57:14 -04:00
Thomas Harte	e066546c13	Resolve PEA timing errors.	2022-06-13 14:08:42 -04:00
Thomas Harte	7dc66128c2	Fix strobe output.	2022-06-13 10:49:47 -04:00
Thomas Harte	e484e4c9d7	Expand test to make sure that correct data strobes are active.	2022-06-13 10:39:06 -04:00
Thomas Harte	f316cbcf94	The old implementation was correct.	2022-06-11 21:15:08 -04:00
Thomas Harte	0a6b2b7d32	Verify newer CMPA.l, RTE, TRAP[V] and CHK.	2022-06-11 11:17:18 -04:00
Thomas Harte	c3345dd839	Fix MOVEM timing.	2022-06-10 21:52:07 -04:00
Thomas Harte	917b7fbf80	Notarise won't fix status of CLR, NEGX, NEG, NOT.	2022-06-10 16:50:38 -04:00
Thomas Harte	97715e7ccc	Expand test set to include those with timing discrepancies.	2022-06-10 16:34:05 -04:00
Thomas Harte	43c0dea1bd	With the difference in RESET times now factored out, test timing too.	2022-06-10 16:12:54 -04:00
Thomas Harte	2e4652209b	Remove entire RESET sequence, move to testing PEA.	2022-06-10 15:57:54 -04:00
Thomas Harte	e2d811a7a0	Notarise digressions that appear to be correct, remove now-working RTE/RTR.	2022-06-09 21:48:15 -04:00
Thomas Harte	dd5c903fd6	DIVS also appears sometimes to differ.	2022-06-09 20:19:39 -04:00
Thomas Harte	2e1675066d	Reinstate address error non-testing.	2022-06-09 16:59:06 -04:00
Thomas Harte	be84ce657b	Add an optional testing whitelist.	2022-06-09 16:18:04 -04:00
Thomas Harte	64053d697f	Take improved guess at address error stacking order.	2022-06-09 16:17:09 -04:00
Thomas Harte	a59ad06438	Print out summary of failure.	2022-06-09 13:13:33 -04:00
Thomas Harte	5af03d74ec	Add note to self about first diagnosis.	2022-06-09 12:21:39 -04:00
Thomas Harte	ba2803c807	Include all bus activity after the split.	2022-06-09 11:30:22 -04:00
Thomas Harte	fdcbf617d8	Avoid STOP.	2022-06-09 08:42:31 -04:00
Thomas Harte	cc7a4f7f91	Fix test build.	2022-06-08 21:15:11 -04:00
Thomas Harte	2e42bda0a3	Permit instructions that end in an address error to differ in transactions.	2022-06-08 16:15:33 -04:00
Thomas Harte	168dc12e27	Avoid spurious mismatches.	2022-06-08 16:03:02 -04:00
Thomas Harte	fd1955e15b	Attempt to randomise and test register contents.	2022-06-08 15:12:47 -04:00
Thomas Harte	f4f93f4836	Test a single, whole instruction; record read/write.	2022-06-08 14:53:04 -04:00
Thomas Harte	dd0a7533ab	Randomise all parts of memory other than the opcode.	2022-06-08 14:43:51 -04:00
Thomas Harte	50130b7004	Minor layout tweak.	2022-06-08 11:42:42 -04:00
Thomas Harte	ab52c5cef2	Pass first all-zeroes test, establishing that processors aren't being fully reset.	2022-06-08 10:56:54 -04:00
Thomas Harte	c7fa93a5bc	Attempt human-legible explanation of differences encountered.	2022-06-08 10:51:05 -04:00