Thomas Harte
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7f824d6494
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Ensured seeks and recalibrates end immediately if no seeking is required.
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2017-08-07 10:31:32 -04:00 |
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Thomas Harte
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3219212f03
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A closer inspection of the data sheet seems to suggest that invalid command sequences will post ST0.
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2017-08-07 07:35:41 -04:00 |
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Thomas Harte
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d90e35e5bd
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Added a bunch of comments, and ensured that the data request bit remains set for the entire period that command bytes are accepted.
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2017-08-07 07:27:00 -04:00 |
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Thomas Harte
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73f8488150
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Reaching the end of the usable part of my day, decided to tidy up a little before bed with indentation that reflects a distinction between top-level entry points and mere loops.
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2017-08-06 22:14:18 -04:00 |
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Thomas Harte
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3853966a1e
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Removed formal storage of ST3, as it just seems to be composed live. This may turn out also to be the best way to deal with ST0–2, time will tell. Also took a stab at the error in responding properly to the ROM's intended use of seek might be accepting new commands as replacements for old ones rather than rejecting them. That didn't seem to do the trick.
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2017-08-06 22:10:12 -04:00 |
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Thomas Harte
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d63893a437
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Collapsed implementations of recalibrate and seek, and decided to intend to go for an upward count on steps taken rather than a downward one. But seek continues presently to fail.
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2017-08-06 21:52:52 -04:00 |
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Thomas Harte
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90c74043f5
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Remembered to toggle off RQM between bytes. CAT now works.
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2017-08-06 21:21:59 -04:00 |
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Thomas Harte
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600445d90a
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Made a first attempt to return sector contents.
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2017-08-06 20:40:29 -04:00 |
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Thomas Harte
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e4b405fd3d
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With the ROM now using a read ID to set its expectations, implemented that and fixed FIND/READ_HEADER macros for multiple use. Execution now reaches the unimplemented section of read data.
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2017-08-06 20:32:46 -04:00 |
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Thomas Harte
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3b7ecbdf0d
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Renamed result_ to result_stack_ to emphasis the fact that it goes backwards. Switched meaning of CB so that it is set for the entire command, execution and result phases.
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2017-08-06 20:17:12 -04:00 |
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Thomas Harte
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01efb645cb
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Took a reasonable gamble that the CHRN reported is from internal registers, not from the last-found header.
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2017-08-06 19:57:34 -04:00 |
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Thomas Harte
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b5ec1f42d5
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Started resetting 'busy' when entering the result phase. AMSDOS now complains of a missing disk after failing to find sector 01. My belief is that it should end up asking for C1. So this is not even getting through a failure to find a sector correctly yet.
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2017-08-06 19:48:17 -04:00 |
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Thomas Harte
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e9972aa0dd
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Added respect for the index-hole limit on reading, and an error phase.
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2017-08-06 19:25:44 -04:00 |
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Thomas Harte
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1c9a744b01
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Made an effort to start inspecting ID fields, at least. Discovered that my emulation has somehow stopped proceeding beyond sense interrupt status though. Fix one in that area: adjust ST0 just in time for the sense interrupt status response, as that'll need to specify the drive number properly.
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2017-08-06 18:06:20 -04:00 |
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Thomas Harte
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e6d4bb29d8
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Discovered correct sense interrupt status result if nobody is in the completed seeking state, and switched to it. It's a single 0x80 rather than two bytes.
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2017-08-06 15:34:33 -04:00 |
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Thomas Harte
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6c5b562d97
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Made an attempt at some of the correct seek/recalibrate behaviour: it's now asynchronous from command processing and able to work on up to four drives at once. I just probably am not yet hitting all the status flags I need to hit.
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2017-08-06 15:22:07 -04:00 |
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Thomas Harte
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a7103f9333
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Disks are now communicated to the 8272. Which is able to handle four of them.
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2017-08-06 13:24:14 -04:00 |
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Thomas Harte
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c12425e141
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Added storage for the extended four status registers, and made an attempt at implementing the two most trivial result-phase commands. Am slightly paused momentarily trying to figure out whether seek activity is orthogonal to read/write activity.
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2017-08-06 12:55:57 -04:00 |
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Thomas Harte
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89f6de1383
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Started on a real ugly-implementation coroutine approach, and implemented specify as a fairly trivial first command: it has no result phase, and is the only thing called by AMSDOS as part of the initialisation sequence.
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2017-08-06 12:36:18 -04:00 |
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Thomas Harte
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34eaf75352
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Fixed WAIT_FOR_TIME macro.
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2017-08-06 12:08:54 -04:00 |
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Thomas Harte
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29288b690e
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Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller.
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2017-08-06 09:45:16 -04:00 |
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Thomas Harte
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25fd3f7e50
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Mildly increased work in here, still primarily oriented towards logging what I actually need to get done.
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2017-08-05 22:26:59 -04:00 |
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Thomas Harte
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3e984e75b6
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Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.
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2017-08-05 19:45:52 -04:00 |
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Thomas Harte
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26ce6cdab2
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Permitted register 3 to dictate vertical sync length.
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2017-08-04 08:56:36 -04:00 |
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Thomas Harte
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3ca9c38777
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Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc.
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2017-08-02 19:45:58 -04:00 |
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Thomas Harte
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0267bc237f
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Added the ability to set a port input, and relaxed bus state testing. I think my on-demand bus reactions here are inappropriate, so more work to do here probably.
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2017-08-01 18:04:51 -04:00 |
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Thomas Harte
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e6854ff8db
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Corrected typo: the input to an AY is BDIR, not BCDIR.
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2017-08-01 17:06:57 -04:00 |
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Thomas Harte
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2d4e202be3
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Completed dangling comment.
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2017-08-01 17:01:36 -04:00 |
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Thomas Harte
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64da8e17d1
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Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended.
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2017-08-01 17:01:20 -04:00 |
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Thomas Harte
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08ad35efd9
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It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
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2017-08-01 16:34:13 -04:00 |
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Thomas Harte
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58b98267fc
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Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
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2017-08-01 16:15:19 -04:00 |
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Thomas Harte
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ace71280a0
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Removed implementation file; this is only ever going to be a template.
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2017-08-01 16:00:17 -04:00 |
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Thomas Harte
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1d99c116e7
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Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.
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2017-08-01 15:29:37 -04:00 |
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Thomas Harte
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ee27e16fb1
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Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.
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2017-08-01 15:19:25 -04:00 |
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Thomas Harte
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3b1db14817
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Made a quick attempt at properly updating the refresh address.
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2017-08-01 07:36:03 -04:00 |
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Thomas Harte
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e3f677fa37
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I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.
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2017-07-31 22:21:46 -04:00 |
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Thomas Harte
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5c68b6cc21
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Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.
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2017-07-31 22:16:08 -04:00 |
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Thomas Harte
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ffaa627820
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Fixed frame restart when there is no adjustment period.
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2017-07-31 22:13:45 -04:00 |
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Thomas Harte
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5a396f6787
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Added an explicit cast.
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2017-07-31 22:04:31 -04:00 |
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Thomas Harte
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cb0dc7b434
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I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
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2017-07-31 22:01:54 -04:00 |
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Thomas Harte
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e28829bd1b
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Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
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2017-07-31 20:14:46 -04:00 |
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Thomas Harte
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68ceeab610
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Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
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2017-07-31 19:56:59 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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1da24d10fd
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Corrected a couple of build errors.
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2017-07-27 08:05:14 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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1c2f68f129
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Removed, as it's been relocated.
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2017-07-25 20:43:05 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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a1e9a54765
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Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
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2017-07-25 20:09:13 -04:00 |
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Thomas Harte
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545683df6f
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Added some documentation, got explicit again about cycle/half-cycle intermingling, and added flush as what amounts to divide(1), for cleaner usage without a clock divider.
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2017-07-25 19:50:40 -04:00 |
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Thomas Harte
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cfbd62a5dc
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Attempted to fix implementation of divide, and marked everything as-yet unmarked as inline.
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2017-07-25 07:43:39 -04:00 |
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