Thomas Harte
b306776ba9
Removes from 6502.hpp all remaining implementation details, making it purely an interface document.
...
Though those details remain visible to files including 6502.hpp through necessity.
2017-09-01 19:46:29 -04:00
Thomas Harte
4af333d5ec
Tidies the 6502 template and folder hierarchy.
...
Specifically: there's now just the one .h file at the top level, giving a clear indication of what a user should read. That separates implementation from interface. It also devolves a lot more to the base class because doing so makes debug builds less of a hassle. The all-RAM 6502 has been shuffled off into a subfolder, to indicate that it's not something you necessarily need know about. Also general documentation improvements have been applied: incorrect citing of the recurring-template pattern has been removed and the meaning of the two BusHandler methods has now accrued at the bus handler.
2017-08-31 22:10:27 -04:00
Thomas Harte
f10be2a18a
Eliminates potential cyclic entry into CSMachine during its -dealloc.
...
Explicit cause: dealloc calls close_output(). That may decide to flush work, indiscriminately. Some of the flushed work might be audio generation. Audio generation might cause the audio queue to react with an out-of-data announcement. Which would cause a fresh attempt to update the CSMachine.
2017-08-31 21:22:23 -04:00
Thomas Harte
d06031dfcb
Removes the options panel for CPC display.
2017-08-27 17:11:35 -04:00
Thomas Harte
4a66dd9e82
Arranges for the ZX80/81 to get a peek at target configuration prior to construction. I'm as yet undecided on whether to make this the norm.
2017-08-27 16:42:16 -04:00
Thomas Harte
522839143f
Revokes -[CSMachine init] and the slightly troubling create-on-demand semantics it places upon subclasses via .machine. Therefore each machine must announce its own implementation of -init.
2017-08-27 16:36:21 -04:00
Thomas Harte
9aa150c338
Abstracts the target platform type out from the static analyser's ownership.
2017-08-27 15:02:13 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
49285e9caa
Attempted to implement Sleeper in Drive and therefore in DiskController. Also corrected a couple of nonconformant file names.
2017-08-20 11:54:54 -04:00
Thomas Harte
cedb809c21
Sketched out a protocol designed to save processing time on anything that may sleep — probably just disk controllers for now but one can easily imagine it being applicable to printers, and possibly sound chips with suitable changes in guarantee for sound packet receivers.
2017-08-20 10:53:25 -04:00
Thomas Harte
e6683e7f2d
Added the base skeletal stuff of HFE support.
2017-08-17 21:48:48 -04:00
Thomas Harte
378f231499
Fully wired in drag-and-drop for media insertion.
2017-08-17 11:00:08 -04:00
Thomas Harte
f68565a33f
Split the static analyser functionality so that it's possible just to ask for the set of media implied by a particular file. Extended ConfigurationTarget so that media alone can be pushed to a machine.
2017-08-17 10:48:29 -04:00
Thomas Harte
4c15e46fd1
Performed the normative removal from public view of Vic-20 implementation details. Which were hefty.
2017-08-16 16:05:30 -04:00
Thomas Harte
75208b0762
Moves the Electron implementation behind a more opaque interface, in line with changes elsewhere.
2017-08-16 15:33:40 -04:00
Thomas Harte
de1c526789
Cut the amount disclosed by the Atari 2600 for public inspection down to the minimum, relocating implementation into the .cpp.
2017-08-16 14:52:40 -04:00
Thomas Harte
148591b7f2
Hid most of the Oric innards, and corrected a potential multi-thread access error emanating from the Mac side of the world.
2017-08-16 14:35:53 -04:00
Thomas Harte
06e31f5102
Consequential to the 6502 change, severs the Atari 2600's cartridge container from its former attempt at runtime polymorphism, in favour of each cartridge's specific hardware being defined as a 'bus extender'.
2017-08-16 12:39:15 -04:00
Thomas Harte
3947347d88
Introduces active input handling for the AY and uses it in the CPC to give proper, active keyboard input, rather than push-on-select, which was only ever a temporary hack. Also maps a few more keys for the Amstrad.
2017-08-15 22:47:17 -04:00
Thomas Harte
6cfc3daacb
Introduced a test within the disk controller so as not to request illegal tracks from disks, instead automatically substituting an 'unformatted' track. Which is just empty.
2017-08-15 21:52:12 -04:00
Thomas Harte
2d81acb82e
Upped C++ standard to C++14 and added an #if that's intended to use the built-in std::gcd when compiled on C++17 or better. Fixed for new signedness warnings resulting for taking the step to C++14.
2017-08-11 19:18:45 -04:00
Thomas Harte
570d25214e
Made an initial attempt at typer support for the CPC.
2017-08-11 11:21:07 -04:00
Thomas Harte
6a65c7a52a
Started working on a CPC-oriented analyser; for now I just want to be able to make a good guess at the appropriate file to load from a disk. As it turns out, the CPC simply adopts the CP/M format, so a generic parser is appropriate. This is its beginning.
2017-08-10 17:10:21 -04:00
Thomas Harte
ad8c8166bc
Built in gamma conversion for all machines, assuming an output of 2.8 for PAL, 2.2 for NTSC.
2017-08-10 15:17:08 -04:00
Thomas Harte
4d60b8801c
Started trying to factor out just the PLL stream -> FM/MFM events part that is presently in the WD1770.
2017-08-05 22:26:15 -04:00
Thomas Harte
3e984e75b6
Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.
2017-08-05 19:45:52 -04:00
Thomas Harte
75c59fefab
Added an empty husk to begin support for Amstrad CPC disk image formats.
2017-08-05 10:02:10 -04:00
Thomas Harte
bbb17acf3a
Expanded interface so that an external machine caller can request a string be typed without any knowledge of whatever it intends to do re: CharacterMappers. Which is immediately useful in paste functionality.
2017-08-03 11:50:50 -04:00
Thomas Harte
ad3a98387f
Within the Typer framework: hatched out CharacterMapper as a distinct thing from the target for keypresses, better to formalise responsibility but also to make it easy cleanly to sever that stuff into its own little part.
2017-08-03 11:42:31 -04:00
Thomas Harte
681d1e2f8d
Breaking its typer for now, adapted the ZX80/81 to having a Z80, not being one.
2017-08-02 22:12:59 -04:00
Thomas Harte
6ca07f1e28
I guess it might end up living somewhere else, but introduced a header with the compiler-specific stuff to allow me to force things inline.
2017-08-01 22:04:58 -04:00
Thomas Harte
9d43784c65
Significantly increased quantity of keys forwarded.
2017-08-01 20:37:55 -04:00
Thomas Harte
f5b278d683
Added enough stuff to put the emulated Amstrad CPC in a state of knowing whether its '0' key is pressed.
2017-08-01 17:31:56 -04:00
Thomas Harte
08ad35efd9
It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
2017-08-01 16:34:13 -04:00
Thomas Harte
58b98267fc
Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
2017-08-01 16:15:19 -04:00
Thomas Harte
ace71280a0
Removed implementation file; this is only ever going to be a template.
2017-08-01 16:00:17 -04:00
Thomas Harte
2b168f7383
Disabled the address sanitiser as an every-time run again, as it just pushes my computer a bit too far.
2017-07-31 22:32:56 -04:00
Thomas Harte
0536f089e1
Eliminated old-[personal-]fashioned line break.
2017-07-31 22:32:26 -04:00
Thomas Harte
3df13cddd4
As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details.
2017-07-31 22:32:04 -04:00
Thomas Harte
68ceeab610
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 19:56:59 -04:00
Thomas Harte
afd409c883
Ensured that ROM images are loaded and passed to the Amstrad CPC.
2017-07-31 18:44:49 -04:00
Thomas Harte
26b6c03a2a
Re-enabled the address sanitiser as a development tool.
2017-07-31 07:30:07 -04:00
Thomas Harte
c0f1313830
Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.
2017-07-30 22:05:29 -04:00
Thomas Harte
5b5720fac0
Added to the static analyser the most basic through-path for Amstrad CPC content.
2017-07-30 21:15:20 -04:00
Thomas Harte
d25d7d7d40
Added the Amstrad CPC as a named target and declared support for its CDT file format.
2017-07-29 21:56:33 -04:00
Thomas Harte
761afad118
Corrected timestamp return, and its testing by the 6502 timing tests.
2017-07-27 21:19:16 -04:00
Thomas Harte
37950143fc
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-27 20:17:13 -04:00
Thomas Harte
9257a3f6d7
Added test for 16-bit arithmetic, and fixed implementation.
2017-07-26 19:04:52 -04:00
Thomas Harte
728143247d
Added a test for RLD and RRD. Which already passes.
2017-07-26 18:56:35 -04:00
Thomas Harte
6ec4e4e3d7
Merge branch 'master' into Memptr
2017-07-25 23:01:34 -04:00
Thomas Harte
37ccb9d3b6
Fixed 6502 timing tests.
2017-07-25 23:00:39 -04:00
Thomas Harte
3c254360ba
Completed fixture of the 6502 BCD test.
2017-07-25 22:55:45 -04:00
Thomas Harte
3ca51bedc6
Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.
2017-07-25 22:48:44 -04:00
Thomas Harte
36076b7ea5
Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.
2017-07-25 22:38:26 -04:00
Thomas Harte
279c369a1f
Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
2017-07-25 22:21:09 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
df4732be2e
Corrected test.
2017-07-24 22:33:49 -04:00
Thomas Harte
9435c1e12a
The 1540 is now a ClockReceiver.
2017-07-24 22:32:41 -04:00
Thomas Harte
2912d7055b
The 6532 is now a ClockReceiver.
2017-07-24 21:57:24 -04:00
Thomas Harte
13f7aa4063
The TIA is now a ClockReceiver.
2017-07-24 21:48:34 -04:00
Thomas Harte
b3ae920746
Converted the DPLL and disk controller classes to be ClockReceivers.
2017-07-24 21:04:47 -04:00
Thomas Harte
e6578defcd
It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.
2017-07-23 22:22:50 -04:00
Thomas Harte
ace8e30818
Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
2017-07-23 22:21:39 -04:00
Thomas Harte
b0c2325adc
Corrected run call, and accepted that jam handling is gone forever.
2017-07-22 22:21:26 -04:00
Thomas Harte
2ff157cf7a
Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
2017-07-22 22:17:29 -04:00
Thomas Harte
1ba3f262a2
Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
2017-07-22 21:46:50 -04:00
Thomas Harte
4ea835e50b
Added test for EX (SP), rp, which passes.
2017-07-22 17:17:32 -04:00
Thomas Harte
5fddbec132
Merge branch 'master' into Memptr
2017-07-22 17:06:22 -04:00
Thomas Harte
6633537fb8
Discovering that there is such a thing as P81 — a ZX81 file without the name omitted — added support for it. Extended FileHolder while I was here to retain the file name and be able to supply its extension, as my quick-fix test-the-last-character approach to o/p/80/81 discrimination stops working with p81 thrown into the mix and this feels like the correct factoring.
2017-07-22 16:02:25 -04:00
Thomas Harte
6437c43147
Added CPI and CPD tests: at last two that pass without requiring implementation changes!
2017-07-22 12:38:18 -04:00
Thomas Harte
5928a24803
Transcribed missing tests as TODOs.
2017-07-22 11:44:17 -04:00
Thomas Harte
20a6bcc676
Added tests for the various LD (nn), rr instructions and corrected implementation to pass.
2017-07-22 11:39:13 -04:00
Thomas Harte
eaf313b0f6
Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.
2017-07-22 11:20:21 -04:00
Thomas Harte
d51b66c204
Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.
2017-07-21 23:01:35 -04:00
Thomas Harte
660f0e4c40
Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.
2017-07-21 22:52:25 -04:00
Thomas Harte
2b5d0877a8
Adjusted parameter name to match documentation. I think it's a carry-over from before I was passing the whole event along.
2017-07-21 21:27:50 -04:00
Thomas Harte
2a7fc86b15
Enabled stricter warnings.
2017-07-21 20:44:35 -04:00
Thomas Harte
8f72fc4a44
Factored out from the UEF implementation the concept of being a tape that has a queue of pending pulses and manages that queue.
2017-07-16 22:04:40 -04:00
Thomas Harte
238348c885
Performed the initial wiring to announce that this application supports TZX files and to route them to the ZX80/81 static analyser. The TZX class itself does not yet do much beyond basic validation. I think it'll be easiest if it follows in UEF's footsteps in queuing up pulses ahead of time, so some factoring out is now required.
2017-07-16 21:33:11 -04:00
Thomas Harte
7b5f93510b
Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
2017-07-16 20:55:57 -04:00
Thomas Harte
8ddd686049
Removed redundant variable.
2017-07-16 19:04:03 -04:00
Thomas Harte
2fb0aea990
Updated the C1540 test vessel to the new world.
2017-07-16 17:00:39 -04:00
Thomas Harte
279f4760d7
Eliminated buffer_size_ as something explicitly stored, and reduced size of delegate call out.
2017-07-16 15:01:39 -04:00
Thomas Harte
368bff1a82
Added a shell class that will one day be able to parse CSW files, plus the logic and metadata to instantiate it when a CSW presents itself.
2017-07-10 21:43:58 -04:00
Thomas Harte
3e5c209039
Added basic Typer support for the ZX80 and '81.
2017-07-09 22:00:34 -04:00
Thomas Harte
54efcb7e2f
Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults.
2017-07-08 19:31:20 -04:00
Thomas Harte
e2575d6de4
Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly.
2017-07-08 19:21:12 -04:00
Thomas Harte
23e989e170
This will likely do for the Swift/XIB side of things: the play/pause button is enabled or disabled as per the user's choice of automatic tape control, and toggles function when pressed. It communicates activity down to the Objective-C[++] layer, giving it a route through to the actual machine.
2017-07-08 19:12:06 -04:00
Thomas Harte
28412150e6
Added controls for controlling the tape motor of the ZX80/81, assuming I can find an automatic option.
2017-07-08 17:59:33 -04:00
Thomas Harte
cb105fdeb4
Took a first stab at high-res support.
2017-06-22 22:48:17 -04:00
Thomas Harte
aec4fd066b
I think I've definitively decided against this model of timing.
2017-06-22 21:32:14 -04:00
Thomas Harte
95a6b0f85c
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-22 21:09:26 -04:00
Thomas Harte
644ef13acd
Connected up the fast-tape GUI option for the ZX80 and '81.
2017-06-22 20:20:31 -04:00
Thomas Harte
0e0ce379b4
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505
Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
2017-06-21 20:32:08 -04:00
Thomas Harte
108da64562
Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
2017-06-20 22:25:00 -04:00
Thomas Harte
184b371649
Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
2017-06-20 21:48:50 -04:00
Thomas Harte
27ac342928
Corrected conditional call timing, and its test.
2017-06-20 20:57:23 -04:00
Thomas Harte
6752f165db
Added failing tests for both kinds of CALL.
2017-06-19 22:03:29 -04:00
Thomas Harte
e05076b258
Added tests for everything except CALL. All passing.
2017-06-19 22:00:04 -04:00
Thomas Harte
fadbfdf801
Added DJNZ test.
2017-06-19 21:31:56 -04:00
Thomas Harte
cb277b8d1e
Added JP and JR tests.
2017-06-19 21:27:23 -04:00
Thomas Harte
234f14dbbe
Tests were at fault; all passing now.
2017-06-19 21:14:40 -04:00
Thomas Harte
99ede3a9ef
BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
2017-06-19 21:04:14 -04:00
Thomas Harte
378233f53d
Extended to BITs and SETs, accruing three new failures.
2017-06-19 21:01:30 -04:00
Thomas Harte
f903408980
Caught up on comments.
2017-06-19 20:53:22 -04:00
Thomas Harte
b684254908
Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
2017-06-19 20:33:34 -04:00
Thomas Harte
351d90ca55
Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
2017-06-19 20:04:55 -04:00
Thomas Harte
23177df26a
Added various tests of the basic ALU ops.
2017-06-19 19:53:26 -04:00
Thomas Harte
ba15371948
Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
2017-06-19 19:47:00 -04:00
Thomas Harte
8d60734737
Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
2017-06-19 19:17:54 -04:00
Thomas Harte
002098d496
The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
2017-06-19 07:45:41 -04:00
Thomas Harte
85c5c4405a
Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
2017-06-19 07:30:01 -04:00
Thomas Harte
d668879ba6
Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
2017-06-18 22:03:13 -04:00
Thomas Harte
e1a2580b2a
Renamed BusOperation to MachineCycle::Operation.
2017-06-17 21:53:45 -04:00
Thomas Harte
b6f51474ff
Ensured that -description can handle the newly-captured bus actions.
2017-06-17 18:20:30 -04:00
Thomas Harte
0f18768091
Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
2017-06-17 18:19:25 -04:00
Thomas Harte
50cd617bd9
Ensured test raises only the intentional failure exceptions.
2017-06-15 22:33:46 -04:00
Thomas Harte
838b818cd3
Finished transcribing first page of machine cycle documentation; several failures contained.
2017-06-15 22:19:49 -04:00
Thomas Harte
cf795562bf
Continued filling in tests, fleshing out what the test machine captures as a result.
2017-06-15 20:59:59 -04:00
Thomas Harte
ac37424878
Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
2017-06-15 19:06:59 -04:00
Thomas Harte
aed2827e7b
Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
2017-06-12 22:22:00 -04:00
Thomas Harte
a48616a138
Fixed reference to Swift-world MachineDocument for the ZX81 file type.
2017-06-12 18:51:11 -04:00
Thomas Harte
8222aac9e3
Added an official declaration of support for ZX81 files.
2017-06-11 21:40:41 -04:00
Thomas Harte
77aa3c187e
Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately.
2017-06-11 21:38:32 -04:00
Thomas Harte
8116f85479
Allowed the static analyser to specify a ZX80 or 81, and a memory model. Neither is respected yet in the machine.
2017-06-11 19:12:20 -04:00
Thomas Harte
50be3a24fe
Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.
2017-06-11 13:30:08 -04:00
Thomas Harte
7e10c7f9d8
Relocated the ZX80/81 concept of a 'file' out from Tape into Data, given that it's an exact duplicate of memory.
2017-06-08 19:09:51 -04:00
Thomas Harte
60300851ea
Started sketching out a tape parser for ZX80 and '81 files. I think this'll help me to verify whether the .O input is working.
2017-06-07 10:12:13 -04:00
Thomas Harte
8c66e1d99d
Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.
2017-06-06 17:53:23 -04:00
Thomas Harte
cc4cb45e9d
Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.
2017-06-06 09:25:18 -04:00
Thomas Harte
c485c460f7
Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.
2017-06-04 18:08:35 -04:00
Thomas Harte
b0a7c58287
Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents.
2017-06-04 17:57:37 -04:00
Thomas Harte
d2637123c4
Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
2017-06-04 17:55:19 -04:00
Thomas Harte
02b7c3d1b0
Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target.
2017-06-04 17:04:06 -04:00
Thomas Harte
8c1769f157
Made a quick attempt at serialising from ZX80 .O to waves.
2017-06-04 16:59:26 -04:00
Thomas Harte
655809517c
Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required.
2017-06-04 16:37:03 -04:00
Thomas Harte
2190f60a89
Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.
2017-06-04 15:46:35 -04:00
Thomas Harte
0eebfdb4cc
Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
2017-06-04 15:39:37 -04:00
Thomas Harte
7811374b0f
Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
2017-06-04 15:07:07 -04:00
Thomas Harte
87095b0578
Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.
2017-06-04 14:04:26 -04:00
Thomas Harte
b642d9f712
Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5
Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
2017-06-03 21:22:16 -04:00
Thomas Harte
b304c3a4b9
Eliminated the 6502's reliance on the micro-op scheduler.
2017-06-03 20:30:07 -04:00
Thomas Harte
b3da16911f
Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
2017-06-03 18:42:54 -04:00
Thomas Harte
e52892f75b
Added a test of interrupt mode 1.
2017-06-03 18:16:13 -04:00
Thomas Harte
8c41a0f0ed
Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.
2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff
Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
2017-06-03 17:41:45 -04:00
Thomas Harte
d14902700a
Minor syntax and wiring fixes.
2017-06-01 22:33:05 -04:00
