Thomas Harte
9d7d45338f
Ostensibly gets the instruction stream correct for test case 1.
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Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-05 21:34:35 -05:00
Thomas Harte
3b55d3f158
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-05 21:25:12 -05:00
Thomas Harte
fda2293d6b
Improves constness.
2021-01-04 22:36:39 -05:00
Thomas Harte
38bca5f0f0
Finally runs into the wall of trying to merge operands and offsets.
2021-01-03 20:08:13 -05:00
Thomas Harte
29cf96c703
Adds decoding of disp16 RETs.
2021-01-03 19:39:28 -05:00
Thomas Harte
782dc3d046
Distinguishes inter- and intra-segment RET.
2021-01-03 19:37:37 -05:00
Thomas Harte
0ae217f51d
Improves exposition, adds decoding of the 0xbx patch of MOVs.
2021-01-03 19:33:16 -05:00
Thomas Harte
adcb2e03e8
Attempts to consolidate source/destination ordering.
2021-01-03 17:28:29 -05:00
Thomas Harte
11b6c1d4b5
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 17:03:50 -05:00
Thomas Harte
367cb1789d
Starts building an x86 test.
2021-01-03 16:37:35 -05:00
Thomas Harte
5401ff6c78
Proactively fixes li sign extension.
2021-01-03 11:14:43 -05:00
Thomas Harte
c934e22cee
Introduces a first test of PowerPC decoding.
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Corrected as a result: the bcx conditional, that stdu is 64-bit only, extraction of the li field.
2021-01-02 22:47:42 -05:00
Thomas Harte
1a3effc692
Modifies contract again. This is why I'm doing this now.
2021-01-02 21:19:45 -05:00
Thomas Harte
32c942d154
Muddles drunkenly towards decoding ModRM.
2021-01-02 21:11:19 -05:00
Thomas Harte
9c5dc0ed29
Deferring ModRM work, proceeds to 0x9f.
2021-01-02 19:29:43 -05:00
Thomas Harte
290972cedf
Adds health warning.
2021-01-02 19:16:21 -05:00
Thomas Harte
dc9d370952
Does the easier part of the easier half of 8086 decoding.
2021-01-02 19:16:07 -05:00
Thomas Harte
a41be61f99
Slightly fleshes out models, for a sensible beginning.
2021-01-01 17:36:47 -05:00
Thomas Harte
3d1783ddae
Add exposition as to the purpose of decoders.
2021-01-01 17:32:57 -05:00
Thomas Harte
8151c8e409
Rounds out field list.
2021-01-01 16:38:40 -05:00
Thomas Harte
0ef42f93ff
Further rounds out decoder.
2021-01-01 11:46:26 -05:00
Thomas Harte
d318ab4e70
Edges further onwards.
2020-12-31 21:12:36 -05:00
Thomas Harte
ebfa35c2c7
Conquers another page of instructions; adds supervisor flag.
2020-12-31 18:14:38 -05:00
Thomas Harte
db50b0fe23
Gets started on 6+10 decoding, places stake as to other fields.
2020-12-31 16:51:31 -05:00
Thomas Harte
233a69a1d8
Decodes operations for the simplest 45.
2020-12-31 16:02:52 -05:00
Thomas Harte
ed63e7ea75
Starts building out a PowerPC decoder.
2020-12-30 22:55:59 -05:00
Thomas Harte
b3ab9fff9b
Imports a custom-built copy of Klaus Dormann's 65C02 test, with only 65816-compatible parts.
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Thereby fixes another couple of 65816 issues — BRK(, etc) not clearing the decimal flag, and `TRB d` being mismapped.
2020-10-19 19:27:16 -04:00
Thomas Harte
14718b93a4
Improve commentary.
2020-10-19 09:32:50 -04:00
Thomas Harte
76d9893866
Declares address-bus sizes formally.
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This allows me to fix the final two implicit conversion warnings, albeit that it would have been nice to find a templatey way just to get the type directly from the declaration of `perform_bus_operation`.
2020-10-18 15:08:21 -04:00
Thomas Harte
c3f8982c62
Resolves all internal implicit type-conversion warnings.
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Chasing those down, it looks like flags were wrong for PLB and PLD. So it's official: warnings help.
2020-10-18 14:55:17 -04:00
Thomas Harte
99eba2f8ba
Ensures intended 65816 exception behaviour.
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i.e. the relevant micro-op sequence exists, and its operation isn't lost. Also sets the 65816 by default to jump straight into power-on, not to execute an instruction first. That shouldn't make a functional difference, but it makes debugging easier because it makes startup fully deterministic.
2020-10-18 14:43:47 -04:00
Thomas Harte
e5f57ea743
Make isReadOperation more overt.
2020-10-17 22:27:04 -04:00
Thomas Harte
3b398f7a9a
Attempts to complete all 65816 bus signalling.
2020-10-16 21:56:20 -04:00
Thomas Harte
096add7551
Exposes non-BusOperation bus outputs.
2020-10-16 21:05:42 -04:00
Thomas Harte
334e0666b7
Reports ::Ready upon a WAI.
2020-10-15 21:37:37 -04:00
Thomas Harte
98c81749c8
Adds the conventional flush.
2020-10-15 21:36:04 -04:00
Thomas Harte
5dcf720bb5
Extends list of BusOperations.
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Now to retest, widely.
2020-10-15 21:35:01 -04:00
Thomas Harte
9c0c0255f6
Ensures data/program bank can't accidentally be set to 16-bit values.
2020-10-15 21:10:32 -04:00
Thomas Harte
68c15bd605
Updates Qt project; catches another couple of issues via its compiler.
2020-10-15 21:09:22 -04:00
Thomas Harte
9a2f32795f
Revokes stack-local storage non-optimisation.
2020-10-15 21:03:10 -04:00
Thomas Harte
7aa6cf4c6b
Tidies up layout very slightly.
2020-10-15 20:51:23 -04:00
Thomas Harte
dfda2adf0d
Attempts implementations of both ready and abort.
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Which I think concludes the inputs?
2020-10-15 20:46:18 -04:00
Thomas Harte
c0a1c34012
Wraps all registers into a struct, so that I can implement abort.
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Makes some preparations for ready too.
2020-10-15 18:42:38 -04:00
Thomas Harte
3c6adc1ff4
Completes 65816 addressing mode tests and corresponding fixes.
2020-10-14 22:00:52 -04:00
Thomas Harte
e511d33a7c
Adds test for [d], y; fixes implementation.
2020-10-14 21:42:41 -04:00
Thomas Harte
27afb8f0a7
Adds direct indirect long test, and thereby fixes addressing mode.
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Nine to go!
2020-10-14 21:26:20 -04:00
Thomas Harte
327ab81436
Fills in direct, x and (direct) tests, fixing implementation of the latter.
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10 to go.
2020-10-14 21:17:28 -04:00
Thomas Harte
b22aa5d699
Starts transcribing the addressing examples I have into tests.
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Correspondingly extends the exposed register set and test-machine addressing range.
2020-10-13 21:38:30 -04:00
Thomas Harte
3e6a2adaaf
Corrects absolute, x and absolute, y addressing modes.
2020-10-13 20:30:39 -04:00
Thomas Harte
8f5537aaaa
Attempts to resolve my direct-indirect addressing stumble.
2020-10-13 20:21:53 -04:00
