Thomas Harte
|
2d4e202be3
|
Completed dangling comment.
|
2017-08-01 17:01:36 -04:00 |
|
Thomas Harte
|
64da8e17d1
|
Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended.
|
2017-08-01 17:01:20 -04:00 |
|
Thomas Harte
|
08ad35efd9
|
It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
|
2017-08-01 16:34:13 -04:00 |
|
Thomas Harte
|
58b98267fc
|
Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
|
2017-08-01 16:15:19 -04:00 |
|
Thomas Harte
|
ace71280a0
|
Removed implementation file; this is only ever going to be a template.
|
2017-08-01 16:00:17 -04:00 |
|
Thomas Harte
|
1d99c116e7
|
Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.
|
2017-08-01 15:29:37 -04:00 |
|
Thomas Harte
|
ee27e16fb1
|
Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.
|
2017-08-01 15:19:25 -04:00 |
|
Thomas Harte
|
3b1db14817
|
Made a quick attempt at properly updating the refresh address.
|
2017-08-01 07:36:03 -04:00 |
|
Thomas Harte
|
e3f677fa37
|
I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.
|
2017-07-31 22:21:46 -04:00 |
|
Thomas Harte
|
5c68b6cc21
|
Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.
|
2017-07-31 22:16:08 -04:00 |
|
Thomas Harte
|
ffaa627820
|
Fixed frame restart when there is no adjustment period.
|
2017-07-31 22:13:45 -04:00 |
|
Thomas Harte
|
5a396f6787
|
Added an explicit cast.
|
2017-07-31 22:04:31 -04:00 |
|
Thomas Harte
|
cb0dc7b434
|
I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
|
2017-07-31 22:01:54 -04:00 |
|
Thomas Harte
|
e28829bd1b
|
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
|
2017-07-31 20:14:46 -04:00 |
|
Thomas Harte
|
68ceeab610
|
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
|
2017-07-31 19:56:59 -04:00 |
|
Thomas Harte
|
4abd62e62b
|
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
|
2017-07-27 22:05:29 -04:00 |
|
Thomas Harte
|
1da24d10fd
|
Corrected a couple of build errors.
|
2017-07-27 08:05:14 -04:00 |
|
Thomas Harte
|
8361756dc4
|
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
|
2017-07-27 07:40:02 -04:00 |
|
Thomas Harte
|
1c2f68f129
|
Removed, as it's been relocated.
|
2017-07-25 20:43:05 -04:00 |
|
Thomas Harte
|
75d67ee770
|
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
|
2017-07-25 20:20:55 -04:00 |
|
Thomas Harte
|
a1e9a54765
|
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
|
2017-07-25 20:09:13 -04:00 |
|
Thomas Harte
|
545683df6f
|
Added some documentation, got explicit again about cycle/half-cycle intermingling, and added flush as what amounts to divide(1), for cleaner usage without a clock divider.
|
2017-07-25 19:50:40 -04:00 |
|
Thomas Harte
|
cfbd62a5dc
|
Attempted to fix implementation of divide, and marked everything as-yet unmarked as inline.
|
2017-07-25 07:43:39 -04:00 |
|
Thomas Harte
|
40339a12e1
|
Formalised the use of a cycles count with a divider, bringing a few additional plain-int users into the fold.
|
2017-07-25 07:15:31 -04:00 |
|
Thomas Harte
|
9be9bd9106
|
Neatened layout.
|
2017-07-24 22:52:35 -04:00 |
|
Thomas Harte
|
c1527cc9e2
|
Reduced back-and-forth between Cycles and ints within the Oric.
|
2017-07-24 22:46:31 -04:00 |
|
Thomas Harte
|
a1a3aab115
|
Fixed implicit sign conversion.
|
2017-07-24 22:40:15 -04:00 |
|
Thomas Harte
|
c77a83d86f
|
The 6560 is now a ClockReceiver. This reduces to zero the number of remaining instances of the text run_for_cycles in this codebase.
|
2017-07-24 22:38:35 -04:00 |
|
Thomas Harte
|
efdac2ce8c
|
The 6522 is now a ClockReceiver.
|
2017-07-24 22:29:09 -04:00 |
|
Thomas Harte
|
2912d7055b
|
The 6532 is now a ClockReceiver.
|
2017-07-24 21:57:24 -04:00 |
|
Thomas Harte
|
b7f88e8f61
|
Filter is now a ClockReciever, affecting all sound output devices.
|
2017-07-24 21:29:13 -04:00 |
|
Thomas Harte
|
8a2bdb8d22
|
Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
|
2017-07-24 21:19:05 -04:00 |
|
Thomas Harte
|
b82bef95f3
|
Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
|
2017-07-24 20:10:05 -04:00 |
|
Thomas Harte
|
8a0b0cb3d7
|
Extended both classes to allow copy assignment, copy construction and implicit zero-length construction.
|
2017-07-23 22:13:41 -04:00 |
|
Thomas Harte
|
1ba3f262a2
|
Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
|
2017-07-22 21:46:50 -04:00 |
|
Thomas Harte
|
8755824c64
|
Added some documentation.
|
2017-07-22 17:25:53 -04:00 |
|
Thomas Harte
|
64865b3f41
|
Signedness fixes.
|
2017-07-21 21:23:34 -04:00 |
|
Thomas Harte
|
53f0e1896b
|
Made delay_time_ unsigned for safe comparison.
|
2017-07-21 21:21:23 -04:00 |
|
Thomas Harte
|
aaa60dab12
|
Fixed signedness of index.
|
2017-07-21 21:21:01 -04:00 |
|
Thomas Harte
|
12f7e1b804
|
Enshrined a default colour burst amplitude. Which now everybody relies on. The 102 figure is derived from the burst apparently being 40 IRE.
|
2017-07-07 23:35:14 -04:00 |
|
Thomas Harte
|
eb8a2de5d6
|
Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
|
2017-05-15 07:38:59 -04:00 |
|
Thomas Harte
|
e270b726b3
|
Tweaked blue, increased saturation.
|
2017-05-13 22:01:02 -04:00 |
|
Thomas Harte
|
44ce7fa54c
|
Corrected luminances across the board, and PAL colours.
|
2017-05-13 21:50:09 -04:00 |
|
Thomas Harte
|
b0142cf050
|
Made an updated stab at NTSC colours.
|
2017-05-13 14:29:36 -04:00 |
|
Thomas Harte
|
a340331229
|
Introduced 1-bit of saturation, returning black and white as black and white.
|
2017-05-11 21:31:58 -04:00 |
|
Thomas Harte
|
15d17c12d5
|
Switched the 6560 to two bytes per pixel, since one isn't sufficient for precision and because mixing up the implementation might help me to figure out what's amiss.
|
2017-05-09 21:22:01 -04:00 |
|
Thomas Harte
|
5998123868
|
Added some consts, for a minor safety improvement.
|
2017-05-06 19:53:24 -04:00 |
|
Thomas Harte
|
e01f3f06c8
|
Completed curly bracket movement.
|
2017-03-26 14:34:47 -04:00 |
|
Thomas Harte
|
a4c5eebd1e
|
The latest Atari Age-discovered numbers suggest this starts up in 1024T mode.
|
2017-03-21 18:22:50 -04:00 |
|
Thomas Harte
|
c445eaec3e
|
Switched startup values, following a comment on AtariAge. May or may not be correct, the thread was speculative.
|
2017-03-19 17:38:26 -04:00 |
|
Thomas Harte
|
e0bca1e37b
|
Reinstated the 16 and 32 kb Atari pagers, and ensured the 6532 always starts in a valid state.
|
2017-03-18 17:34:34 -04:00 |
|
Thomas Harte
|
d3257c345a
|
Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place.
|
2017-03-04 17:00:28 -05:00 |
|
Thomas Harte
|
e09b76bf32
|
Fixed 'same value, then immediate increment, then proper counting increments' behaviour and ensured it takes one cycle to commit a value. Adjusted tests to match.
|
2017-03-04 15:57:54 -05:00 |
|
Thomas Harte
|
ced644b103
|
It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock.
|
2017-01-11 22:03:01 -05:00 |
|
Thomas Harte
|
eca3995481
|
Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset.
|
2017-01-01 21:00:25 -05:00 |
|
Thomas Harte
|
044c920a5b
|
Made it more explicit that there are no unhandled cases.
|
2017-01-01 20:56:52 -05:00 |
|
Thomas Harte
|
0df9ce5a76
|
Made an attempt at read address. So superficially that leaves only the force interrupts.
|
2017-01-01 20:55:09 -05:00 |
|
Thomas Harte
|
f94f34f053
|
Made an attempt at read track. Which means process_input_bit can't just swallow syncs any more; it now reports them as tokens of type ::Sync.
|
2017-01-01 20:39:19 -05:00 |
|
Thomas Harte
|
c994fa39f6
|
Ensured spin-up doesn't occur if there's no motor line.
|
2016-12-31 16:18:30 -05:00 |
|
Thomas Harte
|
1ea4f0d79d
|
Made an attempt to implement 'write track' and ensure that 'write sector' can't end without announcing that it has ended writing.
|
2016-12-31 16:01:44 -05:00 |
|
Thomas Harte
|
8eb21c6702
|
The "MFM...Byte"s aren't MFM-specific, they're relevant to both FM and MFM encoding. So renamed them. Also slimmed syntax within MFM.cpp mostly where emigration from the Acorn disk analyser had left a residue of lengthy namespace specification.
|
2016-12-31 15:25:11 -05:00 |
|
Thomas Harte
|
a8bc9d830e
|
Removed leftover very temporary debugging aid.
|
2016-12-28 23:03:05 -05:00 |
|
Thomas Harte
|
e4000bd060
|
Added some even more verbose logging; slightly simplified write loop logic, and decided it's definitely write_byte that's responsible for CRC generator feeding.
|
2016-12-28 21:24:19 -05:00 |
|
Thomas Harte
|
4adcb46665
|
Fixed FM-mode CRC generation.
|
2016-12-28 19:51:27 -05:00 |
|
Thomas Harte
|
1277a67f9a
|
Introduced data_mode_ to replace is_reading_data_, representing that there are now three possible modes. When writing, any input from the read head won't affect the CRC generator.
|
2016-12-28 19:26:21 -05:00 |
|
Thomas Harte
|
7a627b782d
|
Reintroduced writing of MFM sync marks when writing a sector.
|
2016-12-28 18:48:50 -05:00 |
|
Thomas Harte
|
a568172758
|
Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.
|
2016-12-28 18:29:37 -05:00 |
|
Thomas Harte
|
9c0f622a2e
|
Started working CRC checking into the 1770. Discovered immediately that my generated CRC does not match that built into the Oric disk images. So mine is pretty-much certainly wrong. An opportunity for learning!
|
2016-12-26 16:46:26 -05:00 |
|
Thomas Harte
|
0490a47058
|
Worked on the all-around framework for decoding sectors back from tracks when closing down a file. Hit the wall that the parser is more observant of CRCs than the WD. No, really. So I guess I have to stop avoiding that whole issue.
|
2016-12-26 14:24:33 -05:00 |
|
Thomas Harte
|
83c433c142
|
Deviated from the data sheet, which seems likely to be correct. Hence removed a whole load of the temporary logging.
|
2016-12-26 12:48:49 -05:00 |
|
Thomas Harte
|
742c5df367
|
With lots of logging arising temporarily, fixed bug whereby conversion to a patched track would lead to holding a track with a distinct measure of time, leading to improperly-placed patches.
|
2016-12-25 22:00:39 -05:00 |
|
Thomas Harte
|
acc35885cd
|
Attempted to reduce track invalidations.
|
2016-12-25 20:38:25 -05:00 |
|
Thomas Harte
|
c0a1264ab0
|
Slightly improved legibility.
|
2016-12-25 20:19:47 -05:00 |
|
Thomas Harte
|
e2b829f68e
|
Made an attempt to write the proper address mark.
|
2016-12-25 20:15:07 -05:00 |
|
Thomas Harte
|
beaa868079
|
Factored the MFM parser out into encodings.
|
2016-12-25 20:00:57 -05:00 |
|
Thomas Harte
|
74e98fd097
|
Made an attempt to write actual data (albeit that CRC calculation is still missing).
|
2016-12-25 19:18:45 -05:00 |
|
Thomas Harte
|
98be6ede45
|
Shuffled a little to reduce risk of overflow, ensured writing is a loop, still seem to be writing too quickly for some reason.
|
2016-12-25 16:13:05 -05:00 |
|
Thomas Harte
|
d2ad2c756e
|
Added enough shovelling to write rubbish for an entire sector.
|
2016-12-25 15:46:49 -05:00 |
|
Thomas Harte
|
aceb7e3b6b
|
Started implementing write sector on the 1770, immediately deciding it would be useful to have a callback for end-of-queued-data-written from disk controller. So had a go at implementing that, naively. More investigation required.
|
2016-12-25 12:31:38 -05:00 |
|
Thomas Harte
|
901f19f89c
|
Added enough stuff that SSDs attached to a 1770 will now reach the entry point for writing.
|
2016-12-25 09:46:12 -05:00 |
|
Thomas Harte
|
c304db0f5a
|
Deintegrated the busy flag and the interrupt request line, as the latter is reset by status reads. Which also means I can start reporting the WD INTRQ line status directly from the Microdisc. That appears to be correct, rather than honouring the Microdisc IRQ select there.
|
2016-12-06 21:16:29 -05:00 |
|
Thomas Harte
|
ca50606e1d
|
Restored Vic audio.
|
2016-12-03 17:10:47 -05:00 |
|
Thomas Harte
|
36bc558798
|
Converted all 'Components' to postfix underscores.
|
2016-12-03 10:51:09 -05:00 |
|
Thomas Harte
|
81ee834530
|
As well as a bunch of logging, reinstated rotation position preservation across tracks.
|
2016-12-02 18:36:47 -05:00 |
|
Thomas Harte
|
93c573bfa9
|
Implemented missing status bits (other than the index hole), and a head loading delay for the Microdisc.
|
2016-12-01 21:13:16 -05:00 |
|
Thomas Harte
|
0a0775c3bd
|
Removed earlier hacky solution.
|
2016-12-01 20:16:11 -05:00 |
|
Thomas Harte
|
442986ee2c
|
Introduced a head loading path for 1793 machines.
|
2016-12-01 20:12:22 -05:00 |
|
Thomas Harte
|
82899f2f47
|
Ensured flag setting is atomic, removed duplication of interrupt request versus busy, found better names for the personality testers, unified delegate protocol.
|
2016-12-01 07:41:52 -05:00 |
|
Thomas Harte
|
b31fd11470
|
Fixed reporting of data request line, initial status values.
|
2016-11-30 22:39:55 -05:00 |
|
Thomas Harte
|
2222cb65d6
|
Split the status up into flags, assembled into a register upon demand. Attempted to implement some of the differences between the 1770/1772 and 1773/1793. Albeit with a motor fix still in place.
|
2016-11-30 22:26:02 -05:00 |
|
Thomas Harte
|
84cb07613d
|
Checked some documentation more thoroughly; the 1793 has quite different spin-up (/head load) semantics. So it's another distinct personality. Grrr.
|
2016-11-27 20:39:08 -08:00 |
|
Thomas Harte
|
02ba1f220f
|
The '72 seems to be a '70 with altered timing. So worth differentiating.
|
2016-11-27 21:06:17 +08:00 |
|
Thomas Harte
|
2c01f9dbed
|
Added meaningful TODOs.
|
2016-11-27 08:42:39 +08:00 |
|
Thomas Harte
|
2f459690d4
|
It would appear the 1770 and 1773 actually differ in relation to the (non-sensical) ability not to spin-up for a Type 2, and whether a side compare can occur. So the WD1770 class now requires a personality to be specified. Which it singly fails to honour.
|
2016-11-26 23:29:30 +08:00 |
|
Thomas Harte
|
d8ecc52de8
|
Temporarily disabled spin-down as harmful to the status register if following anything other than a Type 1 command.
|
2016-11-26 22:27:20 +08:00 |
|
Thomas Harte
|
b9677c9927
|
Consolidated interrupt request setting.
|
2016-11-26 09:41:53 +08:00 |
|
Thomas Harte
|
d5f9e0aa3b
|
Ensured there's no such thing as a zero-cycle operation, even if i don't yet know exactly what I should be doing.
|
2016-11-25 21:24:25 +08:00 |
|
Thomas Harte
|
4af678d2ed
|
Gave the Microdisc a clock signal, added just enough of force interrupt to avoid a spurious belief that a type 3 command has started.
|
2016-11-25 20:51:39 +08:00 |
|
Thomas Harte
|
d4a1961378
|
Added getters for the IRQ and DRQ lines plus a delegate to receive changes; adjusted code so that the two lines signal.
|
2016-11-21 13:21:49 +08:00 |
|
Thomas Harte
|
7eeaac23e7
|
Reversed myself. I once again do not think the clock is divided by 256 for envelopes.
|
2016-11-11 20:31:48 -05:00 |
|
Thomas Harte
|
77987bf31e
|
Decided to go with divide by 256 for the envelope counter after all.
|
2016-11-09 21:51:56 -05:00 |
|
Thomas Harte
|
77ce200fbb
|
Simplified/corrected AY tone/noise mixer logic, and made a new guess at the effect of reading registers that are smaller than 8 bits.
|
2016-11-09 21:21:17 -05:00 |
|
Thomas Harte
|
fa65cc2058
|
Resolved type conversion error.
|
2016-11-05 12:57:01 -04:00 |
|
Thomas Harte
|
30c670f8de
|
Ensured programmatic setting of the timers occurs during phase 2 _instead_ of counting.
|
2016-11-04 21:30:18 -04:00 |
|
Thomas Harte
|
21604376e6
|
Reintroduced clocking of the AY and boxed in the range of the master divider a little further.
|
2016-10-30 22:51:08 -04:00 |
|
Thomas Harte
|
ad00304e8a
|
Fixed 6522 countdown.
|
2016-10-28 21:05:42 -04:00 |
|
Thomas Harte
|
4fab794747
|
Added a direct-to-two-cycles emulation path for 6522 owners.
|
2016-10-27 21:13:25 -04:00 |
|
Thomas Harte
|
2eda0b3c86
|
Attempted to simplify the logic behind the most common 6522 usage.
|
2016-10-27 21:06:31 -04:00 |
|
Thomas Harte
|
fd823dc222
|
Settled on terminology.
|
2016-10-23 20:42:49 -04:00 |
|
Thomas Harte
|
b12f2f2796
|
Switched to more straightforward version of two-step loop, dealing with my mistaken dealing of when _master_divider&15 == 0 upon entry without adding an extra sanity check. Am also temporarily on non-modulo logic for tone generation, for a profiling test.
|
2016-10-23 20:32:48 -04:00 |
|
Thomas Harte
|
583db88299
|
Added a dispatch queue-powered Apple implementation of the async task queue, removed any mention of skip_samples in the AY since it isn't implemented.
|
2016-10-22 21:58:45 -04:00 |
|
Thomas Harte
|
33e628a096
|
Made an attempt to eliminate what amounts to manual division.
|
2016-10-21 22:16:44 -04:00 |
|
Thomas Harte
|
46a3c0922f
|
Slightly simplified code, fixed divider.
|
2016-10-21 22:12:44 -04:00 |
|
Thomas Harte
|
d7c0c49715
|
Might as well be consistent with divider loads.
|
2016-10-21 20:07:14 -04:00 |
|
Thomas Harte
|
782ef960e1
|
Sought both to [start to] optimise the AY and correct divider reloads. It turns out that conditionals aren't that troubling. But I can probably eliminate the counters.
|
2016-10-21 20:05:38 -04:00 |
|
Thomas Harte
|
cd59eb5f43
|
Implemented non-linear volume.
|
2016-10-19 23:07:51 -04:00 |
|
Thomas Harte
|
b59da7d4bc
|
Added some documentation.
|
2016-10-19 22:47:44 -04:00 |
|
Thomas Harte
|
08275c6241
|
Fixed mixer IO bit usage.
|
2016-10-19 22:22:15 -04:00 |
|
Thomas Harte
|
59162228ef
|
Reduced mask for clarity.
|
2016-10-19 22:14:05 -04:00 |
|
Thomas Harte
|
319d7c2b12
|
Fixed premature wrapping of the envelope, played about with whether that should be subject to a predivision by 256. It feels unlikely?
|
2016-10-19 22:12:51 -04:00 |
|
Thomas Harte
|
6073906c39
|
Commented and fixed mistake that would equate any noise divider > 32768 with 0.
|
2016-10-19 21:51:35 -04:00 |
|
Thomas Harte
|
101f168ea4
|
Made an attempt to tidy up.
|
2016-10-19 21:43:18 -04:00 |
|
Thomas Harte
|
ada37abe23
|
Made an attempt to implement noise and envelopes. Not quite right yet.
|
2016-10-19 21:13:22 -04:00 |
|
Thomas Harte
|
bd6e6674a0
|
Fixed signed shift assumption and noise-related register test.
|
2016-10-18 22:20:12 -04:00 |
|
Thomas Harte
|
9669a5ec9b
|
Switched to a more authentic interfacing to the AY.
|
2016-10-18 19:32:15 -04:00 |
|
Thomas Harte
|
43612e1ca2
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Made an attempt to eliminate conditionals (running before I can walk?) and started edging towards an envelope generator.
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2016-10-17 08:03:38 -04:00 |
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Thomas Harte
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9730e8247f
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Ensured propagation of synchronise messages, added enough to do plain tone. Probably. So: noise and envelopes missing. And it's all far too quiet.
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2016-10-15 21:04:21 -04:00 |
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Thomas Harte
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51bdac27ae
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Made some AY advances; it's now being polled for samples and collecting more information on what it needs to output.
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2016-10-15 17:45:39 -04:00 |
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Thomas Harte
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288d10c253
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Got some keyboard reaction.
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2016-10-14 21:44:15 -04:00 |
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Thomas Harte
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138eabcff4
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Continued in my effort to wire up a keyboard. Will need further to continue.
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2016-10-14 21:35:15 -04:00 |
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Thomas Harte
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d8e4c488c2
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Started iterating towards having an AY and a fully-working keyboard.
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2016-10-14 21:18:03 -04:00 |
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Thomas Harte
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922dd6a586
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Hit up the other two kinds of audio generator.
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2016-10-07 17:10:00 -04:00 |
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Thomas Harte
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79412dc84d
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Upped MFM clock cycles, switched back to using the typer for the ADFS and adjusted ADFS ROM slots.
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2016-09-28 21:28:34 -04:00 |
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Thomas Harte
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91235c7fd7
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Fixed issue whereby parts of data that merely looked like index or ID address marks within tracks caused a resynchronisation of the tokeniser.
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2016-09-27 07:36:37 -04:00 |
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Thomas Harte
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6330e5706c
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Fixed seek verify. First ADFS directory is visible.
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2016-09-25 21:44:46 -04:00 |
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Thomas Harte
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4db086949a
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Made an attempt to add MFM decoding to the 1770; ensured something is returned when reading the Plus 3 status register again.
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2016-09-25 21:38:52 -04:00 |
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Thomas Harte
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572d5587d9
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Made a first stab at enabling multi-disk machines and thereby obeying (some of) the Plus 3's status register.
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2016-09-25 21:24:16 -04:00 |
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Thomas Harte
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9bbcbd1001
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Renamed class, intending to turn a Disk::Drive into literally just that, and have a thing with a PLL that consumes events be a Controller.
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2016-09-25 20:05:56 -04:00 |
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Thomas Harte
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6084020ab3
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Added shift-break as a better way to boot suitable disks. Continued attempting to clean the 1770.
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2016-09-25 14:11:22 -04:00 |
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Thomas Harte
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a538b45213
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Sought to implement the verify step of type 1 commands.
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2016-09-25 09:54:49 -04:00 |
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Thomas Harte
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0918751802
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Fixed stepping out.
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2016-09-24 22:48:45 -04:00 |
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Thomas Harte
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9e1d4c8b01
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Fixed an initial setup error with seek.
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2016-09-24 22:43:12 -04:00 |
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Thomas Harte
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d50629e6aa
|
This is clearly the winning solution. Edited down.
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2016-09-24 22:36:38 -04:00 |
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Thomas Harte
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07ff5138b7
|
The catalogue now loads.
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2016-09-24 22:35:34 -04:00 |
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Thomas Harte
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1b69ad0fd4
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This attempts to implment sector reading. DFS reports an error.
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2016-09-24 22:29:02 -04:00 |
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Thomas Harte
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ce4100e5b9
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Fixed slots for DFS and ADFS to sideways RAM; continued working on the 1770 to get as far as trying to get the body of a sector.
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2016-09-24 22:04:54 -04:00 |
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Thomas Harte
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7154e8986e
|
Fixed stepping delay.
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2016-09-24 20:16:23 -04:00 |
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Thomas Harte
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53522e28e2
|
Performed an about-face on how this should probably be implemented. Now forsaking the state machine in favour of a macro'd switch-for-cooperative-event-based-messaging implementation. Let's see how this ends up looking.
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2016-09-24 20:12:45 -04:00 |
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Thomas Harte
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88bbeedad3
|
Set actual bit length.
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2016-09-22 21:28:23 -04:00 |
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Thomas Harte
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75eb62b577
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One painful step at a time, this now starts the disk rotating and gets as far as deciding whether it's about to head off on a read or a write.
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2016-09-22 21:25:31 -04:00 |
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