Thomas Harte
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a5038259bc
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Add admission.
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2023-08-21 19:30:34 -04:00 |
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Thomas Harte
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bb84a5a474
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Enable various ADB-controller interrupts.
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2023-08-21 15:35:13 -04:00 |
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Thomas Harte
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8578dfbf22
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Eliminate various other errant spaces.
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2023-05-16 16:40:09 -04:00 |
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Thomas Harte
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28c79b2885
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Eliminate redundant [space][tab] pairs.
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2023-05-12 14:14:45 -04:00 |
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Thomas Harte
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2b56b7be0d
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Simplify namespace syntax.
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2023-05-10 16:02:18 -05:00 |
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Thomas Harte
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cbf5a79ee8
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Takes a swing at improper key repeat.
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2021-02-28 16:46:09 -05:00 |
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Thomas Harte
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5d1970d201
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Adds a hacky different guess at how register access might work.
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2021-02-19 21:46:18 -05:00 |
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Thomas Harte
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2e9065b34c
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Increases number of fixed initial values.
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2021-02-18 22:48:53 -05:00 |
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Thomas Harte
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2a45e7a8d4
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Slows timer X, to what may or may not be correct.
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2021-02-15 16:40:27 -05:00 |
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Thomas Harte
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f8f0ff0fae
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Add timer X counting.
Still no interrupts.
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2021-02-15 16:29:25 -05:00 |
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Thomas Harte
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f5dcff2f29
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Honours interrupt vector.
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2021-02-15 15:05:56 -05:00 |
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Thomas Harte
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eccf5ca043
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Makes first effort to wire up the ADB vertical blank input.
However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
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2021-02-14 22:20:58 -05:00 |
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Thomas Harte
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c284b34003
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Resolves inability of ADB microcontroller to read its own ROM (!)
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2021-02-13 17:53:40 -05:00 |
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Thomas Harte
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2c4dcf8843
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Edges towards implementing an ADB device.
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2021-02-12 21:50:24 -05:00 |
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Thomas Harte
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e83b2120ce
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Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
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2021-02-10 21:46:56 -05:00 |
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Thomas Harte
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3c7f9a43ad
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Merge branch 'AppleIIgs' of github.com:TomHarte/CLK into AppleIIgs
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2021-02-08 18:43:27 -05:00 |
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Thomas Harte
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82312d3b59
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Provide a more convincing version of port output.
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2021-02-08 18:14:08 -05:00 |
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Thomas Harte
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93a80a30d3
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With correct divider appears to get reset requests posted.
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2021-02-07 23:05:01 -05:00 |
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Thomas Harte
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77b1efd176
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Sets sensible 'reset' values.
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2021-02-07 21:53:57 -05:00 |
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Thomas Harte
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acfab1dfb3
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Starts to make some effort at timers.
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2021-02-06 21:02:44 -05:00 |
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Thomas Harte
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819e9039ab
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Corrects printed target address for ZeroPageRelative.
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2021-02-04 20:54:31 -05:00 |
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Thomas Harte
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b8c6d4b153
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Rips out my high-level ADB microcontroller protocol implementation.
Adds just enough that the main computer validates the ADB controller as present and talking.
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2021-01-30 17:53:27 -05:00 |
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Thomas Harte
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5eddc92846
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Implements direction registers.
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2021-01-28 21:06:11 -05:00 |
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Thomas Harte
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dcc2fe0990
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Improves M50470 entry-point detection, adds test output.
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2021-01-26 21:29:17 -05:00 |
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Thomas Harte
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cc90935abd
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Starts to provide just a touch of reflection.
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2021-01-26 19:22:00 -05:00 |
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Thomas Harte
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413e42e1b6
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Attempts to fix BBC.
But thereby stops all ADB output.
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2021-01-25 22:34:03 -05:00 |
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Thomas Harte
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fc4bda0047
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Experimentally flipping interpretation of the output bit gives something closer to coherent.
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2021-01-25 22:02:39 -05:00 |
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Thomas Harte
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c8beb59172
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Attempts properly to track ADB bus activity.
Output is not yet a valid ADB stream. Work to do.
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2021-01-25 17:43:22 -05:00 |
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Thomas Harte
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8789ffda15
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Corrects performer storage, RMW/W confusion, implicit casts, port readback.
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2021-01-24 22:30:42 -05:00 |
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Thomas Harte
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e8e604dc3c
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Attempts to wire up M50470 and GLU.
Resulting in an unexpected interest in R15. Bugs to find, I guess.
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2021-01-24 18:07:05 -05:00 |
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Thomas Harte
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57e0fdfadc
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Ensures ADB microcontroller is clocked.
And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
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2021-01-23 22:55:12 -05:00 |
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Thomas Harte
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36aebe0ff9
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Posts cycle lengths.
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2021-01-23 21:58:52 -05:00 |
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Thomas Harte
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051d2b83f4
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Corrects TSX lookup.
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2021-01-23 15:45:21 -05:00 |
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Thomas Harte
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17b12120eb
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Corrects bit-selection shifts.
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2021-01-21 23:13:00 -05:00 |
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Thomas Harte
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6e9ce50569
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Corrects duration-based iteration.
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2021-01-21 23:05:43 -05:00 |
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Thomas Harte
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adef2e9b4e
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Starts formalising end conditions.
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2021-01-21 22:36:44 -05:00 |
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Thomas Harte
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0fafbf5092
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Completes M50740 instruction set.
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2021-01-21 19:08:38 -05:00 |
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Thomas Harte
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c10c161d39
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Implements ADC and SBC.
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2021-01-21 18:53:24 -05:00 |
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Thomas Harte
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04024ca159
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Adds BIT.
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2021-01-20 21:41:43 -05:00 |
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Thomas Harte
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64d556f60f
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Implements shifts and rotates.
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2021-01-20 21:39:13 -05:00 |
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Thomas Harte
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8564e7406b
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Corrects index-mode CMP, LDA.
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2021-01-20 21:32:46 -05:00 |
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Thomas Harte
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ebdb58d790
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Seemingly advances to the first indefinite loop.
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2021-01-20 21:18:52 -05:00 |
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Thomas Harte
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cf8afc70b2
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Takes a swing at BBC, BBS.
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2021-01-20 20:52:04 -05:00 |
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Thomas Harte
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4f02e8fbaf
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Knocks off the low-hanging instruction fruit.
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2021-01-20 20:41:35 -05:00 |
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Thomas Harte
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6e618a6bb7
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Adds a list of missing instructions.
Not looking too bad; subject to not yet having a strategy for interrupts, timing, nothing yet implemented for timers, IO ports...
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2021-01-20 20:37:35 -05:00 |
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Thomas Harte
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df1bc18fb3
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Pushes ahead to what will be my first interaction with the T flag.
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2021-01-20 20:27:09 -05:00 |
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Thomas Harte
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9f12ce2fb8
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Corrects RTS, adds the remainder of the direct flag manipulations.
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2021-01-20 20:16:55 -05:00 |
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Thomas Harte
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b9672c0669
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Gets beyond a prima facie convincing JSR/RET.
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2021-01-20 18:21:44 -05:00 |
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Thomas Harte
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e58608b25a
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Gets as far as executing a first loop.
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2021-01-20 18:15:24 -05:00 |
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Thomas Harte
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e502d76371
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Corrects immediate instruction length, muddles through to having to parse a second program segment.
Albeit with JSR not yet properly implemented.
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2021-01-19 22:12:18 -05:00 |
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