8787d85e64
Eliminates #undefs as being (i) unnecessary, now this is a source file; and (ii) incomplete in any case.
2018-08-17 22:24:42 -04:00
0e7f54f375
Implements STP and WAI, and ensures all unimplemented 65C02 instructions are NOP for all 65C02s.
2018-08-17 21:49:06 -04:00
b3bdfa9f46
Corrected: it's three-cycle 65C02 branches that ignore interrupts, not two.
2018-08-16 20:47:49 -04:00
592ec69d36
Causes the 65C02 not to accept interrupts immediately after untaken branches.
2018-08-15 22:42:04 -04:00
60e00ddd02
Correction: the test for not skipping an operand fetch requires a 65C02.
2018-08-15 22:07:17 -04:00
6806193dc2
Ensures that "Read/Modify/Write instructions absolute indexed in same page" take only six cycles on a 65C02.
2018-08-15 19:17:37 -04:00
c35dca783f
Ensures that page-crossing indexing no longer causes an extra read of an invalid address on the 65C02.
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It rereads the last byte of the instruction stream instead.
2018-08-15 18:47:53 -04:00
901e0d65b9
Documents all 6502 micro-operations.
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Also makes sure 1-cycle NOPs really, definitely are one cycle only on a 65C02 and eliminates OperationCopyOperandFromA as a redundant copy of OperationSTA.
2018-08-14 22:17:53 -04:00
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
1eca4463b3
Ensures NMI can no longer usurp BRK on 65C02s.
2018-08-14 19:33:48 -04:00
be01203cc1
Starts to expand the range of supported 6502s.
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This fully implements the NES 6502 because, well, it's virtually no extra work, and ensures that RDY takes effect on write cycles on 65C02s.
2018-08-13 22:17:22 -04:00
4b91910fab
Removes erroneous addition.
2018-08-10 23:27:09 -04:00
878c63dcd2
Ensures ADC and SBC decimal take an extra cycle on the 65C02.
2018-08-10 22:52:55 -04:00
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
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This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
8b50ab2593
Corrects (zero) behaviour.
2018-08-10 21:12:55 -04:00
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
6f838fe190
Implements INA and DEA.
2018-08-08 22:30:19 -04:00
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
e46bde35f5
Implements BBS and BBR.
2018-08-07 21:52:17 -04:00
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
5c881bd19d
Implements PLX, PLY, PHX and PHY.
2018-08-06 22:00:23 -04:00
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
633af4d404
The operations table is now per-instance.
2018-08-06 20:47:14 -04:00
76a73c835c
Forces 6502 consumers to declare which model — the original, 65C02 or 65SC02.
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All present machines use a regular 6502.
2018-08-06 20:06:07 -04:00
0b14850467
Corrects some comments.
2018-06-24 23:02:36 -04:00
9a91ae38c1
Differentiates reasons for a read to be four cycles.
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Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
2018-06-20 21:34:21 -04:00
ad9b0cd4e3
Eliminates all endashes.
2018-05-13 15:43:03 -04:00
5d6b5d9f10
Eliminates all emdashes in cross-platform code.
2018-05-13 15:34:31 -04:00
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
45be1c19df
Resolves undefined behaviour of a signed shift left.
2018-03-22 21:59:39 -04:00
0e73ba4b3e
Introduces proper 5/3 SCF/CCF behaviour for the Z80.
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While also `const`ing a bunch of things.
2018-03-09 09:47:00 -05:00
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
74dfe56d2b
Expands documentation of NMI setting.
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Given that it was previously incorrect, explains logic behind request_status_ and last_request_status_ setting. Also takes the opportunity to ensure that NMI is 'sampled' at the same time as IRQ; whether the next thing should be the NMI routine now occurs one cycle before the end of any instruction. That's an assumption for now. Testing to come.
2018-03-02 11:10:02 -05:00
b02e4fbbf6
Corrects NMI receipt to be genuinely edge triggered.
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Previously a caller that signalled NMI set multiple times would trigger multiple NMIs.
2018-03-01 22:04:56 -05:00
23c47e21de
Proceeds the ColecoVision to booting.
2018-02-24 18:14:38 -05:00
7dfbe4bb93
Ensures proper Boolean startup values for IFF1 and IFF2.
2017-11-29 20:32:55 -05:00
5aef81cf24
Commutes cross-platform #pragma marks to //MARK:s.
2017-11-12 15:59:11 -05:00
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
cb0f58ab7a
Corrects order-of-initialisation errors in the CPC (again), TextureBuilder, TextureTarget, Z80, MFM parser and binary tape player.
2017-11-10 22:57:03 -05:00
4cbc87a17d
Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
2017-11-10 22:20:44 -05:00
c0055a5a5f
Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code.
2017-11-09 22:04:49 -05:00
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
ad9df4bb90
Commutes uint8_t *, uint16_t *, uint32_t *, size_t, off_t and long to functional-style casts.
2017-10-21 22:30:15 -04:00
e983854e71
Converts all uint8_t and uint16_t casts to the functional style.
2017-10-21 21:50:53 -04:00
ab2bcb939f
Separates 6502Base into its constituent parts.
2017-09-04 11:08:33 -04:00
Thomas Harte
Thomas Harte